Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target.

Abstract: A computer readable medium containing program instructions for controlling a parametric equalizer is provided. Generally, a computer readable code is provided for displaying a composite equalization curve, wherein the composite equalization curve is formed from at least a first frequency filter with a first center frequency, a second frequency filter with a second center frequency, and a third frequency filter with a third center frequency. A computer readable code is provided for allowing a dragging movement of the first center frequency, the second center frequency, and the third center frequency.

Abstract: A channel memory length selection method for wireless communication systems is provided. The method comprises estimating an initial channel impulse response (CIR) for the wireless communication system; determining a first refined CIR with a first group of taps and a second refined CIR with a second group of taps based upon the initial CIR, number of the second group of taps being less than number of the first group of taps; and selecting either the number of the first group of taps or the number of the second group of taps as the channel memory length according to an energy concentration criterion in regard to the first refined CIR and the second refined CIR.

Abstract: A self-calibrating, adaptive equalization system for generating an ideal digital signal is disclosed. The adaptive equalization system includes an equalizer and a high-gain buffer. The equalizer includes a first equalizer loop that feeds-back a control voltage to the equalizer and the high-gain buffer that includes a second equalizer loop that feeds-back a high-pass-to-low-pass filter ratio signal. Each of the first and second equalizer loops has a high-pass and a low-pass filter, rectifying circuits for each of the filters, and an integrating circuit that compares signal energy output from the rectifiers. The adaptive equalization system generates an ideal digital signal.

Abstract: A method of synchronizing a feedforward filter (46) that receives a signal resulting from the transmission of a series of symbols through a channel, wherein the series of symbols includes a predetermined sequence of symbols includes the step of developing a plurality of samples from the received symbols (60), wherein a sequence of samples corresponds to the predetermined sequence of symbols. The method further includes the steps of estimating a channel impulse response from the plurality of samples, calculating a characteristic of the channel impulse response, and synchronizing (54) the feedforward filter in accordance with the estimated channel impulse response.

Abstract: Processing a received signal is disclosed. It is determined that a received signal does not satisfy a prescribed signal quality criterion. Based at least in part on the determination, an equalizer tap is not updated based on the received signal.

Abstract: Forward and backward equalization processes are effectively used in a communication system for equalizing a received signal of a frame including a known symbol part. The known symbol part is provided in a position other than both ends of the frame. An equalization filter unit acquires a signal of an equalization process result by performing an equalization filter process based on a signal serving as an equalization process target and a tap gain coefficient. An update unit updates the tap gain coefficient using a predefined algorithm. A first or second transmission unit transmits a received signal posterior or prior to the known symbol part to a first or second memory in a forward direction or reverse order.

Abstract: A partial response signaling system includes a transmitter circuit configured to equalize input data in response to a control signal and to transmit a partial response signal through a transmission medium; and a receiver circuit configured to recover an output data from the partial response signal and to generate the control signal based on the partial response signal and an expected signal to output the control signal to the transmitter circuit.

Abstract: The present invention is a method and computer program for equalizing group delay and magnitude of a system for which a system response is known. The method and computer program are implemented via a finite impulse response (“FIR”) filter for the system, and the method broadly comprises the steps of: evaluating a desired response for the system as a function of an amplitude of the system and a phase of the system; separating the phase of the system into a linear component and a non-linear component; performing a first optimization by minimizing a weighted error between a desired response for the system and a cascaded response for the system as a function of an equalizing filter and a phase slope so as to obtain at least one local smallest error E(?) as a function of phase slope; and once the local smallest error E(?) is known, performing a second optimization to locate any existing global smallest error, wherein the global smallest error is within a set distance from the local smallest error.

Abstract: An adaptive feedback estimation and cancellation (AFEC) apparatus includes: a controller for generating and outputting control information by using a synchronization signal from an external synchronization acquisition unit and base station information, in order to remove a feedback signal that exists in a forward/reverse repeater signal to be repeated and then send the forward/reverse repeater signal; a first feedback prediction canceller for adaptively removing a feedback signal that exists in the forward repeater signal based on the control information from the controller and automatically adjusting the gain of the forward repeater signal; and a second feedback prediction canceller for adaptively removing a feedback signal that exists in the reverse repeater signal based on the control information from the controller and automatically controlling the gain of the reverse repeater signal.

Abstract: A method of synchronizing a feedforward filter that receives a signal resulting from the transmission of a series of symbols through a channel, wherein the series of symbols includes a predetermined sequence of symbols includes the step of developing a plurality of samples from the received symbols, wherein a sequence of samples corresponds to the predetermined sequence of symbols. The method may further include the steps of estimating a channel impulse response from the plurality of samples, wherein the channel impulse response estimate is represented by a plurality of correlation values, identifying a maximum correlation value from the plurality of correlation values, defining a window relative to the maximum correlation value, calculating a characteristic of the correlation values within the window, and synchronizing the feedforward filter in accordance with the characteristic.

Abstract: In one embodiment, a receiver has an equalizer, a tap-averaging block, a delay buffer, and a filter. The equalizer receives an input signal from upstream processing and generates sets of filter coefficients. Each set of filter coefficients is adaptively generated by 1) filtering the received signal to generate an equalized signal, 2) calculating an error of the equalized signal, and 3) generating a new set of coefficients based on the error of the equalized signal. The sets of filter coefficients are output to the tap-averaging block, which averages groups of the sets of filter coefficients to generate sets of averaged filter coefficients, where each averaged set is output to the filter. The filter receives a time-delayed version of the input signal from the delay buffer and applies the current set of averaged filter coefficients to the time-delayed signal. The filtered signal is then output to downstream processing.

Abstract: Equalizers are provided including an N-tap feed forward filter, an M-tap feed backward filter, an L-tap filter, a control unit and an accumulator. The control unit is configured to connect the L-tap filter to the N-tap feed forward filter or the M-tap feed backward filter based on multipath information present in a communications channel. The accumulator is configured to sum output signals from at least one of the N-tap feed forward filter, the M-tap feed backward filter and the L-tap filter and to output a summation result. Related digital receivers, methods and computer program products are also provided.

Abstract: The linear equalizer (LE) coefficients for code-division-multiplexed (CDM) pilot systems can be determined based upon frequency-domain calculations involving channel impulse responses. A channel impulse response can be formed at the mobile terminal by suitably filtering and despreading the received baseband signal with respect to the pilot Walsh channel. The channel frequency response is then determined based on the fast Fourier transform (FFT) of the channel impulse response. Frequency-domain equalizer coefficients can be determined from the channel frequency response. The frequency-domain equalizer coefficient can be utilized to determine time-domain equalizer coefficients to implement the equalizer in time domain, or be utilized to implement the equalizer in frequency domain.

Abstract: A technique to perform a guided partial response target search for characterizing a read channel of a disk drive. A target adaptation scheme pre-selects a plurality of targets from a pool of potential targets based on certain criteria and the selected targets are sorted in linear gradient orders. When target adaptation is being performed by comparing the equalizer output with an ideal reconstructed signal, a difference value sets a gradient vector that is used to determine which direction to move along the sorted list of targets to select the next target.

Abstract: A waveform equalizer includes a filter unit, an error estimation unit, a tap coefficient storage unit, and an update amount calculation unit which includes an intermediate calculation unit and an update amount setting unit. Coefficient update amount ?Ci(n) for an ith tap is calculated according to an equation ?Ci(n)=?i(n)×?×e(n)×x*(n?i) with the multiplication by ?i(n) being performed by the update amount setting unit. Here, 0<?i(n)?1, and ?i(n) is a function f(Ci(n?1)) which monotonically increases with Ci(n?1).

Abstract: A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.

Abstract: A method and apparatus for a receive equalizer of a gigabit transceiver that is reconfigurable to support multiple communication standards. Communication standards having variable common mode and coupling requirements are accommodated through the use of reconfigurable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), that provide a plurality of reconfigurable transceivers that are programmable through configuration, or partial reconfiguration, events. The reconfigurable transceivers apply internally generated common mode voltage signals to the differential input in support of the various communication standards.

Abstract: A signal processing method, receiver and equalizing method are provided. The receiver comprises an estimator estimating a channel coefficient matrix from a received signal, a first calculation unit determining a channel correlation matrix based on the channel coefficient matrix a converter converting the channel correlation matrix into a circulant matrix. A second calculation unit determines equalization filter coefficients by applying a first transform to the real parts of a first subset of the terms in the first column of the circulant matrix and by applying a second transform to the imaginary parts of a second subset of the terms in the first column of the circulant matrix. An equalizer equalizes the received signal by using the determined equalization filter coefficients.

Abstract: Equalization circuitry that includes an analog equalizer and a decision feedback equalizer (DFE) is provided for high-speed backplane data communication. The analog equalizer reduces the number of taps that are required by the DFE, which lessens the error propagation of the DFE. Furthermore, the DFE includes a summing circuit and flip-flop circuitry. The flip-flop circuitry may be used as part of a phase detector by clock and data recovery circuitry. The summing circuit may further be embedded into the flip-flop circuitry to reduce the feedback path delay, thereby allowing for higher speed operation. The DFE may be extended to multiple taps by including additional flip-flops.

Abstract: An equalizer includes at least two first mutually interfering equalizer sections, and at least two second interference-correcting equalizer sections, arranged in series. Each of the second equalizer sections corresponds with one first equalizer section, such that although each corresponding equalizer has the same center frequency, the second equalizer sections have an equalization response opposite the interference effect, and the gain of the corresponding second equalizer at the respective common center frequency contains the negative gain of at least one first equalizer adjacent to the corresponding first equalizer at the center frequency of the corresponding first equalizer.

Abstract: An equalizer generates an equalized sample from a plurality of received samples in which a forward equalizer filters a received sample to generate a FE output. A feedback equalizer filters the equalized sample to generate a FBE output. An integrator adds the FE and FBE outputs to generate the equalized sample. The feedback equalizer comprises first and a second sub-filters. The first sub-filter has a first bit-width capability to generate a first FBE output from the equalized sample. The second sub-filter has a second bit-width capability to generate a second FBE output from the equalized sample. The first bit-width is higher than the second bit-width, and the first and second FBE outputs jointly organize the FBE output.

Abstract: A method for synchronizing symbols at the output of a blind equalizer, the method being characterized by the following steps: on sending, inserting into a succession of sent symbols, one or more known sequences of symbols repeated in said succession of symbols; detecting said one or more known sequences at the output of said blind equalizer; deducing any shifting of the symbols at the output of the blind equalizer from the result of said detection; and retiming the symbols at the output of the blind equalizer as a function of the deduced shift.

Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: Bit-Edge Zero Forcing Equalizer. A novel solution is presented by which a BE-ZFE (Bit-Edge Zero Forcing Equalizer) is employed to drive an error term within a data signal to an essentially zero value. This new BE-ZFE looks at values of data that occur at the bit edges of a data signal and drives the associated error term to zero. The new BE-ZFE is appropriately implemented within communication systems that are phase (or jitter) noise limited. Some examples of such communication systems include high-speed serial links one type of which serviced using a SERDES (Serializer/De-serializer) where data that is originally in a parallel format is serialized into a serial data stream and then subsequently de-serialized back into a parallel data stream.

Abstract: A filter equalization technique for an analog signal path, such as in an instrument that simultaneously measures a signal over a band of frequencies, uses magnitude measurement data for high frequency bands for which phase-calibrated sources are not readily available. A sinusoidal signal source together with an accurate power meter is used to provide a stepped frequency input over a desired frequency band to the analog signal path with an accurate measured magnitude. The output of the analog signal path is digitized and the resulting frequency magnitudes are computed. Then the resulting power meter results are deducted from the frequency magnitudes measured each time by the instrument to determine the magnitude response of the analog signal path. Using a Hilbert transform the corresponding phase response is determined based on a minimum phase assumption over the desired frequency band. From the magnitude and phase responses an inverse or digital equalization filter may be designed for the analog signal path.

Abstract: A method is provided for analyzing the channel impulse response of a transmission channel using a time-discrete adaptive equalizer connected in series to the transmission channel, which it equalizes. The method includes determining the IIR filter coefficients (an) of a recursive filter portion and the FIR filter coefficients (bn) of a non-recursive filter portion of the time-discrete adaptive equalizer, at least partially allocating the IIR filter coefficients (an) and the FIR filter coefficients (bn) to input vectors for a discrete Fourier transformation, determining output vectors from the input vectors using a discrete Fourier transformation, forming discrete transmission function values by division of the output vectors, and determining the channel impulse response from the channel transmission function using an inverse discrete Fourier transformation.

Abstract: A method and system for retrieving a desired user data symbol sequence from a received signal are disclosed. In one embodiment, the method includes i) receiving a channel modified version of a transmitted signal comprising a plurality of user data symbol sequences, each being encoded with a user specific known code, ii) determining an equalization filter directly and in a deterministic way from the received signal and iii) applying the equalization filter on the received signal to thereby retrieve the transmitted signal.

Abstract: A system and method of signal denoising using Independent Component Analysis (ICA) and fractal dimension analysis of the signal components in the ICA domain is described. The signal components with fractal dimensions higher than a pre-determined threshold are automatically attenuated or canceled in order to alleviate the noise in the signal. The denoised signal is reconstructed using inverse ICA transform of the signal components.

Abstract: An integrated circuit includes a decision feedback equalizer (DFE) including a first and second digital equalizer logic including circuitry to compensate first and second bits in a received stream and to provide first and second sign bits. The second equalizer logic can run concurrently and can be connected in parallel relative to the first equalizer logic. The second equalizer logic can include a low and high sign bit pipelines providing first and second conditional sign bits by assuming a low and high sign bits, respectively, for a first bits being concurrently processed by the first equalizer logic and a sign bit selection element to select between the first and second conditional sign bits based on the sign bit outcome of the first equalizer logic. The first and second pipelines compensate bits using compensation weights chosen using most recent first and second conditional sign bits and sign bit outcome.

Abstract: A partial response transmission system in which a data signal is transmitted from a transmission side to a reception side through a transmission medium, includes an equalizing circuit provided in the transmission side or the reception side, and configured to adjust a transfer function for an entire system including the transmission medium to a desired transfer function by delaying input data over a plurality of states in units of a period equal to a transition time of a single bit response by the desired transfer function of a partial response transmission and by weighing and adding data in the plurality of stages; and a deciding circuit provided in the reception side and configured to decide an output data from a signal received through the transmission medium through processing under consideration of the desired transfer function.

Abstract: This invention relates to an equalization apparatus, an equalization method and a receiver using the same. Two equalizers are applied to the equalization apparatus to cover two clusters of a channel. The weights of the two equalizers are calculated by channel gains of the whole channel based on the minimum mean square error criterion. Therefore the interference of the whole channel due to different clusters can be reduced enormously.

Abstract: Disclosed is a minimum mean square error (MMSE) equalizer and method for single-user detection of a signal received from a downlink code-division multiple access CDMA channel. The equalizer includes a Kalman filter having an input coupled to the received signal for generating a best linear unbiased estimate of a transmitted chip sequence for a single user. A reduced computational complexity Kalman filter embodiment is also disclosed that only periodically updates a Kalman filter prediction error covariance matrix P(k|k?1), a Kalman filter filtering error covariance matrix P(k|k) and the Kalman gain K(k).

Abstract: The span of a linear transversal equalizer filter moves according to the current positions of the multi-paths to a receiver. The alignment of the filter span is measured quantitatively with respect to the current positions of the multi-paths. Adjustments are made to the filter span to enable the linear transversal filter to capture most of the available energy of the transmitted signal. The low-pass-filtered magnitudes of tap weights of the linear filter are multiplied with values of a function which has zeroes at desired points for the larger tap weights, and a gradient of the function at its zeroes being non-zero. The magnitude of the alignment measurement signal is used as a quantitative measure of the alignment of the equalizer span, while the sign of the alignment measurement signal can be used to decide the direction that the span should be moved in.

Abstract: An equalizer may include, filter an input data signal based on a plurality of filtering coefficients, and outputs an output data signal, determine whether filtering coefficients satisfy a condition in response to a bit selection signal, and output the filtering control signals based on the determination result, and generate the filtering coefficients, estimate channels based on the input data signal and update the filtering coefficients based on the estimation results.

Abstract: A transmitter architecture includes an equalizer and a D/A converter, for high-speed transmission of data across a channel. The equalizer includes a two-tap MAC as part of an N-stage, two-way interleaved FIR filter. The two-tap MAC provides substantial power and area savings over conventional MAC-based FIR filter designs, and may be implemented in short or long communications channels. The D/A converter is decoupled from the equalizer. Its N-bit, binary-weighted driver includes matched unit current generation cells, all of which are fully utilized during each digital-to-analog conversion. The D/A converter remains unchanged, even when the characteristics of the equalizer are changed.

Abstract: Disclosed are a system, method and device for generating an equalized signal from an input signal. Symbols in the equalized signal may be detected on each of a sequence of symbol intervals to recover a symbol value in the symbol interval. A feedback coefficient may be applied to a symbol value recovered in a previous symbol interval to generate the equalized signal in a current symbol interval. The feedback coefficient may be generated based, at least in part, on an estimated error associated with the equalized signal. The estimated error associated with the equalized output signal from among a plurality of candidate estimated error values.

Abstract: In a channel equalizer applicable to a digital television receiver, a forward filter and a backward filter perform filtering to an input signal and a predetermined signal. A Viterbi decoder corrects errors during a transmission procedure in a blind mode. A training symbol storing block stores training symbols. An output signal of the Viterbi decoder and symbols are provided to the backward filter in accordance with a blind mode or a training mode. A Kalman gain is calculated in a Kalman gain calculating block and an error signal is calculated by comparing an equalized signal, symbols, and the output signal of the Viterbi decoder with one another. A tap coefficient is updated by using the calculated error signal and the Kalman gain.

Abstract: An adaptive channel equalization technique and method for wideband passive receivers is disclosed that reduces and tends to minimize distortions caused by circuitry within passive digital receivers. This equalization architecture provides an adaptive equalization solution for a wideband passive channel that receives unknown signals from the RF environment both temporally and spectrally. A wideband chirp signal or calibration signal is periodically injected to capture the spectral response of the receiver channel as it varies from the distortions induced over time and temperature for synthesis of equalization filter coefficients. Thus, the channel equalization is performed independent of receiver signal source and is employed to minimize digital receiver signal measurement distortions across the passband by providing an equalization filter whose magnitude and phase response compensates for the channel distortions of the passive data collection system.

Abstract: An eye opening measurement technique, that does not interrupt a receiver's normal operation, is used as a metric for optimizing any selected parameters of the receiver's operation. If eye opening size decreases, as a result of a change to a receiver parameter, the polarity for stepwise changes is reversed such that the next change is in the opposite direction. Other types of search procedures can be used. Eye opening size is the difference between the eye's upper and lower edges. Measurement of eye opening size is accomplished using a data and auxiliary slicer that find each “edge” of an eye opening based upon the slicers' level of agreement. Depending upon the level of agreement, and whether symbols of the upper or lower region of the eye are counted, the threshold of the auxiliary slicer can be adjusted in the direction necessary to converge on the eye edge sought.

Abstract: In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.

Abstract: There are provided a phase-compensation decision feedback channel equalizer. The phase-compensation decision feedback channel equalizer equalizes phases of signals outputted from a feedforward filter and a feedback filter regardless of a phase distorted by a carrier wave and a ghost, thereby satisfying the same ghost removal performance.

Abstract: An apparatus for automatically selecting one of a standard decision directed mode and a soft dd mode in a decision feedback equalizer for receiving a data signal comprises an equalizer for providing a DFE output signal and having a control input responsive to a control signal exhibiting a first value for selecting the standard dd mode and a second value for selecting the soft dd mode. The equalizer includes a lock detector having an output for providing a lock signal indicative of equalizer convergence. The apparatus includes a mode selector having an input coupled to the lock detector output and having an output coupled to the control input for providing an output signal exhibiting one of the first and second values depending upon characteristics of the lock signal.

Abstract: An adaptive digital filter includes a filtering circuit and a coefficient renewal circuit. The filtering circuit has a coefficient a defined by a fundamental formula: a[n+1]=a[n]+?·e[n]·q[n]/p[n]. ? is a number greater than 0 and smaller than 2, e[n] is a difference between the input and the output of the filter, and q[n] and p[n] are formulas. The renewal circuit calculates a renewal value of the coefficient a. The coefficient renewal circuit calculates 2m (m is an integer) greater than p[n] in the fundamental formula, and also calculates the renewal value of the coefficient a in accordance with an execution formula: a[n+1]=a[n]+?·e[n]·q[n]/2m in place of the fundamental formula.

Abstract: A read channel of a magnetic data storage device includes a filter to provide equalization of the signal being detected from the magnetic media. The filter utilizes coefficients for the filter response. The filter coefficients may drift sideways over time. The drift is detected and a correction is implemented by imposing a leakage on the coefficients to re-center the filter response. The leakage sign differs depending on the direction of drift detected.

Abstract: A read channel of a magnetic recording apparatus includes a filter that uses filter coefficients to process the data detected by a read head from the magnetic recordable media. The coefficients change with time and circumstances. When data is read and found to pass error detection, the filter coefficient set used for the data is stored in a memory as a last good coefficient set. Upon failure of the filtering process, the coefficient set used is replaced with a coefficient set stored in the memory as the last good coefficient set.

Abstract: The present invention provides an apparatus for channel equalization and method thereof, by which a digital signal received via a plurality of antennas is equalized. The present invention includes receiving digital transmission signals using a plurality of antennas, respectively, initializing equalizer coefficients and equalizing the received signals respectively, adding the equalized signals together, predicting a noise amplified in the equalizing step, and generating a final output signal by removing the predicted noise from a value resulting from adding the equalized signals together. Therefore, the present invention performs equalization using a plurality of antennas, thereby enhancing the signal to noise ratio of the final output and facilitating the equalization of the severely distorted channel.

Abstract: Computing optimal Linear Equalizer (LE) coefficients gopt from a channel estimate h. A channel impulse response h is first estimated based upon either a known training sequence or an unknown sequence. The channel estimate is formulated as a convolution matrix H. The convolution matrix H is then related to the LE coefficients in a matrix format equation, the matrix format equation based upon the structure of the LE, the convolution matrix, and an expected output of the LE. A Fast Transversal Filter (FTF) algorithm is then used to formulate a recursive least squares solution to the matrix format equation. Computing the recursive least squares solution yields the LE coefficients using structured equations.

Abstract: A signal processing device for processing a passband signal to generate an equalized signal includes a passband adaptive equalizer for generating the equalized signal according to the passband signal, including at least one feed-forward equalizer (FFE) and one feedback equalizer (FBE), and a multilevel quantizer coupled with the passband adaptive equalizer for selectively utilizing a single predetermined threshold or a plurality of multiple predetermined thresholds to quantize the equalized signal in order to generate a sliced signal.

Abstract: A testing apparatus for testing a device under test is provided, wherein the testing apparatus includes: a comparator for receiving a signal output from the device under test and converting the signal into a logic signal by comparing the signal with a first reference voltage; a driver for amplifying a logic signal to be output to the device under test on the basis of a second reference voltage and outputting to the device under test; a comparator setting unit for determining the first reference voltage so as to compensate for a delay amount of a reception signal received from the device under test and setting the comparator to be the first reference voltage; and a driver setting unit for determining the second reference voltage on the basis of the reference voltage of the comparator and setting the driver to be the second reference voltage.