Equalizer Patents (Class 708/323)
  • Patent number: 7450634
    Abstract: An equalizer and corresponding methods is arranged and constructed to mitigate adverse effects of a wireless channel (300). The equalizer includes a delay line (503) coupled to an input signal (501) and comprising a delay circuit coupled to an output combiner (507) that is operable to provide an interim signal (g0 . . . gN) and a feed forward circuit (505) coupled to the delay line and operable to provide a feed forward signal (506) that comprises a hard decision scaled according to a scaling factor corresponding to an estimate of channel parameters, wherein the output combiner is operable to combine the feed forward signal and the interim signal to provide an output signal (509) that is compensated for an adverse effect of the wireless channel on the input signal.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: November 11, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Timothy R. Miller, Paul R. Runkle
  • Patent number: 7443913
    Abstract: An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: October 28, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Bhavesh G. Bhakta, Sridhar Ramaswamy, Robert F. Payne, Song Wu
  • Patent number: 7426236
    Abstract: A signal processing apparatus includes an input circuit to receive an input signal, and a high-pass filter responsive to the input circuit. The high-pass filter includes M taps to filter precursor intersymbol interference (ISI), one main tap and N taps to filter postcursor ISI. Each of n taps of the N taps is limited to a range of between ?1 and 0. The signal processing apparatus includes a decision feedback equalizer. The decision feedback equalizer includes a decision circuit responsive to the high-pass filter, and a feedback filter responsive to the decision circuit. The decision circuit is responsive to the feedback filter.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: September 16, 2008
    Assignee: Marvell International Ltd.
    Inventor: Runsheng He
  • Patent number: 7421022
    Abstract: A continuous time electronic dispersion compensation architecture using feed forward equalization and a non-linear decision feedback equalization forms an output signal by a linear combination of successively delayed versions of the input signal and the sliced output signal weighted by appropriate coefficients. A selected number of taps in the mixer used to generate a corresponding number of coefficients for use in the feed forward equalizer are held to a selected voltage to ensure that the coefficients associated with these two taps do not drift. This causes the other coefficients to converge to a unique minimum square error value. In one embodiment the selected voltage is the maximum system voltage.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: September 2, 2008
    Assignee: Inphi Corporation
    Inventors: Prashant Choudhary, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit Shanbhag, Qian Yu
  • Patent number: 7421019
    Abstract: A hierarchical adaptive equalizer and a design method thereof are disclosed. The design method divides N delay elements into a plurality of adaptive algorithms, each of the adaptive algorithms having ? delay elements. The design method logically structures a hierarchical tree with the adaptive algorithms. The hierarchical tree comprises ? levels. A top first level of the hierarchical tree comprises ???1 adaptive algorithms. A top second level of the hierarchical tree comprises ???2 adaptive algorithms. A bottom level of the hierarchical tree comprises an adaptive algorithm.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: September 2, 2008
    Assignee: Chung Shan Institute of Science and Technology, Armaments Bureau, M.N.D.
    Inventors: Chien-Hsing Liao, Wei-Min Chang, Tai-Kuo Woo, Shih-Che Lin, Jyh-Horng Wen
  • Patent number: 7406122
    Abstract: An equalizer is provided which is capable of making a filter factor to be set in the equalizer having an equalizing filter converge rapidly and a method is provided for setting an initial value for the rapid convergence of the filter factor. In the equalizer having a filter factor computing device to compute a filter factor for an equalizing filter, and a differential detecting circuit to generate a differential signal between a signal output from the equalizing filter and a common pilot diffusing code, an initial value for the filter factor computing device is generated and set by a multipath timing detecting circuit, a reverse diffusing section, and a channel estimating device being operated based on a received signal.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: July 29, 2008
    Assignee: NEC Corporation
    Inventors: Shinya Shimobayashi, Mariko Matsumoto
  • Patent number: 7400694
    Abstract: An eye opening measurement technique, that does not interrupt a receiver's normal operation, is used as a metric for optimizing any selected parameters of the receiver's operation. If eye opening size decreases, as a result of a change to a receiver parameter, the polarity for stepwise changes is reversed such that the next change is in the opposite direction. Other types of search procedures can be used. Eye opening size is the difference between the eye's upper and lower edges. Measurement of eye opening size is accomplished using a data and auxiliary slicer that find each “edge” of an eye opening based upon the slicers' level of agreement. Depending upon the level of agreement, and whether symbols of the upper or lower region of the eye are counted, the threshold of the auxiliary slicer can be adjusted in the direction necessary to converge on the eye edge sought.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: July 15, 2008
    Assignee: Synopsys, Inc.
    Inventors: Jeffrey Lee Sonntag, John Theodore Stonick, Daniel Keith Weinlader
  • Patent number: 7386044
    Abstract: A Decision Feedback Equalizer (DFE) system includes a DFE and a DFE coefficients processor. The DFE receives an uncompensated signal and operates upon the uncompensated input using DFE coefficients to produce an equalized output. The DFE coefficients processor formulates a channel estimate as a convolution matrix H. The DFE coefficients processor determines a Feed Back Equalizer (FBE) energy constraint based upon the channel estimate. The DFE coefficients processor relates the convolution matrix H to the DFE coefficients in a matrix format equation, the matrix format equation based upon the structure of the DFE, the convolution matrix, an expected output of the DFE, and the FBE energy constraint. The DFE coefficients processor formulates a recursive least squares solution to the matrix format equation and computes the recursive least squares solution to the matrix format equation to yield the DFE coefficients.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: June 10, 2008
    Assignee: Broadcom Corporation
    Inventor: Nabil R. Yousef
  • Publication number: 20080133631
    Abstract: An equalizer for equalizing an input signal includes an infinitive impulse response (IIR) filtering portion for filtering the input signal to produce N filtered outputs; a gain-adjusting portion coupled to the IIR filtering portion with N gains for adjusting the N filtered outputs to produce N gained outputs, respectively; and an adder for summing the N gained outputs to generate an equalized output signal. N is an integer larger than 2.
    Type: Application
    Filed: October 16, 2007
    Publication date: June 5, 2008
    Applicant: MStar Semiconductor, Inc.
    Inventors: Hung-Kun CHEN, Bo-Ju Chen, Zhi-Ren Chang
  • Patent number: 7382827
    Abstract: Directly computing Feed Forward Equalizer (FFE) coefficients and Feed Back Equalizer (FBE) coefficients of a Decision Feedback Equalizer (DFE) from a channel estimate. The FBE coefficients have an energy constraint. A recursive least squares problem is formulated based upon the DFE configuration, the channel estimate, and the FBE energy constraint. The recursive least squares problem is solved to yield the FFE coefficients. The FFE coefficients are convolved with a convolution matrix that is based upon the channel estimate to yield the FBE coefficients. A solution to the recursive least squares problem is interpreted as a Kalman gain vector. A Kalman gain vector solution to the recursive least squares problem may be determined using a Fast Transversal Filter (FTF) algorithm.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: June 3, 2008
    Assignee: Broadcom Corporation
    Inventors: Nabil R. Yousef, Ricardo Merched
  • Patent number: 7369607
    Abstract: Various methods and apparatus are described that use a filter. A receiver may be configured to receive multi-tone signals. The receiver has a Time Domain Equalizer filter employing an algorithm to shorten a length of an incoming impulse response to equal to or less than a guard period by calculating a minimum mean square error solution in combination with measuring an inter-symbol interference of a channel.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: May 6, 2008
    Assignee: 2Wire, Inc.
    Inventor: Hossein Sedarat
  • Patent number: 7346104
    Abstract: Disclosed is an adaptive receiving MIMO (multi input and multi output) system and method which decides a symbol detecting order so as to estimate the symbol having the minimum summation of weights of least square errors at the time of estimating the symbol for respective equalizers provided in parallel by the number of transmit antennas, and updates filter tap coefficients based on the RLS algorithm according to the detecting orders. Therefore, the filter tap coefficients are directly updated without tracking channels in the time-varying channel environment, and accordingly, detection performance very similar to those of the channel tracking and conventional V-BLAST scheme is provided with reduced complexity.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: March 18, 2008
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hee-Jung Yu, Ji-Hoon Choi, Yong-Hoon Lee
  • Patent number: 7342981
    Abstract: A digital receiver, that may be used to receive VSB/QAM digital television signals, includes an adaptive fine carrier recovery circuit that compensates for deviations in the carrier frequency or phase. The carrier recovery circuit de-rotates a signal including phase errors. Estimations of phase errors are filtered using a filter whose gain and bandwidth are adjusted adaptively. This allows the carrier recovery circuit to track phase/frequency offset without introducing significant jitter. In one embodiment, the receiver includes a DFE, and the adaptive carrier recovery circuit mitigates instability that might be associated with the DFE.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: March 11, 2008
    Assignee: ATI Technologies Inc.
    Inventors: Supat Wongwirawat, Azzedine Touzni, Mark Hryszko, Raul A. Casas, Yiwen Yu
  • Patent number: 7342983
    Abstract: A digital filtering apparatus and method for digitally filtering out undesirable or invalid data from data signal lines. The digital filtering apparatus includes a digital delay element having one or more outputs, a comparator connected to the outputs of the digital delay element, and a final stage connected to the output of the comparator and the outputs of the digital delay element. The digital filtering apparatus recognizes and filters out invalid data from data received by the digital delay element, and allows valid data to pass through the filter. Data is considered invalid data if its logical data state transition has a duration less than the clock setting of the digital filtering apparatus. The clock setting can be established by the number of active delay components in the digital delay element. The inventive digital filtering apparatus represents an improvement over conventional analog filters, e.g., in manufacturing efficiency and filtering performance.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: March 11, 2008
    Assignee: Agere Systems, Inc.
    Inventor: Tony S. El-Kik
  • Patent number: 7336899
    Abstract: A method and apparatus for determining the dispersion characteristics of minimum phase filters using substantially only an amplitude response of a minimum phase filter under test includes fitting an amplitude spectrum of the minimum phase filter with a substantially straight line curve, and determining the dispersion characteristics of the minimum phase filter using the straight line curve and the relationships determined by the inventors. Various inventive equations determined by the inventors representative of the relationship between an amplitude response of a minimum phase filter and the dispersion characteristics of the minimum phase filter are used for determining the dispersion characteristics of the minimum phase filter.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: February 26, 2008
    Assignee: Lucent Technologies Inc.
    Inventors: Gadi Lenz, Magaly Spector
  • Patent number: 7330506
    Abstract: The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs variable delay FIR equalizer in the transmitter module to increase the system performance in channel communications.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: February 12, 2008
    Assignee: Synopsys, Inc.
    Inventors: James Gorecki, John T. Stonick
  • Patent number: 7321612
    Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: January 22, 2008
    Assignee: Broadcom Corporation
    Inventors: Davide Tonietto, Ali Ghiasi
  • Patent number: 7317769
    Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: January 8, 2008
    Assignee: Broadcom Corporation
    Inventors: Davide Tonietto, Ali Ghiasi
  • Patent number: 7305030
    Abstract: An equalizing apparatus includes an equalizer which has a plurality of adjustable tap weights that equalizes a received signal based on values of the adjustable tap weights, a tap weight update calculation unit coupled to the equalizer and which determines tap weight updates for use in adjusting the tap weights during operation of the equalizer, an offset memory that stores one or more tap weight update offset values and a summer coupled to the tap weight update calculation unit and to the offset memory. The summer combines each of the tap weight updates with one of the tap weight update offset values to produce modified tap weight updates which, in turn, are provided to the equalizer to adjust the tap weights.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: December 4, 2007
    Assignee: The Boeing Company
    Inventor: Susan E. Bach
  • Patent number: 7301997
    Abstract: A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.
    Type: Grant
    Filed: September 11, 2001
    Date of Patent: November 27, 2007
    Assignee: Vitesse Semiconductor Corporation
    Inventors: John S Wang, Sudeep Bhoja, Shanthi Pavan
  • Patent number: 7289555
    Abstract: A method for processing a signal includes receiving a signal from a channel at a channel speed and providing error adjustment to the signal. The method includes sampling the signal at a speed less than the channel speed to yield sampled scalar data. The signal is sampled at a first phase. The method includes determining a sampled scalar error associated with the signal at a second phase. The difference between the first phase and the second phase comprises a delay. The method also includes forming a cross-correlation vector from the sampled scalar error and the sampled scalar data at a vector speed. The vector speed is less than the speed at which the signal is sampled. The method also includes determining compensation information for the error adjustment. The compensation information is based on the cross-correlation vector, and the compensation information is determined at the vector speed.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: October 30, 2007
    Assignee: Fujitsu Limited
    Inventor: Yasuo Hidaka
  • Patent number: 7286596
    Abstract: In a training operation for optimizing a multiplication coefficient for each tap of an FIR equalizer equalizing a read signal read from a recording medium, as a restricted coefficient updating vector applied for updating the multiplication coefficient for each tap of an FIR filter, a vector is utilized which is obtained by projecting, onto a plane perpendicular to a predetermined restricting conditioning vector, a coefficient updating vector determined based on an equalizer error between the output of the FIR equalizer and a reproduction output determined therefrom and a delayed input value for each tap of the FIR equalizer.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: October 23, 2007
    Assignee: Fujitsu Limited
    Inventors: Masaru Sawada, Motomu Takatsu, Takao Sugawara
  • Patent number: 7274736
    Abstract: A dual path equalization structure is used to equalize DMT systems operating over channels in which different impairments dominate the performance of different parts of the channel. Two TEQ/DFT structures are used to process the received signal, each optimized for a different part of the channel. The outputs of the two paths are combined with appropriate frequency-domain equalization to achieve an overall equalization architecture which is better optimized for the whole channel.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: September 25, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Arthur John Redfern, Nirmal C. Warke, Ming Ding
  • Patent number: 7260162
    Abstract: A method and apparatus for improving the quality of a signal which has been detrimentally affected by inter-symbol interference due to time dispersion. The invention includes selecting one of at least two algorithms of equalization and after the selection, and processing the signal by performing steps according to the selected algorithm.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: August 21, 2007
    Assignee: Nokia Corporation
    Inventor: Olli Piirainen
  • Patent number: 7260146
    Abstract: Equalizing method and apparatus for single carrier system having an improved equalization performance is disclosed, which includes: a section setting unit for setting filter taps having a predetermined section corresponding to the predicted multi-path; a repeat setting unit for setting filter taps of a repetition section by making the set predetermined section repetitive periodically; and a filter unit for filtering the multi-path by updating the coefficients of the filter taps of the set repetition section. The repeat setting unit sets the filter taps of the repetition section corresponding to an operation characteristic of the filter unit. Accordingly, the apparatus can improve equalization performance by setting filter taps corresponding to the predicted multi-path and updating only the set coefficients of the filter taps. Further, the apparatus can improve equalization performance in dynamic channel circumstances in which the multi-path changes.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: August 21, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-sik Kwon, Jin-hee Jeong, Jung-jin Kim
  • Patent number: 7254173
    Abstract: A high speed CMOS-implemented equalizer architecture as described herein utilizes a digitally controlled analog equalization scheme to equalize intersymbol interference present in an input signal. The equalizer structure includes an inductor high frequency gain boosting stage and a feed forward high frequency equalizer stage connected in series. The equalization performed by each of these gain boosting stages is controlled by one or more digital control signals. The combination of these stages results in the equalization of both amplitude and phase distortion. The equalizer architecture is suitable for use with communication systems that operate at 11.2 Gbps speeds.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: August 7, 2007
    Assignee: Applied Micro Circuits Corporation
    Inventors: Wei Fu, Joseph James Balardeta
  • Patent number: 7242711
    Abstract: An improved decision feedback equalization technique is provided that may be used in data communications receivers such as those in WLAN (Wireless Local Area Network) systems. The decision feedback equalizer comprises a feedforward filter that is connected to receive an input data signal and output a filter representation thereof. The feedforward filter has a filter characteristic that depends on filter coefficient data. The decision feedback equalizer further comprises a filter coefficient computation unit for generating the filter coefficient data and outputting the generated data to the feedforward filter. At least one data processing circuit is provided that receives a mode switch signal for switching its operational mode. The data processing circuit is arranged for performing a feedforward filter function in one operational mode and a filter coefficient computation function in another operational mode.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: July 10, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Eckhardt, Michael Schmidt, Eric Sachse
  • Patent number: 7242710
    Abstract: The present invention proposes a new method and apparatus for the improvement of digital filterbanks, by a complex extension of cosine modulated digital filterbanks. The invention employs complex-exponential modulation of a low-pass prototype filter and a new method for optimizing the characteristics of this filter. The invention substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filterbank as an spectral equalizer. The invention is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip. The invention offers essential improvements for various types of digital equalizers, adaptive filters, multiband companders and spectral envelope adjusting filterbanks used in high frequency reconstruction (HFR) systems.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: July 10, 2007
    Assignee: Coding Technologies AB
    Inventor: Per Ekstrand
  • Patent number: 7239652
    Abstract: An n-level look-ahead network converts input values to intermediate values that are provided to a plurality of multiplexers arranged to form a pipelined multiplexer loop. The first stage of the multiplexer loop consists of a single multiplexer. The second stage consists of at least two multiplexers. Communication links couple the output ports of the second stage multiplexers to the input ports of the first stage multiplexer. A first feedback loop electrically couples the output port of the first stage multiplexer to the control port of the first stage multiplexer. This first feedback loop has a first delay device having a first delay time. A second feedback loop couples the output port of the first stage multiplexer to the control ports of the second stage multiplexers. This second feedback loop includes the first delay device and a second delay device having a second delay time.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: July 3, 2007
    Assignee: Broadcom Corporation
    Inventor: Keshab K Parhi
  • Patent number: 7239660
    Abstract: A linear/non-linear adaptive filter for transforming an input signal to an output signal. The present invention also includes a novel GSPT LMS algorithm for significantly reducing complexity. The adaptive filter includes a coefficient updater that can execute a Carry-in operation or a Borrow-in operation to adaptively adjust a filtering coefficient according to whether an updating term signal is a Carry-in signal or a Borrow-in signal.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: July 3, 2007
    Assignee: Mediatek Inc.
    Inventors: Tzi-Dar Chiueh, Chun-Nan Chen, Kuan-Hung Chen
  • Patent number: 7236550
    Abstract: Subtraction of a signal 111 from a pulse response 110, where signal 111 provides a good approximation of the tail of pulse response 110, can provide a method for canceling the tail of pulse response 110. For continuous data streams, signals X(t), 223 and Y(t) can correspond to, respectively, signals 110, 111 and 112. X(t) differs from 110 in being a continuous data stream. 223 differs from 111 in being the low pass filtering of X(t), such low pass filtering accomplished by a unit LPF 211. Y(t) differs from 112 in being a continuous stream of equalized data, produced by subtracting the signal at 223 from X(t). A measurement unit 213, analysis unit 214 and decision unit 215 can act to continuously adapt LPF 211 such that tail cancellation equalization is continuously achieved. Measurement unit 213 can construct, from Y(t), a set of correlation measurements that can be used to adapt LPF 211.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: June 26, 2007
    Assignee: Synopsys, Inc.
    Inventors: Kannan Krishna, Jeffrey Lee Sonntag, John Theodore Stonick
  • Patent number: 7230982
    Abstract: This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For minimum-phase channels, the equalization is performed in a time-forward manner. For maximum-phase channels, the equalization is performed in a time-reversed manner. More specifically, for maximum-phase channels, the filter coefficients are computed based on the channel estimates reversed in time, and the filtering and equalization operations are performed with the received block of symbols in a time-reversed order. In the context of this invention, the term “minimum-phase channel” implies that the energy of the leading part of the channel profile is greater than the energy of the trailing part. The term “maximum-phase channel” implies that the energy of the leading part of the channel profile is less than the energy of the trailing part.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: June 12, 2007
    Assignee: Broadcom Corporation
    Inventors: Steve A. Allpress, Quinn Li
  • Patent number: 7222144
    Abstract: A filtering technique which makes it possible to easily and appropriately eliminate a noise without increasing a scale of a circuit necessary for a filtering process even if a noise frequency is liable to be changed is provided. A filter coefficient calculator (6) of a weight measurement apparatus calculates filter coefficients using a predetermined arithmetic expression and outputs them to a signal processor (5). The signal processor (5) carries out a filtering process on a weighing signal (Ds) using the filter coefficients. The arithmetic expression includes a parameter specifying a band position of an attenuation band where attenuation must be locally enhanced. A user can input a value of the parameter via a data entry part (7). In this manner, the filter coefficients can be changed by using a parameter specifying the band position of the attenuation band which is physical and thus easy to grasp.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: May 22, 2007
    Assignee: Ishida Co., Ltd.
    Inventors: Naoyuki Aikawa, Tohru Morichi, Yukio Wakasa
  • Patent number: 7218693
    Abstract: A method and apparatus for deriving the channel estimation within a packet based transmission system having a predetermined number of tones (N), wherein each channel has a channel order (L). A first method includes precomputing, from the long sequence (X) of a received signal, a channel estimation matrix (R?1) having a dimension of width and length equal to the channel order (L) and storing one fourth of the channel estimation matrix (R?1) since the channel estimation matrix (R?1) is centrosymmetric. Advantageously, precomputing and storing a fourth of the channel estimation matrix (R?1) saves time and complexity. In a second method, the bit-width requirement for fixed precision requirements regarding implementation in hardware is reduced wherein a channel estimation matrix (G) having dimension of width equal to the number of tones (N) and length equal to the channel order (L) is precomputed and stored.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: May 15, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Markos G. Troulis
  • Patent number: 7200194
    Abstract: A method for processing a received signal at a mobile receiver of a wireless communications system is disclosed. The method comprises demodulating the received signal to obtain an analog base band signal and converting the analog base band signal into a digital base band signal. The signal strength of the digital base band signal is estimated and, using the estimation, the digital base band signal is scaled by a scaling factor. The digital base band signal is equalized into an equalized digital signal which is then rescaled by a resealing factor.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: April 3, 2007
    Assignee: Spreadtrum Communications Corporation
    Inventors: Jingdong Lin, Shengquan Hu, Jin Ji, Ying Tian, Datong Chen
  • Patent number: 7197146
    Abstract: A system and method facilitating signal enhancement utilizing an adaptive filter is provided. The invention includes an adaptive filter that filters an input based upon a plurality of adaptive coefficients and modifies the adaptive coefficients based on a feedback output. A feedback component provides the feedback output based, at least in part, upon a non-linear function of the acoustic reverberation reduced output. Optionally, the system can further include a linear prediction (LP) analyzer and/or a LP synthesis filter. The system can enhance signal(s), for example, to improve the quality of speech that is acquired by a microphone by reducing reverberation. The system utilizes, at least in part, the principle that certain characteristics of reverberated speech are measurably different from corresponding characteristics of clean speech. The system can employ a filter technology (e.g., reverberation reducing) based on a non-linear function, for example, the kurtosis metric.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: March 27, 2007
    Assignee: Microsoft Corporation
    Inventors: Henrique S. Malvar, Dinei Afonso Ferreira Florencio, Bradford W. Gillespie
  • Patent number: 7194027
    Abstract: A channel equalizing and carrier recovery system for home phoneline networking alliance (HomePNA) receiver and method thereof are provided. The channel equalizing system includes a frequency diverse quadrature amplitude modulation (FD-QAM) equalizer and a quadrature amplitude modulation (QAM) equalizer. The FD-QAM equalizer receives an FD-QAM signal, determines FD-QAM tap coefficients, and equalizes the FD-QAM signal using the FD-QAM tap coefficients. The QAM equalizer receives a QAM signal, determines QAM tap coefficients, and equalizes the QAM signal using the QAM tap coefficients. The QAM equalizer receives the FD-QAM signal and determines the QAM tap coefficients during a predetermined header period. The carrier recovery circuit includes a phase detector, a loop filter, and a numerically controlled oscillator (NCO).
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: March 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-woo Kim, Chang-hyun Yim, Hyun-cheol Park, Oh-sang Kwon, Jung-hoon Kim, Sung-hyun Hwang
  • Patent number: 7194674
    Abstract: The waveform equalizing device includes: an FIR filter for generating an equalized signal pattern y(i, n) on the basis of equalization of a waveform of the reproduced signal pattern u(i, n); a Viterbi decoding circuit for detecting a path metric difference s(n) between a correct path determined as a survivor path and an error path which fails to survive the correct path in Viterbi decoding based on the equalized signal pattern y(i, n); a target register for setting a target value ds for the path metric difference s(n); and a tap coefficients update circuit for adapting the equalization according to an error of the detected path metric difference from the target value. The tap coefficients update circuit adapts equalization properties so that the mean square error is minimized, thereby achieving a satisfactory result in lowering the error rate.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: March 20, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuya Okumura, Shigemi Maeda
  • Patent number: 7184475
    Abstract: A method of adjusting equalization parameters in a receiver wherein a bit error rate (BER) in a data stream is measured from the number of corrected bits in data blocks which have an information section and an error correction section. A predetermined equalization parameter is changed, and the bit error rate (BER) after change is again measured to find out how to change the predetermined equalization parameter until an optimum is reached. When adjusting the threshold value of the receiver, the history of occurring bits preceding the actual sampled bit is taken into consideration in that the amount and direction of adjustment is derived from a look-up table.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: February 27, 2007
    Assignee: Lucent Technologies Inc.
    Inventors: Ralf Dohmen, Christoph Schulien, Herbert Haunstein, Achim Herzberger, Georg Roell, Konrad Sticht
  • Patent number: 7173967
    Abstract: A vector space comprising all of the filter coefficients for different interfering signals is provided, based on an acquired impulse response. A linear vector sub-space comprising all of the optimal filter coefficients for different interfering signals is established from said vector space using a vector space optimization method. The filter coefficients are established from the vector sub-space according to the current interfering signal being detected, during ongoing data transmission and at the maximum transmission speed.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: February 6, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Blinn, Werner Kozek
  • Patent number: 7167883
    Abstract: A finite impulse response filter, including a plurality of taps arranged to receive and process a sequence of input data samples so as to generate a filter output. Each tap consists of a multiplier operating in one's complement arithmetic, the multiplier being coupled to multiply a respective input sample from the sequence by a respective equalization coefficient, and an adder, which sums an output from the multiplier. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The filter also includes an adjustment-accumulator coupled to receive the filter output and responsive thereto to generate an adjustment that is adapted to correct the filter output to a twos complement result, and an adjustment-adder which sums the adjustment and the filter output to generate a final output.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: January 23, 2007
    Assignee: Mysticom Ltd.
    Inventors: Israel Greiss, Baruch Bublil, Jeffrey Jacob, Dimitry Taich
  • Patent number: 7158567
    Abstract: A method for performing adaptive equalization is presented comprising receiving a Forward Error Correction (FEC) encoded signal from a channel, filtering the received FEC encoded signal using a filter according to at least one adjustable filter coefficient to produce a filtered signal, evaluating the filtered signal to generate a signal error output, adjusting the at least one adjustable filter coefficient in response to the signal error output, performing FEC decode processing dependent on the filtered signal to generate an FEC output, and adjusting the at least one adjustable filter coefficient in response to the FEC output. In one embodiment, the signal error output relates to Mean Squared Error (MSE), and the FEC output relates to bit error rate. The at least one adjustable filter coefficient may be first adjusted in response to the signal error output until a specified condition is met, then adjusted in response to the FEC output.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: January 2, 2007
    Assignee: Vitesse Semiconductor Corporation
    Inventors: John S. Wang, Jeff Rahn, Sudeep Bhoja
  • Patent number: 7151796
    Abstract: An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: December 19, 2006
    Assignee: Broadcom Corporation
    Inventors: Steve A. Allpress, Quinn Li
  • Patent number: 7139311
    Abstract: An equalizer apparatus comprises a first filter (406) having a first respective plurality of filter coefficients, a channel model filter (414) having a plurality of model filter coefficients, and an adaptive algorithm unit (416). The adaptive algorithm unit (416) is arranged to adapt at least a first predetermined number of the first respective plurality of filter coefficients and at least a second predetermined number of the plurality of model filter coefficients in response to an error signal (e) corresponding to a difference in filter output signals from the first filter and the channel model filters (406, 414). The adaptive algorithm unit (416) operates in accordance with a respective state channel estimation technique. The respective state channel estimation technique is adapted so as to reduce a number of states allocatable to at least one of the plurality of state-defining taps, thereby reducing an overall number of states definable associated with the plurality of state-defining taps.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: November 21, 2006
    Assignee: Siemens Aktiengesellschaft
    Inventor: Leo Rademacher
  • Patent number: 7136413
    Abstract: A receiver includes a Viterbi-like equalizer that provides diversity combining of soft values to produce reliability information. The output reliability information at time k is the average of the first reliability information at time k and the second reliability information at time (k?1) after being normalized by the noise power. The first reliability information at time k is the difference between the two accumulated metrics of the two preceding nodes arriving at the same node having the global minimum node metric at time k over all transitions of all states. The second reliability function at time k is the difference between the best accumulated metric characterized by the last (L?1) bit being binary “one” and the best accumulated metric characterized by the last (L?1) bit being binary “zero.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: November 14, 2006
    Assignee: Mediatek, Inc.
    Inventors: Ho-Chi Hwang, Ching-Yao Su, Wei-Nan Sun
  • Patent number: 7123653
    Abstract: The present invention relates to blind decision feedback equalization. The present invention selects one of a filter signal and a quantized signal as an input signal of a feedback filter in the DFE and update the tap coefficient according to the SAG flag f[k] by including a main filtering unit, a SAG flag determining unit and a blind feedback controlling unit. The present invention prevents decrement of a performance caused by an error propagation and also improve a convergence performance in an equalization apparatus and reduce a symbol error rate (SER) at a steady state after converging. In conclusion, the present invention can be used effectively to a receiver in a digital TV, which is required the blind equalizer.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: October 17, 2006
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyoung-Nam Kim, Yong Tae Lee, Seung Won Kim
  • Patent number: 7123728
    Abstract: A computer readable medium containing program instructions for controlling a parametric equalizer is provided. Generally, a computer readable code is provided for displaying a composite equalization curve, wherein the composite equalization curve is formed from at least a first frequency filter with a first center frequency, a second frequency filter with a second center frequency, and a third frequency filter with a third center frequency. A computer readable code is provided for allowing a dragging movement of the first center frequency, the second center frequency, and the third center frequency.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: October 17, 2006
    Assignee: Apple Computer, Inc.
    Inventors: Nick King, Michael F. Culbert
  • Patent number: 7113540
    Abstract: Multi-Input-Multi-Output (MIMO) Optimal Decision Feedback Equalizer (DFE) coefficients are determined from a channel estimate h by casting the MIMO DFE coefficient problem as a standard recursive least squares (RLS) problem and solving the RLS problem. In one embodiment, a fast recursive method, e.g., fast transversal filter (FTF) technique, then used to compute the Kalman gain of the RLS problem, which is then directly used to compute MIMO Feed Forward Equalizer (FFE) coefficients gopt. The complexity of a conventional FTF algorithm is reduced to one third of its original complexity by choosing the length of a MIMO Feed Back Equalizer (FBE) coefficients bopt (of the DFE) to force the FTF algorithm to use a lower triangular matrix. The MIMO FBE coefficients bop are computed by convolving the MIMO FFE coefficients gopt with the channel impulse response h. In performing this operation, a convolution matrix that characterizes the channel impulse response h extended to a bigger circulant matrix.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: September 26, 2006
    Assignee: Broadcom Corporation
    Inventors: Nabil R. Yousef, Ricardo Merched
  • Patent number: 7099385
    Abstract: A data communication receiver comprises an equalizer for adapting to each of a plurality of channels to open the eye for each channel in a Gigabit (1000BASE-T) transceiver. The eye is open for a first channel (A) and a transformation process applies the coefficients of that adaptation to open the eye for the other dimensions. The transformation process keeps the magnitude response constant.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: August 29, 2006
    Assignee: Massana Research Limited
    Inventors: Philip Curran, Stephen Bates
  • Patent number: 7099911
    Abstract: A Givens rotation computation technique is provided that makes use of polynomial approximations of an expression that contains a square root function. The polynomial approximation uses polynomial coefficients that are specifically adapted to respective ones of a number of subintervals within the range of possible values of the input variable of the expression. The technique may be used in data communications devices such as those in wireless local area networks. An example is the application of the Givens rotations technique in a decision feedback equalizer.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: August 29, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Schmidt, Ruediger Menken