Abstract: Aspects of the disclosure are directed to sequencing. In accordance with one aspect, sequencing includes creating a one hot list; selecting a current word of the one hot list as a one hot list output; comparing the one hot list output with a current accumulation register value of an accumulation register to produce a logical comparison; inputting the logical comparison to the accumulation register to generate an updated accumulation register value; and outputting the updated accumulated register state to a client unit to enable or disable the client unit.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

Abstract: The present embodiments relate to circuitry that efficiently performs double-precision floating-point multiplication operations, single-precision floating-point multiplication operations, and fixed-point multiplication operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block efficiently may perform a single-precision floating-point multiplication operation, and multiple specialized processing blocks may be coupled together to perform a double-precision floating-point multiplication operation. Inter-block signaling circuits may generate rounding information and propagate the rounding information together with partial product results from a current specialized processing block to another specialized processing block.

Abstract: Aspects of the disclosed technology relate to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on the initial FPGA-mapped netlist, the circuit design is partitioned into design partitions for implementing the circuit design across a plurality of FPGA chips. Final FPGA-mapped netlists are then generated based on the design partitions represented by the generic RTL design or by a combination of the generic RTL design and the initial FPGA-mapped netlist.

Abstract: A method and computer system are provided for performing a comparison computation, e.g. for use in a check procedure for a reciprocal square root operation. The comparison computation compares a multiplication of three values with a predetermined value. The computer system performs the multiplication using multiplier logic which is configured to perform multiply operations in which two values are multiplied together. A first and second of the three values are multiplied to determine a first intermediate result, w1. The digits of w1 are separated into two portions, w1,1 and w1,2. The third of the three values is multiplied with w1,2 and the result is added into a multiplication of the third of the three values with w1,1 to thereby determine the result of multiplying the three values together. In this way the comparison is performed with high accuracy, while keeping the area and power consumption of the multiplier logic low.

Abstract: A slicer circuit for use in a N-tap, S-bit symbol look-ahead decision feedback equalizer (DFE) wherein the slicer comprises overflow adders and sign adders, the slicer circuit including a first processing path for generating, based on a signal sample y(n), a most significant bit (MSB) for each of 2S*N possible output symbols of the DFE, the first processing path including (2S*N)/2 overflow adder circuits, and a second processing path for generating, based on the signal sample y(n), a least significant bit (LSB) for each of the 2S*N possible output symbols, the second processing path including 2S*N sign adder circuits.

Abstract: A method for generating a coordinate point in an embedded system comprises the following steps: obtaining a random number and a first fixed value, and performing a modulo operation on the random number by using the first fixed value as a modulus, so as to obtain first data; selecting each data bit from the first data; obtaining, according to a position of the selected data bit in the first data, an initial point value corresponding to the selected data bit from a pre-stored initial point value list when data in the selected data bit is not zero; and performing a point adding operation on the obtained initial point value and an intermediate point value, and outputting the obtained operation result as result data. In the present invention, by querying in a preset initial point value list, an initial point value in the initial point value list is obtained, and calculation is performed according to the initial point value, thereby greatly improving the speed of generating a coordinate point.

Abstract: Systems and methods are described herein for reducing an amount of power consumption in a programmable integrated circuit device configured to perform a multiplication operation. The device includes a first multiplier that generates a first partial product associated with a first set of bit locations and a second multiplier that generates a second partial product associated with a second set of bit locations that are more significant than the first set of bit locations. The device further includes a switching circuitry to deactivate the first multiplier to reduce an amount of power consumed by the programmable integrated circuit device.

Abstract: One embodiment of the present invention includes a method for performing arithmetic operations on arbitrary width integers using fixed width elements. The method includes receiving a plurality of input operands, segmenting each input operand into multiple sectors, performing a plurality of multiply-add operations based on the multiple sectors to generate a plurality of multiply-add operation results, and combining the multiply-add operation results to generate a final result. One advantage of the disclosed embodiments is that, by using a common fused floating point multiply-add unit to perform arithmetic operations on integers of arbitrary width, the method avoids the area and power penalty of having additional dedicated integer units.

Abstract: A processor includes a front end with logic to identify a multiplier, multiplicand, and mathematical mode based upon an instruction. The processor also includes a multiplier circuit to apply Booth encoding to multiply the multiplier and multiplicand. The multiplier circuit includes circuitry to determine leftmost and rightmost partial products of multiplying the multiplier and multiplicand using Booth encoding. The circuitry includes a most significant bit (MSB) array and least significant bit (LSB) array corresponding to the multiplier. The multiplier circuit also includes logic to selectively enable selectors of the circuitry to find partial products based upon the mathematical mode of the instruction.

Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems for performing formal verification. For example, certain embodiments can be used to formally verify a Booth multiplier. For instance, in one example embodiment, a specification of a Booth multiplier circuit is received; an initial model checking operation is performed for a smaller version of the Booth multiplier circuit; a series of subsequent model checking operations are performed for versions of the Booth multiplier circuit that are incrementally larger than the smaller version of the Booth multiplier circuit, wherein, for each incrementally larger Booth multiplier circuit, two or more model checking operations are performed, the two or more model checking operations representing decomposed proof obligations for showing; and a verification result of the Booth multiplier circuit is output.

Abstract: A fixed point multiplier that can be used in mobile computer systems operating under limited power constraints provides a trade-off between computational accuracy and energy consumption that may be changed dynamically for energy conservation purposes. In one embodiment, the multiplier pre-stores multiplication shift coefficients to eliminate leading-one circuitry normally used in shift and accumulate multipliers.

Abstract: Methods and systems for signal processing using processing blocks are provided. In one embodiment of the disclosure, there are provided a plurality of multiplier circuitries and control circuitry configured to multiply numbers AB and CD. The number AB includes components A and B, and the component A includes subcomponents AH and AL. The number CD includes components C and D, and the component C includes subcomponents CH and CL. The control circuitry is configured to compute a partial product AD based on multiplying D and AL using a first multiplier circuitry and based on multiplying D and AH the using a first multiplier module of a second multiplier circuitry. The control circuitry is also configured to compute a partial product CB based on B and CL using a third multiplier circuitry and based on multiplying B and the CH using a second multiplier module of the second multiplier circuitry.

Abstract: A method and apparatus may be used to evaluate a polynomial by initializing a multiply and accumulate feedback apparatus (260) comprising a multiplier stage (264) having an output coupled to an input of an accumulator stage (267) having an accumulator feedback output (269) selectively coupled to an input of the multiplier stage over a plurality of clock cycles; iteratively calculating a final working loop variable z over an additional plurality of clock cycles; multiplying the final working loop variable z and a complex input vector x to compute a final multiplier value; and adding a least significant complex polynomial coefficient to the final multiplier value using the multiplier stage of the multiply and accumulate feedback apparatus to yield a result of the polynomial evaluation.

Abstract: Embodiments of the invention relate to sparsity-driven matrix representation. In one embodiment, a sparsity of a matrix is determined and the sparsity is compared to a threshold. Computer memory is allocated to store the matrix in a first data structure format based on the sparsity being greater than the threshold.

Abstract: According to an embodiment, a matrix operation apparatus executing a matrix operation includes multiple nodes, the nodes including: a multiplier configured to perform a first operation for a first input, which is column data and a second input which is row data for the matrix operation and output element components of an operation result of the matrix operation; and an accumulator configured to perform cumulative addition of operation results of the multiplier.

Abstract: A calculating unit for reducing an input number with respect to a modulus, wherein the input number has input number portions of different significances, wherein the input number portions represent the input number with respect to a division number, wherein the modulus has modulus portions of different significances, and wherein the modulus portions represent the modulus with respect to the division number, includes a unit for estimating a result of an integer division of the input number by the modulus using a stored most significant portion of the number, a stored most significant portion of the modulus and the number, and for storing the estimated result in a memory of the calculating unit, and a unit for calculating a reduction result based on a subtraction of a product of the modulus and a value derived from the estimated result from the number.

Abstract: Techniques are disclosed relating to performing extended multiplies without a carry flag. In one embodiment, an apparatus includes a multiply unit configured to perform multiplications of operands having a particular width. In this embodiment, the apparatus also includes multiple storage elements configured to store operands for the multiply unit. In this embodiment, each of the storage elements is configured to provide a portion of a stored operand that is less than an entirety of the stored operand in response to a control signal from the apparatus. In one embodiment, the apparatus is configured to perform a multiplication of given first and second operands having a width greater than the particular width by performing a sequence of multiply operations using the multiply unit, using portions of the stored operands and without using a carry flag between any of the sequence of multiply operations.

Abstract: A specialized processing block is configurable as one ternary linear decomposition or two binary linear decompositions to perform large multiplications using smaller multipliers, and includes a first number of multiplier circuits of a first size, a second number of pre-adders, and a third number of block inputs. The block inputs are connected to a first subset of the multiplier circuits, and to the pre-adders which are connected to a second subset of the multiplier circuits. There is also a fourth number of additional inputs. A plurality of shifters shift partial product outputs of each of the multipliers by various shift amounts. A joint adder structure combines the shifted partial products. Controllable elements controllably select between different configurations of inputs to the multipliers and pre-adders, controllably connect and disconnect certain ones of the shifted partial products, and selectively split the joint adder structure into two smaller adder structures.

Abstract: Methods and apparatus relating to reducing power consumption in multi-precision floating point multipliers are described. In an embodiment, certain portions of a multiplier are disabled in response to two or more multiplication operations with the same data size and data type occurring back-to-back. Other embodiments are also claimed and described.

Abstract: Digital signal processing (“DSP”) circuit blocks that include multipliers of a certain basic size are augmented to enable the DSP block to perform multiplications that are larger than the basic multiplier size would otherwise permit. In some embodiments, the larger multiplication can have less than full precision. In other embodiments, the larger multiplication can have full precision by making use of some capabilities of a second DSP block.

Abstract: Systems and methods for using carry-less multiplication (CLMUL) to implement erasure code are provided. An embodiment method of using CLMUL to implement erasure code includes initiating, with a processor, a first CLMUL call to calculate a first product of a data bit word and a constant, partitioning, with the processor, the first product into a high portion and a low portion, and initiating, with the processor, a second CLMUL call to calculate a second product of the high portion and a hexadecimal number portion, a bit size of the second product less than a bit size of the first product. The second product, or a third product generated by a third CLMUL call, is used to calculate a parity bit. Because the second product or the third product has a number of bits equivalent to the number of bits used by the processor, the erasure codes are more efficiently implemented.

Abstract: Multiplier circuitry that efficiently utilizes the hard and soft logic regions of a programmable logic device (PLD) is provided. The multiplier circuitry includes a partial product generation block, a compression block (e.g., a carry-save adder), and an carry-propagate adder stage. The partial product generation and compression block are implemented in hard logic while the carry-propagate adder is implemented in soft logic. Local or global routing may be used to connect the hard and soft multiplier components. The multiplier may further include a selectable input register in hard logic and/or a selectable output register in soft logic. This mixed-mode design allows for a substantial savings in the amount of hard logic required to implement the multiplier without a significant decrease in multiplier performance.

Abstract: A computer-implemented method includes receiving instructions to execute an analytic, wherein the instructions comprise one or more analytic inputs and a corresponding one or more uncertainty values, and wherein the analytic defines a continuous, monotonic mathematical function. The method includes executing the analytic using the one or more analytic inputs to determine one or more analytic outputs. The method also includes executing an uncertainty calculation to estimate one or more uncertainty outputs corresponding to the one or more analytic outputs, based, at least in part, on the one or more analytic inputs and the corresponding one or more uncertainty values. The method further includes providing the one or more analytic outputs as well as the corresponding one or more uncertainty outputs.

Abstract: A method of identifying a set of parameters representative of a data set is provided. An eigen decomposition of a covariance matrix is calculated to form a decomposed matrix and an eigenvalue vector. The covariance matrix is calculated for a matrix of data including a plurality of data values for each of a plurality of parameters. The decomposed matrix includes a number of eigenvectors equal to a number of the plurality of parameters with each eigenvector including a coefficient for each parameter. The eigenvalue vector includes an eigenvalue defined for each eigenvector. A first matrix is created by rank ordering the coefficient within each parameter of the plurality of parameters for each of the plurality of parameters. A score is determined for each parameter using the created first matrix and the eigenvalue vector. A parameter set is identified based on the determined score for each parameter.

Abstract: Provided is a method for processing data samples from a plurality of data channels. The method may include obtaining a plurality of data samples from the plurality of data channels. Obtaining the plurality of data samples may involve successively obtaining a data sample from each data channel of the plurality of data channels. Successively obtaining a data sample from each data channel may be performed a plurality of times during a specified time period. Each data sample of the plurality of data samples may be associated with a respective sample time, and each respective sample time may be relative to a single specified reference point in time. The method may further include, for each data sample of the plurality of data samples, determining a time-dependent coefficient value that may correspond to the sample time associated with the data sample, and applying the determined time-dependent coefficient value to the data sample.

Abstract: The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number.

Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.

Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

Abstract: The method for implementing a characteristic-2-multiplication of at least two input bit strings each having a number N of bits by means of a processor unit suitable for carrying out an integer multiplication, having the following steps: a) generating at least one sequence of a number K of zero bits, using K?{1, . . . , N}, by means of a first transformation of the respective input bit string to at least one predetermined position in the respective input bit string for generating at least one first intermediate bit string; b) linking the at least two first intermediate bit strings by means of the integer multiplication of the processor unit for generating at least one second intermediate bit string; and c) transforming the at least one second intermediate bit string by means of a second transformation for generating a result bit string.

Abstract: Multiplier circuits that can optionally be configured as bit shifters. An exemplary multiplier includes a one-hot circuit, a multi-bit multiplexing circuit, and a multiply block. The one-hot circuit has a multi-bit input and a multi-bit output. The multiplexing circuit has first and second multi-bit inputs and a multi-bit output, with the first input of the multiplexing circuit being coupled to the output of the one-hot circuit. The multiply block has first and second multi-bit inputs and a multi-bit output, with the first input of the multiply block being coupled to the output of the multiplexing circuit. When selected by the multiplexer, the position of the single high bit in the one-hot circuit output determines the number of bits by which the multiplier output is shifted relative to the second multiplier input. When the one-hot circuit output is not selected as an input to the multiplier, the multiplier performs a multiply function.

Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Abstract: A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2n)2) multiplier, a GF(2n) standard basis multiplier, and a GF(2n) look-up table multiplier; the controller is connected respectively to the input port, the output port, the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier; the GF((2n)2) multiplier is connected respectively to the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier. By using the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier, the multiplication of three operands is realized. Compared with the existing multiplier, the multiplier of the present invention has significant advantages in the speed of multiplying three operands over GF((2n)m).

Abstract: A method for determining a quotient value from a dividend value and a divisor value in a digital processing circuit is provided. The method includes computing a reciprocal value of the divisor value and multiplying the reciprocal value by the dividend value to obtain a reciprocal product, the reciprocal product having an integer part. The method also includes computing an intermediate remainder value by computing a product of the integer part and the divisor value, and subtracting the resulting product from the dividend value and determining the quotient value based upon the intermediate remainder value.

Abstract: A method and apparatus may be used to evaluate a polynomial by initializing a multiply and accumulate feedback apparatus (260) comprising a multiplier stage (264) having an output coupled to an input of an accumulator stage (267) having an accumulator feedback output (269) selectively coupled to an input of the multiplier stage over a plurality of clock cycles; iteratively calculating a final working loop variable over an additional plurality of clock cycles; multiplying the final working loop variable z and a complex input vector x to compute a final multiplier value; and adding a least significant complex polynomial coefficient to the final multiplier value using the multiplier stage of the multiply and accumulate feedback apparatus to yield a result of the polynomial evaluation.

Abstract: The “Big Bung!” was not at the beginning of Universe!

Abstract: A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations.

Abstract: An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive a second operand, and an adder coupled to the first register and the second register. The adder is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.

Abstract: Circuitry for increasing the precision of multipliers by a desired factor while limiting the increase in arithmetic complexity of the multiplier to that factor can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD). The smaller increase in arithmetic complexity, so that the increase is proportional to the increase in precision, rather than to the square of the increase in precision, is achieved by using specialized processing block components differently on alternating clock cycles. For example, to implement double precision, the same multiplier components are used in each of two clock cycles, but some specialized processing block internal structures (e.g., shifters and adders) are used differently in the two cycles, so that over the two cycles, a larger multiplication may be calculated from smaller partial products.

Abstract: A multiply-accumulate unit (MAU) configurable to perform both real and complex multiplication operations, a method of performing a mac operation and a processing unit incorporating the MAU or the method. In one embodiment, the MAU includes: (1) a first multiplier having a first vector input and a first scalar input and configured to multiply a first vector by a first scalar to yield a first product, (2) a second multiplier having a second vector input and a second scalar input and configured to multiply a second vector by a second scalar to yield a second product and (3) an accumulator coupled to the first multiplier and the second multiplier and configured to receive the first and second products.

Abstract: A method and apparatus for detecting a signal using a cyclo-stationary characteristic value is provided. A method of detecting a signal using a cyclo-stationary characteristic value includes: calculating cyclo-stationary characteristic values with respect to a cyclic frequency domain of an input signal; multiplying the calculated cyclo-stationary characteristic values with each other; and detecting the signal from the input signal based on the result of the multiplication.

Abstract: A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.

Abstract: A method is described that includes performing the following with an instruction execution pipeline of a semiconductor chip. Multiplying two vectors by: receiving a vector element multiplicand and vector element multiplier expressed in a first base system; converting the vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier; multiplying with a first execution unit of the pipeline the converted vector element multiplicand and the converted vector element multiplier to form a multiplication result; accumulating in a register a portion of the multiplication result with a portion of a result of a prior multiplication of operands expressed in the second lower base system; and, converting contents of the register into the first base system.

Abstract: An elliptic curve cryptographic system where point coordinates are transformed from a first coordinate system to a second coordinate system. The transformed coordinates are processed by field operations, which have been modified for operating on the transformed point coordinates. In some implementations, the point coordinates are transformed from an affine coordinate system to a projective coordinate system using a non-random value for the projective coordinate. In some implementations, the transformed projective representation of the point can be changed from a first representation of the point in projective coordinates to a second representation of the point in projective coordinates, where the projective coordinate used in the representation change is a random value.

Abstract: The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.

Abstract: Techniques for efficiently performing transforms on data are described. In one design, an apparatus performs multiplication of a first group of at least one data value with a first group of at least one rational dyadic constant that approximates a first group of at least one irrational constant scaled by a first common factor. The apparatus further performs multiplication of a second group of at least one data value with a second group of at least one rational dyadic constant that approximates a second group of at least one irrational constant scaled by a second common factor. Each rational dyadic constant is a rational number with a dyadic denominator. The first and second groups of at least one data value have different sizes. The first and common factors may be selected based on the number of logical and arithmetic operations for the multiplications, the precision of the results, etc.

Abstract: Multiplication engines and multiplication methods are provided for a digital processor.

Abstract: A configurable multiplier circuit for multiplying both real and complex numbers is included in a PLD. In one embodiment, the circuit includes two adder trees. Multiplexers are used such that a conventional multiplier component is not required. The circuit is programmable to operate in one of two modes. In a first mode, the circuit multiplies the four parts of two complex numbers and outputs two values, the real portion of the product and the imaginary portion of the product. In a second mode, each of two portions of the circuit multiplies two pairs of real numbers and outputs the products.

Abstract: Systems and methods are provided for efficiently counting detected events via a multiplicative group counter. An equivalent class polynomial congruent with a first of a plurality of elements comprising a multiplicative group is represented as a series of binary values. The represented polynomial is subjected to a state transition function as each event is detected, such that the series of binary values is altered to represent a new equivalent class polynomial congruent with a second of the plurality of elements of a multiplicative group. The series of binary values is decoded to determine a number of detected events recorded by the counter.