Multiplication Patents (Class 708/620)
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Publication number: 20090172067Abstract: Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating. The result of the multiplier can be stored in a result register in unsaturated form. The output of the result register can then be saturated and provided to addition and subtraction logic to allow efficient implementation of a saturating multiplier.Type: ApplicationFiled: December 30, 2008Publication date: July 2, 2009Inventor: Paul Metzgen
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Publication number: 20090164546Abstract: A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay.Type: ApplicationFiled: December 21, 2007Publication date: June 25, 2009Inventors: Vinodh Gopal, Erdinc Ozturk, Gilbert Wolrich, Wajdi K. Feghali
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Publication number: 20090157790Abstract: An efficient method and apparatus to compute a product of polynomials of degree n?1 where n is an arbitrary prime is provided. The total number of multiply operations and Arithmetic Logical Unit (ALU) operations to compute the product is minimized through the judicious use of polynomial evaluations at few points to decrease the number of multiplications while using only simple ALU operations.Type: ApplicationFiled: December 15, 2007Publication date: June 18, 2009Inventors: Vinodh Gopal, Michael E. Kounavis
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Publication number: 20090157789Abstract: Systems and methods are provided for efficiently counting detected events via a multiplicative group counter. An equivalent class polynomial congruent with a first of a plurality of elements comprising a multiplicative group is represented as a series of binary values. The represented polynomial is subjected to a state transition function as each event is detected, such that the series of binary values is altered to represent a new equivalent class polynomial congruent with a second of the plurality of elements of a multiplicative group. The series of binary values is decoded to determine a number of detected events recorded by the counter.Type: ApplicationFiled: December 13, 2007Publication date: June 18, 2009Inventor: David Steven Schuman
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Publication number: 20090146691Abstract: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.Type: ApplicationFiled: February 13, 2009Publication date: June 11, 2009Inventors: Martin VORBACH, Frank MAY, Dirk REICHARDT, Frank LIER, Gerd EHLERS, Armin NUCKEL, Volker BAUMGARTE, Prashant RAO, Jens OERTEL
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Publication number: 20090138744Abstract: A multiplier device is configured to include first to nth multipliers M1 to Mn for multiplying a carrier modulated information signal with first to nth mutually phase shifted and identical, substantially square wave mixing signals MS1 to MSn with 50% duty cycle. In order to eliminate fifth or higher order interferences from the output of the multiplier device according to the invention, n is greater than 2, outputs of the multipliers M1 to Mn are respectively coupled through weighting circuits W1 to Wn with respective fixed weighting factors WF1 to WFn to an adder circuit, the mixing signals MS1 to MSn having respective phase angles ?i corresponding to ?i=i*??, the weighting factors WFi corresponding to the sine value of the respective phase angles ?i=i*?? with ?? being the mutual phase difference between each two phase consecutive mixing signals corresponding to ?/(n+1) and i varying from 1 to n.Type: ApplicationFiled: January 27, 2009Publication date: May 28, 2009Inventor: Wolfdietrich Georg KASPERKOVITZ
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Patent number: 7539714Abstract: Method, apparatus, and program means for performing a sign and multiply operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a first source operand multiplied by a sign value of a second source operand. In some embodiments, the first source operand may be overwritten by the result.Type: GrantFiled: June 30, 2003Date of Patent: May 26, 2009Assignee: Intel CorporationInventors: William W. Macy, Jr., Huy V. Nguyen
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Publication number: 20090125576Abstract: This invention relates to Pade approximation convert circuit of the direct digital frequency synthesizer in which a multiplier receives and multiplies a first input signal and a variable signal so as to produce a multiplication signal; a divider receives and divides a second input signal and a variable signal so as to produce a division signal; an adder receives and adds the multiplication signal and the division signal so as to generate an output signal, that is then returned back to the divider. A quarter period of a sinusoidal wave signal is completed by the proceeding of direct calculation two times such that the time for the calculation of a complete sinusoidal wave can be saved and the area of the calculation circuit can be reduced.Type: ApplicationFiled: November 13, 2007Publication date: May 14, 2009Inventors: Shiann Shiun Jeng, Hsing Chen Lin, Wei Li Tou, Pao Kuei Horng
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Patent number: 7519643Abstract: A Montgomery multiplier for providing security of information used in smart cards from hacking by a differential power analysis attack by minimizing power consumption difference by the input data. More particularly, the Montgomery multiplier applies an asynchronous dual rail lines method wherein two lines DATAFALSE and DATATRUE are used to represent one binary data such that in order to represent binary data ‘0’, a logical high signal is applied to the DATAFALSE line, and a logical low signal is applied to the DATATRUE line. Conversely, to represent binary data ‘1’, a logical low signal is applied to the DATAFALSE line, and a logical high signal is applied to the DATATRUE line. That is, when the data is represented by the asynchronous dual rail lines method, whatever the binary data value is, the same number of logical high states and logical low states are generated. As a result, whatever binary data is to be operated, the power consumption difference of the circuit is minimized.Type: GrantFiled: December 29, 2004Date of Patent: April 14, 2009Assignee: Gwangju Institute of Science and TechnologyInventors: Dong-Soo Har, Dong-Wook Lee
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Patent number: 7519646Abstract: A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.Type: GrantFiled: October 26, 2006Date of Patent: April 14, 2009Assignee: Intel CorporationInventors: Himanshu Kaul, Mark A. Anders, Sanu Mathew, Ram Krishnamurthy
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Patent number: 7506016Abstract: Multiplier device comprising first to nth multipliers M1 to Mn for multiplying a carrier modulated information signal with first to nth mutually phase shifted and identical, substantially square wave mixing signals MS1 to MSn with 50% duty cycle. In order to eliminate fifth or higher order interferences from the output of said multiplier device according to the invention, n is greater than 2, outputs of said multipliers M1 to Mn are respectively coupled through weighting circuits W1 to Wn with respective fixed weighting factors WF1 to WFn to an adder circuit, said mixing signals MS1 to MSn having respective phase angles ?i corresponding to ?i=i*??, said weighting factors WFi corresponding to the sine value of said respective phase angles ?i=i*?? with ?? being the mutual phase difference between each two phase consecutive mixing signals corresponding to ?/(n+1) and i varying from 1 to n.Type: GrantFiled: December 1, 2004Date of Patent: March 17, 2009Assignee: Semiconductor Ideas to Market (ITOM) B.V.Inventor: Wolfdietrich Georg Kasperkovitz
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Patent number: 7506017Abstract: A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit×N/2-bit multipliers. Because the same circuitry can be used to serve as both an N×N multiplier and as dual N/2×N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e.g., duplex multipliers with N values of 16 or more) are used.Type: GrantFiled: May 25, 2004Date of Patent: March 17, 2009Assignee: Altera CorporationInventor: Guy Dupenloup
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Patent number: 7487196Abstract: Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating. The result of the multiplier can be stored in a result register in unsaturated form. The output of the result register can then be saturated and provided to addition and subtraction logic to allow efficient implementation of a saturating multiplier.Type: GrantFiled: August 12, 2004Date of Patent: February 3, 2009Assignee: Altera CorporationInventor: Paul Metzgen
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Publication number: 20090003695Abstract: A signal correcting method and a circuit thereof are provided. In the method, first, the values of a plurality of input signals are clamped to generate a plurality of corresponding clamping signals according to a plurality of adjustable predetermined values. Then, a combined multiplication operation is performed to the clamping signals according to the coefficients in a matrix obtained by multiplying the coefficients in at least two predetermined correcting matrixes, so as to output a plurality of results. Next, the results are respectively clamped according to a plurality of corresponding predetermined thresholds so as to output the corrected input signals.Type: ApplicationFiled: September 26, 2007Publication date: January 1, 2009Applicant: NOVATEK MICROELECTRONICS CORP.Inventor: Ming-Feng Chiang
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Publication number: 20090006509Abstract: The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0.q?1q?2 . . . q?n), then the algorithm provides for computing S = AB D to yield a w-bit quotient Q and w-bit remainder R by: (1) determining the next quotient digit q?j using a quotient digit selection function; (2) generating the product q?jD; and (3) performing the triple addition of rRj?1, (?q?jD) and b - ( j - 1 ) ? ( A r ) where R0=b?1Ar?1. The recurrence relation may be implemented with carry-save adders for computation using bitwise logical operators (AND, OR, XOR).Type: ApplicationFiled: June 28, 2007Publication date: January 1, 2009Inventors: Alaaeldin Amin, Muhammad Waleed Shinwari
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Publication number: 20080275932Abstract: In the course of performing an Elliptic Curve Scalar Multiplication operation by Additive Splitting Using Division, a main loop of an integer division operation may be performed. The integer division has a dividend and a divisor. By storing both the divisor and the negative value of the divisor, susceptibility to a Simple Power Analysis Side Channel attack is minimized. A carry bit from a previous iteration of the main loop determines which of the divisor or the negative of the divisor to use. The order of an addition operation and a shift left operations in the main loop is interchanged compared to a known integer division method and there are no negation operations in the main loop.Type: ApplicationFiled: February 29, 2008Publication date: November 6, 2008Inventor: Nevine Maurice Nassif Ebeid
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Publication number: 20080225939Abstract: The present invention discloses a multifunctional video encoding circuit system capable of performing six types of operations: addition, subtraction, multiplication, multiply-accumulation, interpolation, and absolute difference summation. A partial product generation part, a partial product reduction part and an accumulation part of the circuit system are equipped with a virtual power suppression unit each for reducing the power consumption of the partial product generation part, the partial product reduction part and the accumulation part, so as to reduce the power consumption of the multifunctional video encoding circuit system.Type: ApplicationFiled: March 15, 2007Publication date: September 18, 2008Inventors: JIUN-IN GUO, KUAN-HUNG CHEN, JINN-SHYAN WANG, YU-MIN CHEN, YUAN-SUN CHU
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Publication number: 20080222226Abstract: Multiplication engines and multiplication methods are provided for a digital processor.Type: ApplicationFiled: January 10, 2008Publication date: September 11, 2008Applicant: Analog Devices, Inc.Inventors: Andreas D. Olofsson, Baruch Yanovitch
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Publication number: 20080208940Abstract: A reconfigurable circuit including a multiplier for multiplying a value, an accumulator for cumulatively adding said multiplied value and a round-off processing unit for rounding off said cumulatively added value; wherein said multiplier, said accumulator and said round-off processing unit are disposed within a single processing element and said accumulator provides an output at a timing according to a control signal.Type: ApplicationFiled: February 21, 2008Publication date: August 28, 2008Applicant: FUJITSU LIMITEDInventor: Hiroshi FURUKAWA
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Patent number: 7418468Abstract: Low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits, suitable for analog decoders, for example, are provided. The circuits include multiplier modules that receive first input signals and respective ones of a plurality of second input signals. Each multiplier module generates as output signals products of the first input signals and its respective second input signals. Dummy multiplier modules that respectively correspond to the multiplier modules receive the second input signals, and each dummy multiplier module forms products of the second input signal of its corresponding multiplier module and the other second input signals. The dummy multiplier modules reduce the overall voltage requirements of the circuit, thereby providing for low-voltage operation.Type: GrantFiled: February 10, 2005Date of Patent: August 26, 2008Assignee: University of AlbertaInventors: Chris J. Winstead, Christian Schlegel
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Patent number: 7395300Abstract: Presented herein are systems and methods for computing the product of a constant and a mixed number power of two. A circuit comprises a first register, a second register, a memory, a third register, and a multiplier circuit. The first register stores the constant. The second register stores the integer portion and the fraction portion. The memory stores a plurality of values, each of said plurality of values corresponding to a particular one of a corresponding plurality of fractions, wherein each one of said plurality of values is two to the exponential fraction corresponding to the one of said plurality of values. The third register stores a particular one of the plurality of values, said particular one of the plurality of values corresponding to the fraction portion. The multiplier circuit multiplies the contents of the third register by the contents of the first register, thereby resulting in a product.Type: GrantFiled: January 27, 2004Date of Patent: July 1, 2008Assignee: Broadcom CorporationInventors: Sunoj Koshy, Arun Rao
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Patent number: 7395299Abstract: An apparatus and method for efficiently calculating an intermediate value between a first end value such that the area and time required to implement this operation is minimized is described. The apparatus and method may be used to efficiently multiply a value by a fraction. A fraction is involved in calculating an intermediate value and also for multiplying by a fraction. When the denominator of the fraction is odd, the binary representation of the blending function, which is used to calculate an intermediate value, exhibits special characteristics. The special characteristics allow the present invention to, among others, avoid the use of multipliers, which require a large number of gates to implement. The method and apparatus described exploit this and other special characteristics in order to efficiently implement in hardware the blending function and to efficiently multiply a value by a fraction.Type: GrantFiled: June 23, 2003Date of Patent: July 1, 2008Assignee: Intel CorporationInventors: Tom Altus, Jacob D. Doweck
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Publication number: 20080144812Abstract: The system and method for performing iterative scalar multiplication which is protected against address bit attack is provides a methodology, and system for implementing the methodology, for performing an iterative scalar multiplication process utilizing the Takagi algorithm, the most-to-least binary algorithm, or the least-to-most binary algorithm, modified with either a simultaneous register access operation (SRA) or a general simultaneous register access operation (GSRA). Further, a level-based randomization scheme may be added to provide further security to the algorithms.Type: ApplicationFiled: December 19, 2006Publication date: June 19, 2008Inventors: Theeb A. Al-Gahtani, Mohammad K. Ibrahim
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Patent number: 7389317Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.Type: GrantFiled: April 9, 2002Date of Patent: June 17, 2008Assignee: Texas Instruments IncorporatedInventors: Karl M. Guttag, Christopher J. Read, Keith Balmer
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Publication number: 20080109506Abstract: A data transformation method capable of saving numeral operations, the data transformation method includes encoding a plurality of digital data to generate a plurality of sets of byte data according to an encoding mode, determining a plurality of repetition patterns of the plurality of sets of byte data, processing shift operations on the plurality of sets of byte data to generate a plurality of sets of shifted byte data according to positions of the plurality of repetition patterns located in the plurality of sets of byte data, processing addition operations on the plurality of sets of shifted byte data.Type: ApplicationFiled: January 25, 2007Publication date: May 8, 2008Inventors: Hung-Lun Chien, De-Yu Kao
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Publication number: 20080104163Abstract: A method for sampling includes selecting and sampling at uniform time steps over a collection time that is more than one period. Reordering the collected samples into “one period” and transforming the period from the time domain to the frequency domain.Type: ApplicationFiled: October 30, 2006Publication date: May 1, 2008Inventor: Lee A. Barford
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Publication number: 20080104164Abstract: A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.Type: ApplicationFiled: October 26, 2006Publication date: May 1, 2008Inventors: Himanshu Kaul, Mark A. Anders, Sanu Mathew, Ram Krishnamurthy
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Publication number: 20080065714Abstract: For calculating a result of a modular multiplication with long operands, at least the multiplicand is divided into at least three shorter portions. Using the three shorter portions of the multiplicand, the multiplier and the modulus, a modular multiplication is performed within a cryptographic calculation, wherein the portions of the multiplicand, the multiplier and the modulus are parameters of the cryptographic calculation. The calculation is performed sequentially using the portions of the multiplicand and using an intermediate result obtained in a previous calculation, until all portions of the multiplicand are processed, to obtain the final result of the modular multiplication.Type: ApplicationFiled: October 27, 2006Publication date: March 13, 2008Applicant: INFINEON TECHNOLOGIES AGInventor: Wieland Fishcher
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Publication number: 20080021947Abstract: A processor includes a triple-base-number-system (TBNS) Arithmetic Unit architecture. TBNS processing enables extremely high-performance digital signal processing of larger word-size data, and enables a processor architecture having reduced hardware complexity and power dissipation. With demanding signal processing applications a TBNS processing is much more efficient as compared to either traditional SBNS or even DBNS. In a processor, a Multiplication Unit comprises at least three Adders to each add an extracted pair of like powers of two numbers to be multiplied. A result of one Adder controls a number of bits of shift of a barrel shifter, and a result of remaining Adders are input to a lookup table feeding the barrel shifter. A register holds an output of the barrel shifter. TBNS processing system includes a binary-to-TBNS data converter adapting a Binary-Search-Tree and Range Table to convert binary data/numbers into TBNS representation.Type: ApplicationFiled: July 18, 2006Publication date: January 24, 2008Inventors: Amitabha Sinha, Pavel Sinha, Kenneth Alan Newton, Krishanu Mukherjee
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Publication number: 20080005218Abstract: A computer is connected to a memory. The computer to execute an encryption program in the memory. The encryption program including a multiplication portion to perform multiplication of input operands. The multiplication portion includes graph based functions to generate coefficients representing products returned from the multiplication portion to generate encryption keys. Other embodiments are described and claimed.Type: ApplicationFiled: June 28, 2006Publication date: January 3, 2008Inventors: Michael E. Kounavis, Arun Raghunath
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Publication number: 20070299899Abstract: Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Inventors: William C. Hasenplaugh, Gunnar Gaubatz, Vinodh Gopal, Matthew M. Bace
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Publication number: 20070255780Abstract: A multiplication and division puzzle and method of making thereof include a main table having a plurality of cells in rows and columns, the cells being filled with products and multipliers. A template having a plurality of cells that correspond to the plurality of cells in the main table has selected cells removed to form openings therein to reveal a set of product clues in the main table when the template is superimposed or laid thereon. The product clues include the products in the cells of the main table. The non-selected cells that remain in the template, concealing the multiplier answer and non-selected product answers in the main table. The main table and template are used to form a puzzle blank having a plurality of cells containing the set of product clues and empty cells for the user to fill in missing product answers. The main table contains all of the product and multiplier answers.Type: ApplicationFiled: February 8, 2007Publication date: November 1, 2007Inventor: Lyndon O. Barton
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Patent number: 7266579Abstract: Integrated circuit parallel multiplication circuits, including multipliers that deliver natural multiplication products and multipliers that deliver polynomial products with coefficients over GF(2). A parallel multiplier hardware architecture arranges the addition of partial products so that it begins in a first group of adder stages that perform additions without receiving any carry terms as inputs, and so that addition of the carry terms is deferred until a second group of adder stages arranged to follow the first group. This intentional arrangement of the adders into two separate groups allows both the polynomial product to be extracted from the results of the first group of additions, and the natural product to be extracted from the results of the second group of additions.Type: GrantFiled: July 7, 2003Date of Patent: September 4, 2007Assignee: Atmel CorporationInventors: Vincent Dupaquis, Laurent Paris
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Patent number: 7240204Abstract: Scalable and unified multipliers for multiplication of cryptographic parameters represented as elements of either of the prime field (GF(p)) and the binary extension field (GF(2m)) include processing elements arranged to execute in pipeline stages. The processing elements are configurable to perform operations corresponding to either the prime field or the binary extension field. In an example, the processing elements include a dual-field adder having a field-select input that permits selection of a field arithmetic. In a representative example, multipliers are implemented as integrated circuits having processing units that each receive a single bit of one operand and partial words of the remaining operand.Type: GrantFiled: August 11, 2000Date of Patent: July 3, 2007Assignee: State of Oregon Acting by and through the State Board of Higher Education on behalf of Oregon State UniversityInventors: Çetin K. Koç, Erkay Savas, Alexandre F. Tenca
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Patent number: 7212959Abstract: A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for directing initial inputs and intermediate result values.Type: GrantFiled: August 8, 2001Date of Patent: May 1, 2007Inventors: Stephen Clark Purcell, Scott Kimura, Mark L. Wood Patrick
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Patent number: 7213043Abstract: A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.Type: GrantFiled: January 21, 2003Date of Patent: May 1, 2007Assignee: LSI Logic CorporationInventor: Mikhail I. Grinchuk
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Patent number: 7206801Abstract: A digital Parallel Multiplier has a Partial Product Generator, a First Stage Adder Circuit and a Final Stage Adder Circuit. The spurious switching in the First Stage Adder Circuit may be substantially reduced by synchronizing the input signals to the Adders in First Stage Adder Circuit. The reduced spurious switching reduces the power dissipation of the Multiplier. The timing of the input signals is synchronized by means of the Latch Adders having a Latch that is an integral part of an Adder. Consequently, the power dissipation and hardware overheads of the Latch Adders are low. The Latch Adders may be controlled by Control Signals, which may be generated by Control Circuits. The application of the Latch Adders may be applied to the Final Stage Adder Circuit to further reduce spurious switching and thereby further reduce the power dissipation.Type: GrantFiled: May 14, 2003Date of Patent: April 17, 2007Assignees: Chang, Joseph Sylvester, Gwee, Bah HweeInventors: Joseph Sylvester Chang, Bah Hwee Gwee, Kwen Siong Chong
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Patent number: 7200194Abstract: A method for processing a received signal at a mobile receiver of a wireless communications system is disclosed. The method comprises demodulating the received signal to obtain an analog base band signal and converting the analog base band signal into a digital base band signal. The signal strength of the digital base band signal is estimated and, using the estimation, the digital base band signal is scaled by a scaling factor. The digital base band signal is equalized into an equalized digital signal which is then rescaled by a resealing factor.Type: GrantFiled: October 11, 2002Date of Patent: April 3, 2007Assignee: Spreadtrum Communications CorporationInventors: Jingdong Lin, Shengquan Hu, Jin Ji, Ying Tian, Datong Chen
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Patent number: 7194498Abstract: A circuit and methodology for higher radix multiplication with improved partial product generation. The invention relates to the design of a high precision multiplier for an arithmetic unit of a digital processor.Type: GrantFiled: February 25, 2002Date of Patent: March 20, 2007Assignee: Southern Methodist UniversityInventors: David William Matula, Peter-Michael Seidel, Lee D. McFearin
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Patent number: 7177894Abstract: A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a switching-reduction circuit that outputs a signal to a subsequent digital circuit. The value of the signal may depend on the relevance of the signal value to a next output of the subsequent digital circuit. A method according to various aspects of the present invention includes receiving a next input signal. The method further includes determining whether the next input signal may be relevant to a next output of a subsequent digital circuit. The method further includes providing the next input signal to the subsequent digital circuit when the next input signal may be relevant to the next output of the subsequent digital circuit, and providing a previous signal to the subsequent digital circuit when the next input signal will not be relevant to the next output of the subsequent digital circuit.Type: GrantFiled: August 28, 2003Date of Patent: February 13, 2007Assignee: Broadcom CorporationInventor: Christian Lutkemeyer
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Patent number: 7159004Abstract: An adder includes a first XOR element for generating an XOR output of the first and the second data inputs, a first multiplexer for selecting one of the first carry input or the first data input while the XOR output is made a selection signal, a second multiplexer for selecting one of the second carry input or the second data input, a third multiplexer for selecting one of the first or the second carry inputs while the carry selection input is made a selection signal, and a second XOR element for generating an XOR output of an output of the third multiplexer and the XOR output, and is characterized in that an output of the first multiplexer is made a first carry output, an output of the second multiplexer is made a second carry output, and an output of the third multiplexer is made an addition value.Type: GrantFiled: August 27, 2003Date of Patent: January 2, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Kimito Horie
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Patent number: 7080114Abstract: A high speed scalable multiplier. The high speed scalable multiplier can include a folding multiplier configured to fold multiplicands and multipliers where individual ones of the multiplicands and multipliers exceed a folding threshold. The folding multiplier also can compute a product of the multiplicands and multipliers based on less than all bits forming the multiplicands and multipliers. The high speed scalable multiplier also can include a conventional multiplier and at least one additional folding multiplier, each of the multipliers being individually, selectably activatable.Type: GrantFiled: December 4, 2001Date of Patent: July 18, 2006Assignee: Florida Atlantic UniversityInventor: Ravi Shankar
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Patent number: 7062526Abstract: A functional unit in a digital system is provided with a rounding Multiplication instruction, wherein a most significant product of first pair of elements is combined with a least significant product of a second pair of elements, the combined product is rounded, and the final result is stored in a destination. Rounding is performed by adding a rounding value to form an intermediate result, and then shifting the intermediate result right. A combined result is rounded to a fixed length shorter than the combined product.Type: GrantFiled: October 31, 2000Date of Patent: June 13, 2006Assignee: Texas Instruments IncorporatedInventor: David Hoyle
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Patent number: 7024444Abstract: There is disclosed a multiplier circuit for use in a data processor. The multiplier circuit comprises a partial products generating circuit that receives a multiplicand value and a multiplier value and generates a group of partial products. The multiplier circuit also comprises a split array for adding the partial products. A first summation array comprises a first group of adders that sum the even partial products to produce an even summation value. A second summation array comprises a second group of adders that sum the odd partial products to produce an odd summation value. The even and odd summation values are then summed to produce the output of the multiplier.Type: GrantFiled: July 21, 2003Date of Patent: April 4, 2006Assignee: National Semiconductor CorporationInventor: Daniel W. Green
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Patent number: 6993551Abstract: A method for reducing computational steps in a digital processor including multiplications producing a plurality of multiplication products. This method specifies a desired multiplication function to be implemented in a digital processor, the desired multiplication function having a respective set of initial coefficients corresponding to each digital multiplier stage of the multiplication function. An initial total number of non-zero bits of the initial coefficients is determined and the initial coefficients are modified. Further, a resulting number of non-zero bits in the modified set of coefficients is quantified. Finally, the modified set of coefficients that result in a reduced number of non-zero bits as compared to the initial coefficients is chosen. The new modified coefficients are implemented in the device by constructing the digital multiplier stages with the modified coefficients.Type: GrantFiled: April 12, 2002Date of Patent: January 31, 2006Assignee: Visteon Global Technologies, Inc.Inventors: J. William Whikehart, Christopher John Hagan
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Patent number: 6993071Abstract: A multiplier device for multiplying one of a discrete set of digital level values with a filter coefficient in a filter device implemented in a decision feedback equalizer including (i) a decoder device for receiving a discrete digital level value to be multiplied and for generating control signals according to the digital level value, (ii) an inverter circuit providing two parallel operations, each operation including multiplying the determined number by either +1/?1 in accordance with the control signals for generating two intermediate results, (iii) a multiplier circuit receiving the two intermediate results and providing respective parallel operations for multiplying a corresponding intermediate result by +1 or zero (0) in accordance with a control signal and generating further intermediate results, (iv) a logic circuit for shifting bits of one further intermediate result to effect a multiplication of one of the further intermediate output result with a discrete digital level value different than any of tType: GrantFiled: March 20, 2001Date of Patent: January 31, 2006Assignee: Koninklijke Philips Electronics, N.V.Inventor: Dagnachew Birru
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Patent number: 6993550Abstract: The invention relates to a fixed point multiplying apparatus and method using an encoded multiplicand. The multiplicand is encoded into an independent binary system instead of a conventional binary system and each bit value of the encoded multiplicand is used as a control signal about an inputted multiplier in order to effectively execute a fixed point multiplication used in a transform algorithm such as the DCT (Discrete Cosine Transformation) in use for a multimedia codec. The multiplication is executed at a high speed with a simple structure and a small gate number.Type: GrantFiled: April 15, 2002Date of Patent: January 31, 2006Assignee: Electronics and Telecommunications Research InstituteInventor: Jin Wuk Seok
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Patent number: 6959316Abstract: A data processor, such as a DSP, includes a multiplier block having a multiplier front end for generating partial products from input operands, and further includes a plurality of ALUs having inputs that are switchably or programmably coupled, in a first mode of operation, to first data sources representing outputs of the multiplier front end. In the first mode of operation the ALUs add together partial products received from the multiplier front end to arrive at a multiplication result. In a second mode of operation the inputs of the plurality of ALUs are switchably or programmably coupled to second data sources for performing at least one of arithmetic and logical operations on data received from the second data sources.Type: GrantFiled: November 29, 2000Date of Patent: October 25, 2005Assignee: Nokia Mobile Phones LimitedInventor: Jari A. Parviainen
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Patent number: 6940920Abstract: A multiplier arrangement (MUXER) is adapted to generate from analog phase information and from high-frequency local oscillator signals, components of a high-frequency phase vector (PV), and to synthesise said high-frequency phase vector (PV) from said components within a summing means is further adapted to provide said high-frequency phase vector (PV) as a vector which is making an excursion alongside the contours of a square within the complex plane during a first category of predetermined transitions of a phase signal (?) on which said analog phase information is dependent. A signal modulator including such a multiplier arrangement as well as a transmitter are described as well.Type: GrantFiled: May 16, 2001Date of Patent: September 6, 2005Assignee: AlcatelInventors: Joannes Mathilda Josephus Sevenhans, Bart Verstraeten, Silvio Taraborrelli
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Patent number: 6934728Abstract: A method and processor for multiplication operation instruction processing are provided. Multiplication operation instructions are executed on source operands in data memory locations. The multiplication operation instructions are provided to perform complex multiplication operations. The multiplication operation instructions may generate the square of a multiplication source operand and generate the difference of a subtrahend source operand and a minuend source operand simultaneously. The square is output to a target accumulator specified in the multiplication operation instruction. The difference is output to a difference register specified in the multiplication operation instruction. In the alternative, the multiplication operation instructions may generate the sum of the square of multiplication source operand and an addition operand as well as generate the difference of a subtrahend source operand and a minuend source operand simultaneously.Type: GrantFiled: June 1, 2001Date of Patent: August 23, 2005Assignee: Microchip Technology IncorporatedInventor: Michael I. Catherwood