Abstract: A method of communicating with two or more slaves is provided. The method includes receiving a command packet with an interface, wherein the command packet is sent by a master over a master-slave bus and associating a slave address of the command packet with one of two or more slaves communicatively coupled to the interface.

Abstract: An interconnected computer system includes a Peripheral Component Interconnect Express (PCIe) fabric, a first computer system communicatively coupled to the PCIe fabric, a second computer system communicatively coupled to the PCIe fabric, and a shared single-access hardware resource coupled to the PCIe fabric. The first computer system includes a first processor and first memory coupled to the first processor configured to store a first flag indicating a desire of the first computer system to access the shared single-access hardware resource and a turn variable indicating which of the first computer system and the second computer system has access to the shared single-access hardware resource. The second computer system includes a second processor and second memory coupled to the second processor configured to store a second flag indicating a desire of the second computer system to access the shared single-access hardware resource.

Abstract: Disclosed are an inter-core data processing method and system, a system on chip, and an electronic device. The method includes: a first core sends, by means of a command transmission module, to a second core a first command indicating that the first core is ready to perform a data processing operation corresponding to a target address; the second core acquires a mutex corresponding to the target address in response to the first command and returns a second command to the first core by means of the command transmission module; and the first core performs the data processing operation corresponding to the target address by means of a bus module in response to the second command.

Abstract: An image forming apparatus comprises a non-volatile memory storing start-up firmware a volatile memory having a memory space commonly available for the start-up firmware and an operating system of the image forming apparatus; and a control unit configured to copy, to the memory space, a setting value of a setting item for write-protecting the non-volatile memory, among setting items included in the start-up firmware, wherein the operating system acquires and checks the setting value copied to the memory space.

Abstract: Disclosed systems and methods initiate an instance of an isolated application on a node computing device. The systems determine that the isolated application requests exclusive access to a block storage resource, create a control group associated with the block storage resource to provide access to members of the control group and set an access rate limit to zero for non-members of the control group, and assign the isolated application to the control group.

Abstract: Integrated circuit devices and methods for synchronizing execution of program code for multiple concurrently operating execution engines of the integrated circuit devices are provided. In some cases, one execution engine of an integrated circuit device may be dependent on the operation of another execution engine of the integrated circuit device. To synchronize the execution engines around the dependency, a first execution engine may execute an instruction to set a value in a register while a second execution engine may execute an instruction to wait for a condition associated with the register value.

Abstract: A memory system includes a memory device including a plurality of segments; a processor configured to generate a Read-Modify-Write (RMW) command on a target segment address corresponding to a target segment among the plurality of segments; a scheduler configured to receive the RMW command from the processor and schedule the RMW command; and a RMW unit configured to execute the RMW command on the memory device according to control of the scheduler, wherein the scheduler compares, when a plurality of RMW commands received from the processor are pending, target segment addresses of the plurality of RMW commands to re-order the plurality of RMW commands.

Abstract: Provided are a memory device and a memory system. A memory device which is connected to the channel, comprises a memory cell array and a memory-authority control unit which controls operational authority of the channel, wherein the memory device controls data flow of other memory device connected to the channel, when the memory-authority control unit has the operational authority of the channel.

Abstract: A solid state drive with a reset circuit includes a controlling circuit, a flash array and a buffer. The controlling circuit includes a physical layer circuit and a first input/output port. The first input/output port is connected with a first reset terminal of a host. The flash array and the buffer are connected with the controlling circuit. When the first reset terminal of the host activates a reset signal, a voltage level of the first input/output port is changed. After a delay time, the voltage level of a second reset terminal of the physical layer circuit is changed and the physical layer circuit is reset.

Abstract: A memory access control includes a tracker configured to receive cache invalidate (XI) commands from the memory controller and to provide responses to the memory controller and an address storage element in the tracker that stores an address to be locked by one of the processing units. The system also includes a lock required, a cache invalidate (XI) tracker bit, a set input that upon receipt of a set command sets the lock required bit when a first condition is met, a first reset input that resets the lock required bit upon receipt of a reset command; and a second reset input that resets the XI tracker bit. The tracker rejects incoming XI commands from the memory controller when the lock required bit is set, allows incoming XI commands when the lock bit is not set and sets the XI tracker bit when a first incoming XI command is received.

Abstract: A method of and system for performing metadata tag compression in security policy enforcement system may comprise conveying a set of data elements, each with an associated metadata tag, from a first processor subsystem to a second processor subsystem. The first processor subsystem may be configured to process conventional tasks, the second processor configured to apply one or more policy decisions to the data element. The conveying may further comprise sending the set of data elements along with an index element that identifies one or more metadata tags, and sending one or more of the metadata tags identified by the index element.

Abstract: A computer-implemented method of delegating an object in an object library to a computer application having multiple execution threads includes, in certain embodiments, registering at least some of the execution threads with the object library; executing a first registered execution thread to access the object; generating delegation information; associating the object with the generated delegation information; and delegating the object to a second registered execution threads based on the delegation information, thereby ensuring sequential delegation of the object, without locking thereof, in the registered execution threads of the computer application.

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

Abstract: Disclosed herein are a data protection apparatus and method for a smart device. The data protection apparatus for a smart device includes a detection unit for detecting unauthorized activity in a bootloader of the smart device, based on whether a program for acquiring an administrator privilege has been installed and whether a compressed-command file is present, during a procedure for loading the bootloader, and a data access blocking unit for, when the unauthorized activity is detected, performing an operation of locking the smart device, thus blocking access to data in the smart device.

Abstract: In a system where multiple controllers share a link interface but are not all (1) compatible with the same configuration of the physical layer or (2) using the same clocking, a configuration arbitration subsystem intercepts, organizes, and re-clocks configuration-access requests from the various controller agents. Priorities are assigned according to stored policies. The configuration arbiter grants configuration access to the top-priority agent, synchronizing the agent's message with the arbiter's clock. Lower-priority agents' messages are stored in command queues until they ascend to top priority. Besides preventing timing conflicts and streamlining the coordination of clocks, the configuration arbiter may provide access to physical-layer registers beyond the controllers' built-in capabilities to further optimize configuration.

Abstract: A circuit arrangement that includes master circuits generating access transactions, and each access transaction includes an address, a interconnect master identifier, and a system management master identifier. A slave circuit is coupled to the one or more master circuits and is configured to generate responses to the access transactions. Each response includes an interconnect master identifier from one of the plurality of access transactions. An interconnect circuit routes the access transactions to the slave circuit and routes the responses to the one or more master circuits according to the interconnect master identifiers. Exclusive access control circuitry controls exclusive access to the slave circuit based on the value of the system management master identifiers and addresses in the access transactions.

Abstract: Methods, systems, and devices are described for controlling a sprinkler system, including an apparatus for sprinkler system control that includes a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions are executable by the processor to receive operation instructions for the sprinkler system from a source that is separate from a control panel of the sprinkler system, and operate valves of the sprinkler system independent of instructions from the control panel.

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

Abstract: A method of delaying or blocking new bus resets from propagating while a previous bus initialization (bus reset, tree-id or self-id) is in process during the performance of a IEEE-1394 serial bus. The method provides for more robust Beta only bus operation during high frequency bus resets. The bus resets are caused by noise events, power-up and power-down sequences and other bus reset causing events.

Abstract: A computer-implemented method is disclosed to enhance link anomaly tolerance in a small computer system interface (SCSI) system. The method starts with detecting a SCSI command failed at a SCSI target, where the SCSI target is communicatively coupled with a SCSI initiator through a set of communication links and the failed SCSI command is sent from the SCSI initiator. After detecting the failure, the SCSI target withholds returning a response for the failure. Then the SCSI target checks a status of the set of communication links periodically within the withholding duration while the response for the failed SCSI command is withheld. The SCSI target returns the response for the failed SCSI command upon at least one of two conditions is met: (1) The withhold duration expires; (2) The set of communication links is determined to function normally based on checking the status of the set of communication links.

Abstract: A method and system are provided for monitoring and controlling a mobile device using a supervisory device. In some embodiments, the supervisory device operates in conjunction with the mobile device to monitor an extent of usage of the mobile device as well as to ensure that certain software is being used appropriately. The supervisory device may take one or more responsive actions when an extent of usage of the mobile device reaches a threshold extent of usage, when certain software on the mobile device is not being used appropriately, and/or when certain settings of the mobile device have been changed. The supervisory device may operate in a non-permissible mode and determine that the mobile device is currently enabled. In response to this operation and determination, the supervisory device may disable the mobile device and/or transmit to an external device a notification message.

Abstract: A method of transaction processing includes receiving a plurality of transactions from an execution queue, acquiring a plurality of locks corresponding to data items needed for execution of the plurality of transactions, executing each transaction of the plurality of transactions upon acquiring all locks needed for execution of each transaction, and releasing the locks needed for execution of each transaction of the plurality of transactions upon committing each transaction. The plurality of transactions have a specified order within the execution queue, the plurality of locks are sequentially acquired based on the specified order of the plurality of transactions within the execution queue, and an order of execution of the plurality of transactions is different from the specified order of the plurality of transactions within the execution queue.

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

Abstract: A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal.

Abstract: In an embodiment, an apparatus includes a consuming logic to request and process data including a critical data portion and a second data portion, the data stored in a memory coupled to a processor interposed between the apparatus and the memory. In addition, the apparatus includes a protocol stack logic coupled to the consuming logic to issue a read request to the memory via the processor to request the data and to receive a plurality of completions responsive to the read request. In an embodiment, the protocol stack logic includes a completion handling logic to send data of a first of the completions to the consuming logic before protocol stack processing is completed on the completions. Other embodiments are described and claimed.

Abstract: The processor circuit (1) has a Harvard architecture. This processor circuit includes a calculation unit (2), a first memory element (3a) for data storage and a second memory element (4a) for instruction storage. Said first and second memory elements (3a, 4a) are connected by at least one communication bus (5, 6) to the calculation unit. The processor circuit includes management means (8), placed between the first and second memory elements and the calculation unit and capable of saving several data items or instructions to save time during successive data reading.

Abstract: A concurrency assertions system disclosed herein provides for atomic evaluation of an assertion expression by locking an assertion lock upon initiating an assertion and thereby protecting the assertion evaluation from concurrent modifications to the variables in the assertion expressions. When a violation of an assertion is detected, the concurrency assertions system ensures that the exception statistics at the time of the assertion violation represents a program state where the assertion is violated, thus improving analysis of assertion violations. Furthermore, the concurrency assertions system continuously evaluates an expression for an assertion for a time period while other threads in the program are being executed.

Abstract: The present subject matter discloses methods and systems of sharing of peripheral devices in multi host computing systems (100). In one implementation, the method of sharing a peripheral device (116) amongst a plurality of hosts of the multi-host computing system (100) comprises receiving a request to switch the peripheral device (116) from a first operating system running on a first host from amongst the plurality of hosts to a second operating system running on a second host from amongst the plurality of hosts; generating a request for the first operating system to relinquish control of the peripheral device (116); determining the status of the relinquishment based on response generated by the first operating system; initiating a request for the second operating system to install a device driver for the peripheral device (116) upon determining successful relinquishment; and transferring ownership of the peripheral device (116) to the second operating system.

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract: Portable communication devices and related methods for use in supporting voice and/or data communication are provided. One example portable communication device includes a housing, a display device disposed at said housing, a processor disposed at least partially within said housing, the processor coupled to said display device, and an interface connector disposed at said housing and coupled to said processor. The interface connector is configured to couple to a module. The processor is configured to communicate, through said interface connector, via a plurality of communication protocols. The processor is configured to select at least one of the plurality of communication protocols based on the module coupled to the interface connector.

Abstract: A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host.

Abstract: Disclosed is a method of synchronizing a plurality of processors accesses to at least one shared resource. One of a plurality of processors requests an exclusive region lock for a shared resource using a logical block address (LBA) of a dummy target. The LBA is defined in a region map that associates LBAs to shared resources. The exclusive region lock request is inserted as a node in a region lock tree of the dummy target. Access to the shared resource is granted based on a determination whether there is an existing region lock in the region lock tree that is overlaps with the new exclusive region lock request.

Abstract: A method is disclosed for retrieving the reservation status information of a storage area network (SAN) device, a host transmits a persistent reservation in command with service action setting of ‘read reservation’ to a first LUN, wherein the host is connected to a port of the data storage server to which the LUN belongs. The host receives a message from the LUN. The host determines that the message is a success. The host sends to the LUN a persistent reservation in command with service action setting of ‘read keys’, responsive to a success message. The host determines that the LUN responds with a zero data length. The host determines the LUN is reserved with type 2 reservation, responsive to a determination that the LUN responds with a non-zero data length.

Abstract: A system and computer program product are disclosed for retrieving the reservation status information of a storage area network (SAN) device, a host transmits a persistent reservation in command with service action setting of ‘read reservation’ to a first LUN, wherein the host is connected to a port of the data storage server to which the LUN belongs. The host receives a message from the LUN. The host determines that the message is a success. The host sends to the LUN a persistent reservation in command with service action setting of ‘read keys’, responsive to a success message. The host determines that the LUN responds with a zero data length. The host determines the LUN is reserved with type 2 reservation, responsive to a determination that the LUN responds with a non-zero data length.

Abstract: The present invention relates to a far-end control method with a security mechanism including a host transmitting an identification code through the PSTN (Public switched telephone network) to the I/O control device of the far-end. The I/O control device has a CPU to receive the identification code and judge whether the identification code matches with the predetermined value stored therein; if the identification code matches with the predetermined value, the mobile internet connection between the host and the I/O control device is activated to enable the host to mutually transmit information or signals with a far-end control device from the I/O control device through the mobile internet, and the connection will be disabled after the information or signal transmission is completed.

Abstract: A network switch configures a static forwarding to a packet processor by suppressing packet switching and forwards all traffic received on a group of ports a trunk port for aggregation. A trunk header is overloaded with message classification information for use at the downstream packet processor. Routing logic retrieves the packet classification information and stores the information in control fields that are ignored due to the static forwarding and local switching disablement. The static forwarding forwards the packet, with the appended classification information, to a packet processor via the aggregation port. Packet classification information is indicative of the type of the message traffic and is performed upon packet arrival at the switching device.

Abstract: Present techniques involve systems and methods for driving a synchronous bus by implementing repeaters along the bus to restore and/or amplify a signal transmitted through the bus. In one embodiment, a repeater may be implemented at different sections of a synchronous bus, and each repeater may be activated according to where a signal is to be transmitted. In another embodiment, decoders may be configured to each repeater on the synchronous bus. As a signal directed to a section of a bus is transmitted through the bus, each sequential decoder may identify the bus section to which a signal is directed. The decoder may enable its corresponding repeater based on the bus section to which the signal is directed, such that all repeaters along the bus which come before the signal destination may be enabled to allow signal transmission through the bus and signal restoration by the repeaters.

Abstract: A method for processing commands on a host channel adapter includes a host channel adapter receiving data from a host connected to the host channel adapter. The command includes an instruction, identification of packet data, and a length field. The host channel adapter extracts a length of the command from the length field, generates a scoreboard mask based on the length, where the scoreboard mask includes unused bits in the scoreboard preset, and sets, with each portion of the data received, a corresponding bit in a scoreboard. The host channel adapter further determines that the size of the data received for the command matches the length using the scoreboard, issues a kick on the host channel adapter when a size of the data received for the command matches the length, executes, in response to the kick, the instruction on a pipeline, and sends the packet data on a network.

Abstract: A data transfer apparatus performing data communication by transmitting a bus use request to an arbiter between a plurality of nodes coupled in a tree shape through a bus is provided. The data transfer apparatus includes a request generation circuit which generates a highest priority request indicating that a priority level for using the bus is the highest, a determination circuit which determines the priority level of the highest priority request, and a priority level setting circuit which determines the highest priority request which takes priority based on a result of the determination circuit when a plurality of highest priority requests conflicts in a node.

Abstract: A bus system of a system on chip (SoC) includes a first and a second masters, a first slave, and a first and a second control modules. The control modules generates a first and a second access control state signals in response to a first locking access preparation request signal from a corresponding master. The access control signals are broadcasted between the first and the second control modules through a communication channel. A method of operating a bus system in a locked access mode includes allowing one of masters to access one of slaves through a control module and restricting other masters from accessing the one of slaves through other control modules connecting the other masters and the one of slaves in accordance with a control state signal.

Abstract: A Device-to-Device Communication Bus protocol may facilitate transmission of a two to four byte packet by any device sharing the bus. All devices on the bus may monitor the bus, receiving all packets transmitted by other devices and recognizing when they may initiate transmission. The first byte of the packet may be an Address byte uniquely identifying the sender and allowing hardware arbitration to uniquely select one of any number of senders who may wish to transmit and begin transmission simultaneously. Arbitration may take place during transmission of the Address byte, with the transmitting device monitoring a bus bit value as it is transmitting the Address byte. If the data value observed by the transmitting device doesn't match the transmitting device's desired transmit value, the transmitting device may recognize loss of arbitration and suspend transmission to retry once the packet is complete. The receive function in every device may accept the packet as a normal received packet.

Abstract: A processor chip includes data processing elements that each has dedicated to it a respective switch for dynamically establishing an interconnection between the data processing elements conditional upon verification of a validity of the interconnection, which verification is automatically performed by at least one of the data processing elements to be interconnected.

Abstract: A method for arbitrating between a host device and a cellular base band mode for use of a shared SD storage, including requesting, by a cellular base band modem from a host device, access to an SD storage, including writing an access request message, notifying the host device of the access request message, reading, by the host device, the access request message, granting, by the host device, the access request, including writing an access grant message, notifying the cellular base band modem of the access grant message, reading, by the cellular base band mode, the access grant message, holding an SD host bus in a busy state, thereby forcing the host device to hold and not access the bus, accessing, by the cellular base band modem, the SD storage, and upon completion of the accessing, removing the busy state from the SD host bus.

Abstract: The present invention relates to a SPC comprising at least one data processing means for realizing a first data channel 1 and a second data channel 2, and comprising a data transmission means 3 which is connected to data channels 1,2 in a manner such that, using data transmission means 3, data may be transferred from at least one data channel 1, 2 to a higher-order device 5 that is connectable to the controller. The object of the present invention is to further increase the safety of safety controllers. This aim is achieved by providing an active data lock 4, using which it is possible to influence the data transmission—which may be realized using data transmission means 3—to higher-order device 5. As a result, only error-free data are sent via higher-order device 5 to external I/O assemblies.

Abstract: In a methods and systems of controlling a process's access to a device driver, a lock may be used to establish a process wait state or to wake up one or more processes. A spinlock may be used to acquire a lock associated with a device driver. The lock includes a lock value representing the availability of the lock. If the lock value is a first value, the process acquires the lock and sets the lock value to a second value. Otherwise, the process returns to the step of using the spinlock to acquire the lock associated with the device driver. If the lock is acquired, the process accesses the device driver. If the device is not ready, the process is set to wait for the lock. Waiting for the lock comprises setting a field of the process to a pointer to the lock and setting a state of the process to waiting. After the device has been successfully accessed or the process has been set to wait for the lock, the lock is released typically by setting the lock value to the first value.

Abstract: A method, apparatus, and system of exclusive access during a critical sub-operation to enable simultaneous operations are disclosed. In one embodiment, a method of a host device includes identifying a critical sub-operation of an operation associated with a storage system, applying a lock associated with the critical sub-operation based on a type of the sub-operation, providing exclusive access of the critical sub-operation to a first instance requiring the critical sub-operation, denying other instances access to the critical sub-operation during an interval comprising a period when the first instance executes the critical sub-operation, and releasing the lock when the critical sub-operation is no longer required by the first instance. The first instance and the other instances may originate on different host devices.

Abstract: An embedded controller capable of providing direct memory access (DMA) to memory for a host. The controller may include a processor, a memory medium, and an interface coupled to the memory medium. The interface may be configured to couple to a host and receive a DMA request. The DMA request may include a request to read data from a memory location in the memory medium or a request to write data to a memory location in the memory medium. The DMA request may include a relative memory address. The interface may be configured to translate the relative memory address into a first address of the memory medium. Accordingly, the interface may perform operations according to the DMA request using the first address of the memory medium. The processor may be configured to operate according to data stored in the memory medium.

Abstract: A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator. Upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

Abstract: A method is disclosed to control access to stored information. The method supplies a control unit in communication with a computing device and in communication with stored information. If the computing device requests access to that stored information, the method determines if access to the stored information is available. When access to the stored information becomes available, then the method reserves a communication pathway interconnecting the control unit and the requesting computing device, thereby disallowing the sending of non-MPLF unsolicited status via that reserved communication pathway, and provides a message to the computing device, using that reserved communication pathway, granting access to the stored information.

Abstract: A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host.