Abstract: In a computer system having a logical-partitioned server, each partition of the server is provided with its own separate lock and access corridor, in addition to a global lock. When the locking of a partition lock is followed by the locking of the global lock, the system is serialized. The partition locks are controlled by system firmware on behalf of an OS isolating each partition; however, the global lock is controlled by the system firmware to be unlocked independent of the lock/unlock status of the partition locks. In this manner, the ability or inability of an OS that issued a machine check interrupt to unlock its partition lock after the machine check analysis is complete is irrelevant; once the machine check analysis is complete, the system firmware unlocks the global lock, giving other partitions access to shared system resources to run their own machine checks.

Abstract: A distributed shared memory system having a memory access request transaction queue having a plurality of queue slots prevents occurrences of deadlocks. The distributed shared memory system is implemented in a networked multiprocessor computing system, and includes, in each coherency controller of each of the memories in the system, a mechanism to reserve at least one slot of the memory access request transaction queue for exclusive processing of processor return (PR) transactions to provide an uninterrupted processing of PR transactions. The number of blocking (BL) transaction is limited to a number less than available slots. The distributed shared memory system also includes a distributed memory return transaction queue that allows each of entries in the memory access request transaction queue to add a plurality of memory return transactions per clock cycle.

Abstract: A method and apparatus for emulating hardware bus lock in a multi-architecture computer system includes a fault handler that acquires a semaphore reserved for bus lock and a semaphore that limits access to a page table. The fault handler includes an emulation module that sets a mode bit to prevent the bus lock and allows re-execution of the instruction that caused a request for a hardware bus lock. Using this method, the fault handler ensures a minimum disruption to operation of the computer system by restricting access to the least amount of computer system resources.

Abstract: A data processing system includes a global promotion facility and a plurality of processors coupled by an interconnect. In response to execution of an acquisition instruction by a first processor among the plurality of processors, the first processor transmits an address-only operation on the interconnect to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor among the plurality of processors. In response to receipt of a combined response for the address-only operation representing a collective response of others of the plurality of processors to the address-only operation, the first processor determines whether or not acquisition of the promotion bit field was successful by reference to the combined response.

Abstract: Systems and methods are described for resource locking and thread synchronization in a multiprocessor environment. One method includes restricting access to a protected shared resource by use of a lock; issuing the lock to a requesting software to permit access to the protected shared resource; indicating the issuance of the lock to the requesting software by writing a first value to a lock register; freeing the lock, thereby making the lock available for use by another requesting software, after the requesting software completes accessing the protected shared resource; and indicating that the lock is free by writing a second value to the lock register.

Abstract: Security systems for computers connected to networks transmitting packets are disclosed. One disclosed system includes a security agent and a local security device featuring a network hardware connector, a computer hardware connector, a flash memory and a microprocessor to perform a software instruction. The security agent closes the security device by altering a setting of a bit of the flash memory. Further disclosed is a firewall on a single chip for providing security to a network transmitting packets. The firewall includes a network hardware connector, a memory for storing a rule and a software instruction for examining each packet and a microprocessor. Preferably the rule is configurable by a user and the memory includes at least one displayable Web and Web server functionally for serving a Web page and accepting a command from a user such that said at least one rule is determined by the command.

Abstract: A computer processor includes a number of register pairs LOCKADD/LOCKCOUNT to hold values identifying when a computer resource is locked. The LOCKCOUNT register is incremented or decremented in response to lock or unlock instructions, respectively. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. In embodiments without LOCKOUT registers, the lock may be freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header in which two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.

Abstract: A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a STATUS_FULL signal when the queue is full of commands and a STATUS_EMPTY signal when the queue is empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control provides a QUEUE_FULL signal in response to either (1) the STATUS_FULL signal or (2) the DEBUG signal and not the STATUS_EMPTY signal to split further commands or stall the data bus.

Abstract: A microcomputer and an information processing system protect data stored therein and secure the safety of the data. The microcomputer (1) has a memory (3), a read protect register (13), and a write protect register (14). The protect registers store addresses that represent protected areas in the memory where an access from the outside is prohibited. If an access from the outside involves an address of the protected areas, the access to the memory is disabled.

Abstract: If an uncachable write from a processor 300 is held in a processor request buffer 130 when a request control circuit 180 detects that a transaction for a cachable read to the processor 300 has been issued to a system bus 400, a retry control circuit 160 requests the transaction to be retried so as to prevent reversal in sequence between a preceding uncachable write and a following cachable read.

Abstract: A method for efficiently detecting bus contention from a register transfer level (RTL) description is provided. A bus contention occurs if more than two components try to propagate data onto a bus at the same time. The provided method simulates possible input combinations and detects whether there is a possibility for a bus contention. In addition, the provided method is designed for testability, therefore using the method, the designer may identify contention that may exist in test mode at the RTL level of the design even when such conditions may not occur in system mode. The method provides the designer with the input combination as well as the RTL statement that caused the contention. The method detects the bus contention by simulating a small number of input combinations.

Abstract: A distributed shared memory system having a memory access request transaction queue having a plurality of queue slots prevents occurrences of deadlocks. The distributed shared memory system is implemented in a networked multiprocessor computing system, and includes, in each coherency controller of each of the memories in the system, a mechanism to reserve at least one slot of the memory access request transaction queue for exclusive processing of processor return (PR) transactions to provide an uninterrupted processing of PR transactions. The number of blocking (BL) transaction is limited to a number less than available slots. The distributed shared memory system also includes a distributed memory return transaction queue that allows each of entries in the memory access request transaction queue to add a plurality of memory return transactions per clock cycle.

Abstract: According to one embodiment (100) a system may receive a multi-bit input value (DEST_IP) and split it into a number of portions (L1bits, L2bits and L3bits). A first portion (L1bits) can generate a first address (A1) that accesses a first array (116). A first array (116) can provide output values or second array pointer values. Second array pointer values may be combined with a second portion (L2bits) to generate a second address (A2). A second address (A2) can access a second array (118). A second array (118) can provide output values or third array pointer values. Third array pointer values may be combined with a third portion (L3bits) to generate a third address (A3). A third address (A3) can access a third array (120) which can provide output values.

Abstract: An information processing system which makes it possible to protect information stored in the ROM of the system from unauthorized access by means of a debug tool. The information processing system includes a ROM for storing an unlocking program and a user program; a CPU for executing said unlocking program and said user program stored in said ROM; an on-chip debug circuit serving to output debug information of said user program as executed by said information processing system; and a debug function disabling circuit serving to disable debug functions of said on-chip debug circuit at power up and to enable the debug functions of said on-chip debug circuit when said unlocking program has been executed.

Abstract: The present invention comprises a smart retry system for agents in a computer system. The smart retry system of the present invention includes a master agent, a slave agent, an arbiter, and smart retry logic components, all adapted to be coupled to a bus. The bus permits agents coupled to the bus to communicate with the arbiter and other agents coupled to the PCI bus. The smart retry logic component of the present invention prevents a PCI master agent from accessing the bus for the purpose of attempting a retry transaction, until after the slave agent that issued the retry is ready.

Abstract: A method and apparatus for emulating hardware bus lock in a multi-architecture computer system includes a fault handler that acquires a semaphore reserved for bus lock and a semaphore that limits access to a page table. The fault handler includes an emulation module that sets a mode bit to prevent the bus lock and allows re-execution of the instruction that caused a request for a hardware bus lock. Using this method, the fault handler ensures a minimum disruption to operation of the computer system by restricting access to the least amount of computer system resources.

Abstract: An apparatus and method for providing a transient connection port are provided. Further, an apparatus and method for switching between a permanent connection port and a transient connection port are provided. The apparatus and method include a permanent connection port and a transient connection port located at the rear of a rack mounted server system and the front of the rack mounted server system, respectively. The permanent connection port operates when there is an absence of a connected device at the transient connection port. When a device is connected to the transient connection port, a signal is sent to a logic switch which causes the active input to be switched from the permanent connection port to the transient connection port. When the device is no longer connected to the transient connection port, the absence of the signal from the transient connection port causes the logic switch to switch the active input back to the permanent connection port.

Abstract: A method for processing a SCSI bus fault in a SCSI system which has an initiator device and a target device interconnected via a SCSI bus. In response to a control command, the initiator device requests the target device to execute a specific SCSI command. Then, the initiator device processes a normal script phase in response to the SCSI command to transfer the SCSI command to the target device over the SCSI bus. If the fault occurs on the SCSI bus while the SCSI command is transferred to the target device, the initiator device retries the transfer of the SCSI command to the target device a predetermined number of times. Therefore, data damage in the target device due to the SCSI bus fault can be reduced to a minimum.

Abstract: Synchronization services provide a concurrency-safe reader/writer lock supporting a time out feature. The lock can be implemented using lockless data structures to provide efficient synchronization services. Various features such as lock nesting and auto-transformation address common scenarios arising in componentized programs. The lock supports upgrading and suspension, and the time out feature can support an efficient, low-cost optimistic deadlock avoidance scheme. Peculiarities of the reader/writer scenario are addressed in an efficient way to maintain lock stability and consistency, thus providing synchronization services suitable for implementation at the kernel level. In one implementation using event objects, the events are managed for high efficiency and stability of the lock. For multiprocessor machines, a hybrid lock avoids a context switch by behaving as a spin lock before waiting for the lock to become available.

Abstract: A method and apparatus for providing fault detection in an Advanced Process Control (APC) framework. A first interface receives operational state data of a processing tool related to the manufacture of a processing piece. The state data is sent from the first interface to a fault detection unit. A fault detection unit determines if a fault condition exists with the processing tool based upon the state data. A predetermined action is performed on the processing tool in response to the presence of a fault condition. In accordance with one embodiment, the predetermined action is to shutdown the processing tool so as to prevent further production of faulty wafers.

Abstract: A system and signal processing method, in which at least two processors have prioritized, shared access to one or more devices connected along a bus. In preferred embodiments, a fast processor is connected along a first bus, a slow processor and shared device are connected along a second bus, and a communication device is connected between the buses. The communication device is configured to provide the fast processor continuous access to the shared device (in response to grant of an access request by the fast processor) for a limited time that is longer than the time required for a single word transfer, but the slow processor must contend with the fast processor for access to the shared device each time after the slow processor completes a word transfer. Preferably, the communication device provides the fast processor continuous access to the shared device for up to a maximum number of word transfers in response to grant of one access request by the fast processor.

Abstract: A protocol for superimposing status information onto an arbitration scheme between a first bus agent and a second bus agent. One embodiment of the arbitration scheme uses a grant signal and a request signal to arbitrate for use of a bus. The second bus agent may request to use the bus by asserting a request signal, which is received by a bus arbitration circuit. The bus arbitration circuit may or may not reside within the first bus agent. The bus arbitration logic acknowledges the request by asserting a grant signal, which is received by the second bus agent. A specific relationship between an address phase and the arbitration signals allows the first bus agent to pass status information to the second bus agent via the grant signal. The specific relationship between an address phase and the arbitration signals is a condition that typically does not occur where the arbitration signals are used to arbitrate for use of the bus.

Abstract: A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header.

Abstract: Method and apparatus for coordinating access to a shared object amongst a plurality of processes in a distributed system. One process is identified as a lock owner process controlling a lock associated with the shared object. When a process needs to access the shared object, it requests control of the lock from the lock owner process. When no other process controls the lock, the lock owner process grants control to the requesting process. When another process controls the lock, the lock owner process places the requesting process in a queue and waits for the lock to become available. All accesses to the shared object are processed through the lock owner processes thus assuring coordination and synchronization among the processes.

Abstract: A shared bus hang prevention and recovery scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. Some of the masters are associated with the external bus and others are associated with the internal bus, and one of the bus masters is a control master associated with the internal processor. The scheme utilizes a shared bus hang prevention and recovery device having a circuitry and a control code. The circuitry is timing each pending request of the control master for the shared bus and initiating bus recovery if the shared bus is hung up, when the control master exceeded a pre-determined time period allowed for waiting to acquire the shared bus control and complete the transfer on the shared bus.

Abstract: An apparatus is presented for improving the efficiency of data transfers between devices interconnected over an on-chip system bus a multi-master computer system configuration. Bus efficiency is improved by providing an apparatus for controlling a read-modify-write transaction to an address in a bus slave device that does not suspend essential features of the system bus during the transaction, namely, pipelining and transaction splitting. The apparatus includes transaction control logic in a bus master device and transaction response logic in a bus slave device. The transaction control logic provides a write barrier command from the bus master device over the on-chip system bus to the bus slave device. The transaction response logic receives the write barrier command, and precludes execution of future transactions to the address within the bus slave device until completion of the read-modify-write transaction while allowing execution of transactions to other addresses within the bus slave device to complete.

Abstract: A data processing system and method are disclosed for prohibiting access to a SCSI bus prior to a correct entry of an access password. The system includes a plurality of internal SCSI bus devices coupled to the SCSI bus. The system also includes an external SCSI connector for coupling external SCSI devices to the SCSI bus. The access password is established and stored within the system. The plurality of internal SCSI bus devices and the external devices are prohibited from accessing the SCSI bus prior to a correct entry of the access password. The SCSI bus includes a busy signal line. Prior to a correct entry of the access password, the system asserts the busy signal line, indicating that the SCSI bus is busy. Both internal and external devices are prohibited from accessing the SCSI bus while the busy signal line is asserted.

Abstract: The invention relates to a security lock for devices connectable to a computer bus. The devices receives from the computer information as to the owner of the computer, and compares the information it receives from the bus to information regarding the legitimate owner, which is permanently stored in the device. When the information received from the bus is different from the information stored in the device, the operation of the device is restricted. The invention prevents use of a device on a computer other than the one of the legitimate owner. It discourages theft of the device.

Abstract: A computer system provides a self-modifying synchronization memory address space and protocol for communication between multiple busmasters. In one computer system embodiment, the self-modifying synchronization memory address space is provided in a memory controller embedded in a peripheral device of the computer system such as a bridge that provides central, high speed access by a busmaster to the memory controller without accessing a host bus. The synchronization memory address space includes a set of semaphore memory cells mapped to shared critical resources in the computer system. The semaphore memory cell allows for exclusive access by a busmaster to a shared critical resource by switching itself from an idle state to a busy state responsive to a first read operation by a busmaster. In the busy state of the semaphore memory cell, a busy state is communicated to other busmasters which attempt to read the semaphore memory cell.

Abstract: A system and method for using a toggle command for setting and releasing a lock, i.e. a locktoggle. In an exemplary computer system, one or more processors are each coupled to a bus bridge through separate high speed connections, such as a pair of uni-directional address buses with respective source-synchronous clock lines and a bi-directional data bus with attendant source-synchronous clock lines. The locktoggle command is used to transmit both a lock request and an unlock request from a processor to a system coherency. point, e.g. the bus bridge. The system coherency point acknowledges when the lock has been established or released. While the lock is active, other processors are inhibited. from accessing at least the memory locations for which the lock was initiated. Locks are thus established at the system coherency point, which may advantageously allow for locking functionality in a non-shared bus system.

Abstract: A parallel processor system has a plurality of nodes interconnected by a network for communication under control of a network interface controller of each node. The network interface controller includes a message reception controller for receiving a message from another node and judging illustratively the status of message reception and the need to return an acknowledge message; an acknowledge generating unit for generating an acknowledge message transmission request based on predetermined information in the message and the reception status when the return of an acknowledge message is judged to be necessary; and a message transmission controller for receiving an acknowledge the message transmission request and generating and returning an acknowledge message correspondingly. At the receiving node, the network interface controller can return an acknowledge message without processor intervention.

Abstract: A computer system includes a pipelined communication link on which pipelined transactions are identified by a tag. A finite number of tags are available. The computer system detects where all the available tags have been assigned to outstanding transactions, no tags are free and the condition has persisted for a predetermined amount of time.

Abstract: In a multi-node system, a method and apparatus to implement a locked-bus transaction is described. In one embodiment, a bus agent initiates a locked-bus transaction and a node controller defers the transaction so that it will be initiated again at a later time. The node controller then sends the locked bus request to one or more other node controllers in the system, which prevent bus transaction at their respective busses. Once the requesting node controller receives confirmation that the other nodes are locked, it can allow the locked-bus transaction to proceed from the bus agent.

Abstract: The present invention comprises a smart retry system for agents in a computer system. The smart retry system of the present invention includes a master agent, a slave agent, an arbiter, and smart retry logic components, all adapted to be coupled to a bus. The bus permits agents coupled to the bus to communicate with the arbiter and other agents coupled to the PCI bus. The smart retry logic component of the present invention prevents a PCI master agent from accessing the bus for the purpose of attempting a retry transaction, until after the slave agent that issued the retry is ready.

Abstract: An apparatus and method for permitting bus locking in a computer system having a mixed architecture. The mixed architecture includes a first bus coupled to processors that may run applications using bus locking or cache line locking. The apparatus interfaces the first bus with a second bus that does not support bus locking. The apparatus when presented with a locked transaction effectively implements bus locking on the second bus.

Abstract: The present invention comprises a host bus clocked in a host clock domain, a secondary bus for receiving a reset command clocked in a secondary bus clock domain and a controller for dynamically delaying transactions on the host bus until the secondary bus is out of reset.

Abstract: An apparatus for and method of separating protocol header information from content data in an IEEE 1394-1995 serial bus network. A receiving node receives isochronous data packets from a transmitting node via a serial bus. Each packet can include a data portion in addition to protocol header information, although not every packet necessarily includes the data portion. Each incoming packet is loaded into a buffer in the receiver as the packet is being received. The protocol header information is removed and stored in sequence in a first block of memory. This is accomplished by placing an input_more direct memory access (DMA) instruction into a next instruction register and, then, executing the instruction. In addition, the receiver is conditioned for removing the data portion from the buffer by loading an input_last DMA instruction into the next instruction register.

Abstract: An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) to system memory, and direct memory access (DMA) to system memory transactions.

Abstract: Method and apparatus for locking by sharing lock states. Each resource is associated with a lock state that represents its lock. Lock states are made of one set of transactions per locking mode. Resources may share the same lock state if the state of their respective locks is equal. Locking operations change the association between a resource and a lock state to reflect changes to the resource's lock. In one embodiment, a table of immutable lock states (TILS) record the immutable lock states that were created by lock operations in order to avoid duplication of lock states with equal value. Locking operations (acquire and release) on a resource R by a transaction T compute a new lock state value by adding (acquire) or removing (release) T from the lock state associated with R, consult the TILS to retrieve an immutable lock state corresponding to the computed value (and registers one if none was found), and change R's association to refer to the lock state returned by the TILS.

Abstract: A bus arbitration system is described which includes an arbitrator for controlling accesses to a memory bus by a plurality of memory users in response to requests made by those memory users. Each memory user reads the address if a current access to memory and generates a same-address-set signal when the address of the last access by that memory user lies in the same set as the address of the current access. The arbitrator holds for each memory user a predetermined number of accesses which are permitted by that memory user during an access span, and, responsive to a request, grants up to that predetermined number of accesses provided that the same-address-set signal is asserted.

Abstract: A deadlock-avoidance system for a computer. In a multi-bus, multi-processor computer, one processor may request a lock on a bus, to execute a locked cycle, thereby blocking all other processors, and other agents, from access to the bus. In addition, a conflicting agent may, in effect, lock a resource which is needed by the processor to complete the cycle for which the lock was requested. These two locks can create a deadlock situation which stalls the computer: the processor and the conflicting agent have each locked a resource needed by the other. Under the invention, when a locked cycle is requested by a processor, all other operations are suspended in the computer. Then queues standing in memory controllers are emptied. If a process requested by an agent occupies a resource, such as a bridge, required by the requested locked cycle, that resource is freed. Then the locked cycle is executed.

Abstract: A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

Abstract: A method of providing a lock to a requester, the method including the steps of storing a lock indicator at a storage location on a storage medium; receiving a lock command from a requester on a host computer, wherein the lock command identifies the storage location on the storage medium and represents a lock request; in response to receiving the lock command, retrieving the lock indicator from the storage medium; performing an exclusive OR operation on the lock request and the retrieved lock indicator to produce a lock request result; and sending an indication back to the host computer indicating whether the lock request was granted.

Abstract: A unified memory system includes a processor, a memory controller, a plurality of bus transactor circuits and a shared memory port. A processor bus is coupled between the processor and the memory controller. A first multiple-bit, bidirectional system bus is coupled between the shared memory port, the memory controller and the plurality of bus transactor circuits. A second multiple-bit, bidirectional system bus is coupled between the memory controller and the plurality of bus transactor circuits.

Abstract: A circuit for controlling the data transmissions among two devices capable of transmitting information, via an output buffer, over a bus, so as to prevent bus contention, is comprised of a first device enabled circuit for generating a first device enabled signal indicative of whether one of the devices is enabled to transmit information. A second device enabled circuit generates a second device enabled signal indicative of whether the other of the devices is enabled to transmit information. A circuit, which is in communication with the first and second device enabled circuits, generates an output enable signal. The output enable signal is input to one of the devices to create a delay between the end of a transmission of information by one device and the beginning of a transmission by the other device.

Abstract: A transmitting device capable of transmitting video data with high speed has been disclosed. When transmitting video data, by providing a transmitting circuit for invalidating a time out signal of a timer which counts the occupied time of a bus, the video data having large volume of information can be successively transmitted by continuously using the bus, and thus the video data can be transmitted with high speed.

Abstract: A routing table comprises routing table entries [230], a word line driver [92], prioritizer [100], and memory [106]. Each routing table entry [230] comprises content addressable memory (CAM) cells [220] and an entry masking circuit. The routing table looks up in parallel an entry matching an input network address, and outputs the search result in deterministic time. Only the bits specified by the masking circuit in each entry are compared when searching. If multiple entries match the input, the prioritizer [100] uses mask information from the masking circuits of the matching entries to select the best entry, e.g. the entry having the most matching bits.

Abstract: Method and apparatus for locking by sharing lock states. Each resource or object has an associated lock state (that may be cached) comprised of transactions that own a lock in a specific mode for the resource. Several resources may share the same lock state. In one embodiment of the invention, a table of immutable lock states (TILS) is utilized to maintain the correct association of locked resources and immutable lock states. To acquire a lock, a new lock state is computed by adding the current transaction to the old lock state. If the new lock state is already in the TILS, the association between the resource and the lock state is updated to reflect the new lock state. If the new lock state is not in the TILS, the new lock state is added to the TILS. To release a lock, the transaction determines the new lock state that will result after removal from the lock state for that resource. The association between the resource and the lock state is then updated to reflect the change.

Abstract: A distributed computer system includes a host CPU, a network/host bridge, a network/I/O bridge and one or more I/O devices. The host CPU can generate a locked host transaction, which is wrapped in a packet and transmitted over a network to the remote I/O device for replay. The remote I/O devices can generate interrupts. The interrupt is wrapped in a packet and transmitted to the host computer for replay as an interrupt. The host CPU then executes the appropriate interrupt service routine to process the interrupt routine. The remote location of the I/O device with respect to the host CPU is transparent to the CPU and I/O devices. The bridges perform wrapping and unwrapping of host and I/O transactions for transmission across a network.

Abstract: A bus bridge which can prevent invalid data from being transferred from a secondary PCI bus to a primary PCI bus even when an SCSI controller or another device provided with a memory the content of which is cleared after a read, is connected to the secondary PCI bus. In a controller, a transaction is processed as a delayed transaction. A combination circuit generates a switching logic signal in accordance with a command or an address included in the transaction. In accordance with the memory content, a bus release controller restricts transmission by a transaction forward controller of a control signal for stopping the transaction issued on the primary PCI bus. Instead of restricting the transmission of the control signal, the time-out period of the buffer memory may be prolonged.