Abstract: Method and apparatus for coordinating access to a shared object amongst a plurality of processes in a distributed system. One process is identified as a lock owner process controlling a lock associated with the shared object. When a process needs to access the shared object, it requests control of the lock from the lock owner process. When no other process controls the lock, the lock owner process grants control to the requesting process. When another process controls the lock, the lock owner process places the requesting process in a queue and waits for the lock to become available. All accesses to the shared object are processed through the lock owner processes thus assuring coordination and synchronization among the processes.

Abstract: A computer system avoids livelock conditions on a computer bus coupled to plural bus masters. In response to receiving a transaction request from a first bus master across the computer bus, a bus controller transmits a retry command to the first bus master if the bus controller is unable to execute the transaction request. A livelock condition is avoided by preventing transaction requests from any of the bus masters, other than the first bus master, from being processed until after the first bus master re-submits the transaction request. The bus controller may prevent execution of the transaction request from the other bus masters by transmitting retry commands to all bus masters that submit transaction requests after the transaction request from the first bus master is received and before the first bus master re-submits the transaction request.

Abstract: The present invention comprises a method for blocking transactions on a host bus until a target agent is out of reset, comprising synchronizing a reset signal received by the host bus such that the reset signal is clocked in the clock domain of the target agent, determining whether the reset signal clocked in the target agent clock domain is deasserted and blocking transactions on the host bus until it is determined that the reset signal clocked in the target agent clock domain has been deasserted.

Abstract: A computer system includes a first device on a first data bus, a second device on a second data bus, and a bridge device that delivers data transactions between the two devices. The bridge device includes an execution queue that stores only a higher priority transaction and transactions initiated before the higher priority transaction, and a controller that selects transactions from the execution queue to be completed on one of the data buses.

Abstract: A system and method for controlling the flow of information between devices. A count is maintained representative of requests issued by a first device. The count is incremented for each packet issued by a first device and decremented for each packet received at the first device. A maximum buffer count, which corresponds to the capacity of the buffer is used to perform flow control by determining when the maximum buffer count is to be exceeded by the issuance of a packet by the first device. If the count is to be exceed, issuance of packets by the first device is prevented until the maximum buffer count will not be exceeded by issuance of the packet.

Abstract: A computer system incorporating an apparatus for allocating exclusive shared resource requests includes a shared resource, a first type device coupled to the shared resource and a second type device coupled to the shared resource. The computer system also includes an arbitrator unit coupled to the shared resource capable of granting the second type device exclusive access to the shared resource by preventing the first type device from being granted exclusive access to the shared resource. The arbitrator unit prevents the first type device from being granted exclusive access to the shared resource for at least a duration of time after the second type device has completed an associated second type shared resource transaction.

Abstract: A central processing unit (CPU) having a built-in dynamic random-access memory (DRAM) with exclusive access to the DRAM when the CPU performs an interlock access to the DRAM. A memory controller prevents the DRAM from being externally accessed while the CPU is performing the interlock access. When the memory controller receives an external request for accessing the DRAM during a time when the CPU is performing an interlock access to the DRAM, the memory controller outputs a response signal indicating that external access to the DRAM is excluded or inhibited. The request signal can be a hold request signal for requesting a bus right or can be a chip select signal. The response signal can be a hold acknowledge signal or a data complete signal. The memory controller can be switched to and from first and second lock modes, where hold request and hold acknowledge signals are used during the first lock mode and chip select and data complete signals are used in the second lock mode.

Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available.

Abstract: A shared resource lock mechanism is provided which enables processors in a mullet-processor environment which each share common resources to obtain locks on those resources using a read modify write type transaction which does not at any point in time require the locking of a bus or a memory which contains the lock records used to lock the particular resources.

Abstract: An arbiter uses a history based bus arbitration scheme to more fairly allocate a shared resource among multiple devices. The arbiter uses a history queue to dynamically update the priorities of the devices using the shared resource, and makes the grant decision in a single calculation using the combination of the history queue and requests from bidding devices. The priority for granting master to each device is dynamically modified so that the least recently serviced requestor will be granted the shared resource. A hidden arbitration scheme provides more fair history based resource allocation. A bus retry scheme demotes priority for processing devices that are assigned bus master but do not perform bus operations within a predetermined number of clock cycles. The arbiter also prevents bus grants during hot swap operations.

Abstract: A computing system that incorporates the invention includes a host processor which is coupled to a memory subsystem via a first bus system, a controller device and a second bus system. The controller device includes memory for storing plural Scripts for replay to the host processor, for instance, via the second bus system. A Script is an instruction set used to execute operations on a controller device. Each Script includes one or more addresses where either message or status data (or other operational data) can be found which is to be inserted, prior to dispatch of the Script. During operation of the computing system, the memory subsystem is caused, as a result of its operation, to issue an instruction to the controller device to dispatch a Script to, for instance, the host processor. The controller device responds by accessing the required Script, playing the Script which results in accesses to locally stored operational data for inclusion into the Script.

Abstract: A circuit for controlling the data transmissions among two devices capable transmitting information, via an output buffer, over a bus, so as to prevent bus contention, is comprised of a first device enabled circuit for generating a first device enabled signal indicative of whether one of the devices is enabled to transmit information. A second device enabled circuit generates a second device enabled signal indicative of whether the other of the devices is enabled to transmit information. A circuit, which is in communication with the first and second device enabled circuits, generates an output enable signal. The output enable signal is input to one of the devices to create a delay between the end of a transmission of information by one device and the beginning of a transmission by the other device.

Abstract: A multiprocessor system that assures forward progress of local processor requests for data by preventing other nodes from accessing the data until the processor request is satisfied. In one aspect of the invention, the local processor requests data through a remote cache interconnect. The remote cache interconnect tells the local processor to retry its request for data at a later time, so that the remote cache interconnect has sufficient time to obtain the data from the system interconnect. When the remote cache interconnect receives the data from the system interconnect, a hold flag is set. Any requests from other nodes for the data are rejected while the hold flag is set. When the local processor issues a retry request, the data is delivered to the processor and the hold flag is cleared. Other nodes may then obtain control of the data.

Abstract: A method for transferring data is performed by a first input/output device in order to perform a data transaction with a host device. The first input/output device receives a first data transaction request from the host device. The first input/output device stops the first data transaction. The first input/output device then requests a data second transaction with a second input/output device and asserts a request signal. The first input output device continuously asserts the request signal even when receiving a stop signal from the second input/output device. The first input/output device retries the second data transaction with the second input/output while continuously asserting the request signal. Upon completing the second data transaction with the second input/output device, the first input/output device releases the request signal. The first input/output device then completes the data transfer with the host device.

Abstract: A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

Abstract: In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.

Abstract: A shared resource lock mechanism is provided which enables processors in a multi-processor system which each share common resources to obtain locks on those resources using a transactions which minimizes the amount of time system resources are unavailable, while also allowing system resources to be available for other processing tasks.

Abstract: This is a method and system to lock and release modules on computing devices. The system may include: An automatic lock system for modules on a computing device, the system comprising: a processor connected to a system bus; an input means connected to the processor by the system bus; an output means connected to the processor by the system bus; and a module that inserts into the computing device and is connected to the system bus; a module controller that controls the module and is connected to the system bus; a latch that locks and releases the module to and from the computing device; and a subsystem that controls the latch. The system may also include a basic input/output system (BIOS).

Abstract: A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU with associated local memories, a dual-port RAM accessible from said CPUs, and a common bus switch circuit for connecting any one of said CPUs to a common bus shared by said CPUs.

Abstract: A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header.

Abstract: A data processing unit capable of solving a conventional problem in that a CPU cannot acquire the right of using a bus as long as a DMAC (Direct Memory Access Controller) has that right, and hence the operating ratio of the CPU reduces. A CPU bus is kept disconnected from the DMAC bus as long as the CPU disables the access request to a memory connected to the DMAC bus, and is connected to a DMAC bus in response to the access request unless the DMAC has the right of using a DMAC bus.

Abstract: A data processing system (10) and method is used to recover a CPU from faulty operation. A single timer (38) is used to enable recovery operations. When the timer (38) experiences a first time-out event, a software watchdog interrupt (28) is generated. If the software interrupt (28) is properly handled before another consecutive/subsequent watchdog time out occurs, normal software execution will resume. However, if the software watchdog interrupt is not processed and the watchdog timer (38) experiences a second time-out event while the watchdog time-out interrupt (28) is pending, the timer (38) will generate a bus transfer termination signal (30) and set a status bit (270) within a watchdog status register (44). This assertion of termination signal (30) and the setting of the bit (270) allows the microprocessor to determine that a locked bus state exists.

Abstract: A hardware authentication mechanism ensures that a device receiving a packet of copy-protected data has been authorized by the transmitting device to receive the packet of data. The transmitting device authenticates a receiving device and verifies that the receiving device is authorized to receive the copy-protected data. Once authenticated, the transmitting device then sends a write authentication transaction, including a physical identifier value representing the transmitting device, to the receiving device. This authentication transaction is preferably addressed to a predefined address in the receiving device. This address is preferably communicated from the receiving device to the source device during the earlier authentication process. Alternatively, the address is assigned by convention.

Abstract: A lockout system for preventing children from accessing parentally-restricted and undesirable material with a computer comprises a controller unit for receiving commands from a computer and generating control codes to a data device to transmit electronic information over a phone line. A locking device is operably coupled to the controller unit and has a LOCKED state and an UNLOCKED state. The controller unit is further operable for determining the state of said locking device and preventing the transmission of electronic information from said data device when the locking device is in a LOCKED state. Other embodiments utilize a locking device to disable a relay in-line with the telephone line of a modem or to interrupt the phone line directly.

Abstract: A method and apparatus to prevent data from being corrupted prior to reaching the final destination is provided. The method and apparatus monitors the status of posted write transactions and transaction initiations. If it is determined that a posted write transaction is incomplete and there is a pending transaction initiation, a bus retry is requested for the pending transaction.