Abstract: The present invention provides an apparatus and method that increases the utilization by processors on shared resources. It provides the minimum latency in a multiprocessor system during usage right exchange between multi-processors on a shared resource. The apparatus provides a timed mailbox including a timer. The timed mailbox is at least associated with a first processor and a second processor. The second processor starts to utilize a shared resource to perform a task. According to a predetermined clock cycle number, the timed mailbox issues a signal in advance to notify the first processor of the availability of the shared resource to be utilized by the first processor.

Abstract: In an information-processing apparatus including a plurality of modules and a first arbiter which arbitrates bus-access requests of the plurality of modules, at least one of the plurality of modules includes a plurality of submodules and a second arbiter which arbitrates bus-access requests of the plurality of submodules and transmits at least one of the bus-access requests of the plurality of submodules to the first arbiter. The first arbiter gives priority to the module which transmits many bus-access requests, or the module which made a previous bus access, and limits the number of consecutive accesses made by the same module, so as to control the priority of accessing the bus by the plurality of modules. The second arbiter controls priority of accessing the bus by the plurality of submodules according to the free state of a buffer of each submodule, or the access type, whereby the bus-access requests made by the plurality of modules can be arbitrated, thus increasing bus-use efficiency.

Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.

Abstract: An information processing apparatus configured to control communications of a plurality of devices via a common communication channel on the basis of predetermined priority levels of the devices includes a changing unit configured to change the priority level of a predetermined device, which is one of the plurality of devices, having a first priority level to a second priority level for a predetermined amount of time and a controlling unit configured to control the length of the predetermined amount of time.

Abstract: Requestors acquire tokens before issuing access requests to a memory controller. The access requests issued are accumulated in a command queue of the memory controller. When the amount of access requests accumulated in the command queue is smaller than or equal to a first threshold, or in level 0, tokens are generated at a rate equivalent to 200% of a bus bandwidth. If the amount of accumulation is greater than the first threshold and is smaller than or equal to a second threshold, i.e., in level 1, tokens are generated at a rate equivalent to the bus bandwidth. If the amount of accumulation exceeds the second threshold, the token generation is stopped.

Abstract: In an embodiment of the invention, an apparatus and method for detecting resource consumption and preventing workload starvation, are provided. The apparatus and method perform the acts including: receiving a query; determining if the query will be classified as a resource intense query, based on a number of passes by a cache call over a data blocks set during a time window, where the cache call is associated with the query; and if the query is classified as a resource intense query, then responding to prevent workload starvation.

Abstract: A system and method for implementing a control process within a process control system and resolving inconsistencies during execution of the control process includes loading the logical structure of the control process, loading a plurality of instantiation objects or processes when the control process is instantiated, using the instantiation objects to instantiate a procedural element of the control process as the control process calls for the procedural element during execution, executing the procedural element as part of the control process, and deconstructing the procedural element as execution of the procedural element is completed during execution of the control process. Resolution of inconsistencies includes executing a first model of an entity in a controller, executing a second model of the entity in an execution engine, detecting a difference between the models, generating a prompt and receiving an operation instruction to continue the process or abort the process.

Abstract: An arbiter in a communication system including a plurality of request shapers in communication with a plurality of requestors. Each request shaper is configured to receive a request for access to a resource of the communication system, initially assign a priority level to the request upon receipt of the request, increase an age of the request, after increasing the age of the request, compare the age of the request to a delta period value associated with the respective requestor, and repeatedly increase the priority level of the request based on the comparison. Each of the plurality of requestors has a corresponding delta period value that is different from that of other ones of the plurality of requestors. An arbiter core is configured to grant one of the plurality of requestors access to the resource based on the priority level of each request and the age of each request.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An apparatus for performing arbitration increases the fairness of arbitrations, decreases system latency, increases system throughput, and is suitable for use in more complex systems. According to an exemplary embodiment, the apparatus includes a generator for generating a plurality of arbitration numbers corresponding to a plurality of agents, and circuitry for selecting one of the agents to access a resource shared by the agents based on the arbitration numbers. At least one of the arbitration numbers includes a plurality of fields corresponding to a plurality of parameters.

Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.

Abstract: A wireless network device includes a first communication module to communicate with at least one of first devices and a second communication module to communicate with at least one of second devices. An arbitration module receives a request for communication from the first communication module, detects when the second communication module is communicating in a locked mode, and denies request for communication from the first communication module when the second communication module is communicating in the locked mode. Transmission or reception of a packet in the locked mode is not interrupted to avoid loss of the packet. The arbitration module grants the request for communication from the first communication module when the second communication module is communicating in the locked mode and when granting the request for communication from the first communication module does not require stopping the second communication module from communicating in the locked mode.

Abstract: Aspects of the subject matter described herein relate to detecting the ready state of a user interface element. In aspects, a synchronization object is created to indicate when a user interface element is ready. Data is then loaded into the user interface element. After the data is loaded, an indication is made via the synchronization object that the user interface element is ready. After this occurs, a thread waiting on the synchronization object may interact with the user interface element with confidence that the user interface element is ready.

Abstract: A semiconductor integrated circuit according to an aspect of the invention includes a plurality of master devices which issue data transfer requests, at least one slave device which performs data transfer in accordance with the data transfer requests, and a network which arbitrates the plurality of data transfer requests respectively issued from the plurality of master devices, and informs the slave device of the arbitration result, thereby performing data transfer between the master devices and the slave device, wherein when issuing the data transfer request, the master device informs the network of a period which extends from the issuance of the data transfer request to the start of the data transfer.

Abstract: An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal “CDSZ”) indicative of the size of data to be read or written. A state machine 155 grants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data. Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine 155 can set an optimal number of bus cycles.

Abstract: An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.

Abstract: For control unit access, a vehicle to be checked is identified using an identifier. Control and/or monitoring operations covered by the control unit access are selected. A communication link is set up over a selected vehicle communication interface. Communication devices covered by the selected vehicle communication interface are ascertained. Independent control and/or monitoring operations covered by the control unit access are ascertained, where these operations are associated with available communication means and are not dependent on a superordinate control and/or monitoring operation. A control and/or monitoring operation, which has the greatest number of subordinate dependent control and/or monitoring operations, is selected for execution.

Abstract: Loading and unloading a plurality of libraries on a computing device having a loader lock and internal and external counts for each library in the plurality of libraries is disclosed. The libraries assume an initialize state, followed by an initialized state, a pending unload state, and an unload state according to when the internal and external counts are incremented and decremented. When in the pending unload state, the functions of a library that include functions that require acquiring the loader lock exit, the internal count is decremented by one, and the loader lock is released. Prior to entering the pending unload state, a library may be placed into a reloadable state. A library in the reloadable state may be reloaded upon request until a timer times out. When the timer times out, the library in the reloadable state transitions into the pending unload state.

Abstract: Resource requests are allocated by storing resource requests in a queue slots in a queue. A token is associated with one of the queue slots. During an arbitration cycle, the queue slot with the token is given the priority to the resource. If the queue slot with the token does not include a request, a different queue slot having the highest static priority and including a request is given access to the resource. The token is advanced to a different queue slot after one or more arbitration cycles. Requests are assigned to the highest priority queue slot, to random or arbitrarily selected queue slots, or based on the source and/or type of the request. One or more queue slots may be received for specific sources or types of requests. Resources include processor access, bus access, cache or system memory interface access, and internal or external interface access.

Abstract: A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

Abstract: An access request arbitration section, a data amount management section and a resource control section are provided between a plurality of masters and a shared resource. The data amount management section manages access data amounts passing between the plurality of masters and the resource. The access request arbitration section executes arbitrary arbitration of issuing access permission to a master determined according to the access data amount at any timing, in addition to periodic arbitration of issuing access permission to any of the masters at fixed-interval arbitration timing. If an access request of less than a defined data amount is granted in periodic arbitration, the remaining access chance can be used in arbitrary arbitration.

Abstract: A method and a system of controlling access of data items to a shared resource, wherein the data items each is assigned to one of a plurality of priorities, and wherein, when a predetermined number of data items of a priority have been transmitted to the shared resource, that priority will be awaiting, i.e. no further data items are transmitted with that priority, until all lower, non-awaiting priorities have had one or more data items transmitted to the shared resource. In this manner, guarantees services may be obtained for all priorities.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An aspect of the present invention provides an arbiter which grants a request (to access a resource) in the same clock cycle as in which the requests from requesters is received. In one embodiment, such a feature may be provided in case of arbitration policies requiring state information from previous grants. In another embodiment, such a feature may be provided when the arbitration policy is programmable such that the same arbiter can be used for different arbitration policies.

Abstract: A command generating and monitoring system includes a command processor configured to determine a command data set from a command input. A monitoring processor is coupled to the command processor and is configured to generate an authentication key by comparing the command data set received from the command processor to a comparison command data set generated by the monitoring processor. A data bus is coupled to the command processor and the monitoring processor. The data bus is configured to receive the command data set and the authentication key for retrieval by a consuming device.

Abstract: A reader-writer lock is provided that scales to accommodate multiple readers without contention. The lock comprises a hierarchical C-SNZI (Conditioned Scalable Non-Zero Indicator) structure that scales with the number readers seeking simultaneous acquisition of the lock. All readers that have joined the C-SNZI structure share concurrent acquisition, and additional readers may continue to join until the structure is disabled. The lock may be disabled by a writer, at which time subsequent readers will wait (e.g., in a wait queue) until the lock is again available. The C-SNZI structure may be implemented in a lockword or in reader entries within a wait queue. If implemented in reader entries of a wait queue, the lockword may be omitted, and new readers arriving at the queue may be able join an existing reader entry even if the reader entry is not at the tail of the queue.

Abstract: According to an aspect of an embodiment, an apparatus has a pair of first system boards, each of the first system boards including a processor and being adapted for sending duplicate requests, in parallel, respectively, a second system board including a processor and being adapted for sending requests, a first transfer device for transferring requests, having a first arbiter for selecting and outputting one of the duplicate requests sent from each of the first system boards, and a second arbiter for selecting and outputting one of the requests sent from the second system board and a second transfer device for transferring requests, having a third arbiter for selecting one of the duplicate requests sent from each of the first system boards and outputting the selected request in synchronization with the selected request outputted by the first arbiter, the second transfer device having a forth arbiter.

Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.

Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.

Abstract: A network comprises a plurality of nodes; a plurality of bi-directional point-to-point communication links, wherein a priority-based arbitration scheme is used to communicate over each of the plurality of point-to-point links; and a hub that is communicatively coupled to each of the plurality of nodes via the plurality of point-to-point links; wherein when the hub determines that one or more of the nodes is transmitting a message via the hub, the hub selects which node's message should be forwarded to the other nodes based, at least in part, on the priority-based arbitration scheme and forwards the selected node's message to the other nodes with elevated priority.

Abstract: A method and an apparatus that synchronize an application state in a client with a data source in a backend system in an asynchronous manner are described. A response is sent to the client based on a priority determined according to a history of received update requests. When a notification message from a data source in a backend system is received, an update request is selected from a plurality of update requests currently pending to be served according to the priority associated with each update request. A response is sent to the client over a network corresponding to the selected update request. The response includes state updates according to the changes in the data source and the current application state in the corresponding client.

Abstract: Bus transfer efficiency is improved in bus communication that uses a shared memory, based on a communication origin master 101 selectively using an arbitration completion notification signal and a memory access completion notification signal. Based on the arbitration completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12. Based on the memory access completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12.

Abstract: A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence.

Abstract: An access control device controls an access right with respect to a plurality of electronic devices in a network for each combination of electronic devices. An authority information generating section generates authority information which is used when an electronic device accesses an application on an electronic device. A permission information generating section generates permission information which is information about whether or not the electronic device permits an access request from the electronic device, in relation with the authority information. An access information storing section stores the authority information and the permission information. A transmission control section transmits via the communication section the authority information to the electronic device and the permission information to the electronic device.

Abstract: A computer system associated with a plurality of interrupt sources that produce interrupt signals may include interrupt signal processing blocks corresponding to the interrupt sources, respectively. Each of the interrupt processing blocks can include: a counter for generating an interrupt count value associated with the number of interrupt signals received from the corresponding interrupt source; a first register for storing the interrupt count value; a logic circuit for to generate an interrupt request signal according to the interrupt count value; and a second register for storing a service routine address associated with the interrupt source.

Abstract: Methods and systems for a low-cost high density compute environment with increased fail-over support through resource sharing and resources chaining. In one embodiment, one of a number of servers qualified to share resources is elected as a resource server. The shared resource can be firmware memory, hard-drive, co-processor, etc. The elected server responds to requests from individual requesters and provides the responses, such as firmware images. In one embodiment, all the blade servers on a rack use an image server for their firmware image so that these blade servers can automatically adopt a common personality across the entire rack. If the elected image server fails, a dynamic process elects an alternate image server. In one embodiment, among a set of qualified servers, only one is actively elected at a given time.

Abstract: Disclosed is a content reception apparatus capable of receiving a content distributed from a server apparatus via a first network and a second network, the content reception apparatus including a plurality of content reception apparatuses capable of being connected to the second network that is local and connected to the first network, the server apparatus being capable of distributing a content and capable of being connected to the first network. The content reception apparatus includes an arbitration condition storage unit to store an arbitration condition for an arbitration, an arbitration table storage unit to store an arbitration table, an input unit with which a content reception request is input, an arbitration start request transmission unit to generate and transmit an arbitration start request, and an arbitration unit to execute arbitration processings.

Abstract: When four access request origins A, B, C, and D are present, a priority table (No. 1) having a priority order of A, B, C, and D, a priority table (No. 2) having a priority order of B, D, A, and C, a priority table (No. 3) having a priority order of C, A, D, and B, and a priority table (No. 4) having a priority order of D, C, B, and A are prepared. An order of employing these tables is determined in advance in this order. A priority table next in the order to the priority table employed in last arbitration or, when a priority table at the bottom in the order is employed in last arbitration, a priority table at the top in the order is employed. Based on the priority levels defined in the employed priority table, an access request to be accepted is selected.

Abstract: An arbitration circuit for granting access to a shared resource among requestors comprises N request shapers, where N is an integer greater than one. An input unit receives a request from a requestor. An age unit assigns an age to the request and increases the age of the request when the requestor is not granted access to the shared resource. A priority unit assigns a priority level to each of the requests and selectively increases the priority level of the request based on the age of the respective one of the requests and a delta period of the request. An arbiter core receives the requests from the N request shapers and selectively grants access to the shared resource to each of the requestors corresponding to the requests based on the priority level and age of the requests. The delta period of one of the N request shapers is different than the delta period of another of the N request shapers.

Abstract: Methods and systems for a low-cost high density compute environment with increased fail-over support through resource sharing and resources chaining. In one embodiment, one of a number of servers qualified to share resources is elected as a resource server. The shared resource can be firmware memory, hard-drive, co-processor, etc. The elected server responds to requests from individual requesters and provides the responses, such as firmware images. In one embodiment, all the blade servers on a rack use an image server for their firmware image so that these blade servers can automatically adopt a common personality across the entire rack. If the elected image server fails, a dynamic process elects an alternate image server. In one embodiment, among a set of qualified servers, only one is actively elected at a given time.

Abstract: The remaining time period until the deadline of transfer by a device connected to a bus is measured, the remaining data size to be transferred by the device is detected, and the priority level of the device is set based on the remaining time period and the remaining data size.

Abstract: Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Abstract: An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the device to the central logic unit and the second unidirectional, point-to-point communication link transfers data from the central logic unit to the device.

Abstract: A data processing apparatus and method are providing for arbitrating access to a shared resource. The data processing apparatus has a plurality of logic elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests by one or more of the logic elements for access to the shared resource to perform a priority determination operation to select one of the requests as a winning request. The arbitration circuitry applies an arbitration policy to associate priorities with each logic element, the arbitration policy comprising multiple priority groups, each priority group having a different priority and containing at least one of the logic elements. Within each priority group, the arbitration circuitry applies a priority ordering operation to attribute relative priorities to the logic elements within that priority group.

Abstract: When receiving a write message associated with data, an input/output controller issues a write-request message to a home processor node which holds the data in a memory. When receiving the write-request message, a memory controller in the processor node executes a consistency process on the basis of information, regarding the state of the data, stored in a directory, and sends a write-permission message to the input/output controller which has issued the write-request message. In response to the received write-permission message, the input/output controller in an input/output node issues an update message, serving as a write message, to the home processor node. In response to the received update message, the memory controller in the process node updates the data in the main memory. In the above process, when receiving a plurality of write messages from input/output devices, the input/output controller issues write-request messages irrespective of the progress of a preceding write message.

Abstract: The present invention provides an arbitration circuit capable of stable operation regardless of timings for read and write requests. A latch signal of a predetermined pulse width is generated in accordance with a read request signal or a write request signal and supplied to latches. Flip-flops or FFs respectively fetch therein write and read requests produced within the time of the latch signal. The latches respectively output the fetched requests as signals at the same timing. Thus, since the timings for the signals coincide with each other even when the write request and the read request are made at close intervals while the latch signal is being outputted from a latch controller, a write control signal or a read control signal can be stably outputted in accordance with the order of priority defined in advance by a delay unit.

Abstract: An arbiter circuit includes a priority coefficient calculating unit, a priority coefficient comparator an acceptance determining unit, and a priority determining unit. The priority coefficient calculating unit calculates for each request an arbitration priority coefficient based on a priority level set for each request by requesters. The priority coefficient comparator compares arbitration priority coefficients calculated for the requesters by the priority coefficient calculating unit. The acceptance determining unit determines whether to accept the requests based on the comparison result by the priority coefficient comparator. When the arbitration priority coefficient calculated by the priority coefficient calculating unit is equal between two or more requests, the priority determining unit determines a priority order for accepting the requests.

Abstract: An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving module that receives multiple asynchronous requests for providing a final output. The request resolving module includes one or more arbiter stages cascaded with each other and operatively coupled with logic units.

Abstract: A method and apparatus for dynamically arbitrating, in hardware, requests for a resource shared among multiple clients. Multiple data streams or service requests require access to a shared resource, such as memory, communication bandwidth, etc. A hardware arbiter monitors the streams' traffic levels and determines when one or more of their arbitration weights should be adjusted. When a queue used by one of the streams is filled to a threshold level, the hardware reacts by quickly and dynamically modifying that queue's arbitration weight. Therefore, as the queue is filled or emptied to different thresholds, the queue's arbitration weight rapidly changes to accommodate the corresponding client's temporal behavior. The arbiter may also consider other factors, such as the client's type of traffic, a desired quality of service, available credits, available descriptors, etc.

Abstract: A mechanism for priority control in resource allocation for low request rate, latency-sensitive units is provided. With this mechanism, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.