Abstract: A circuit for selecting one of N requestors in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the requestors is selected next. The first addend is an N-bit vector where each bit is false if the corresponding requester is requesting access to a shared resource. The second addend is a 1-hot vector indicating the last selected requester. A multithreading microprocessor dispatch scheduler employs the circuit for N concurrent threads each thread having one of P priorities. The dispatch scheduler generates P N-bit 1-hot round-robin bit vectors, and each thread's priority is used to select the appropriate round-robin bit from P vectors for combination with the thread's priority and an issuable bit to create a dispatch level used to select a thread for instruction dispatching.

Abstract: An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.

Abstract: An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.

Abstract: In one embodiment, the present invention includes a bus controller including a mutual exclusion unit to receive a data transmission request from first and second agents and to select one of the agents for servicing based on which agent is the first to send the request, multiple selection units controlled by the mutual exclusion unit, and a two-phase register coupled to at least one of the selection units to transmit data from the selected agent. Other embodiments are described and claimed.

Abstract: A dynamic arbitration controller includes components for reading current state information as well as records of known arbitration states which may cause a deadlock condition, comparing the current state to the records of known arbitration states and resolving deadlock conditions during arbitration. The dynamic arbitration controller may include circuits for storing and retrieving information related to the arbitration. The dynamic arbitration controller may be implemented as a circuit design or as a computer program product stored on machine readable media.

Abstract: An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.

Abstract: According to an aspect of the invention, there is provided a data transfer control device that carries out data transfer in a data transfer system, in which plural bus masters are connected to a system bus and the data transfer between the bus masters is arbitrated by bus arbitration of each of the bus masters, between the bus masters, the data transfer control device including: an execution cycle monitoring section that monitors an access state for the system bus at the bus master when plural bus masters simultaneously request a use right with respect to the system bus; and a function execution order changing control section that changes an execution order of plural functions included in the bus master to be monitored, based on the access state monitored by the execution cycle monitoring section.

Abstract: A request from a first processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the first processor at a first clock frequency. A request from a second processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the second processor at a second clock frequency that is lower than the first clock frequency.

Abstract: An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal “CDSZ”) indicative of the size of data to be read or written. A state machine 155 grants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine 155 can set an optimal number of bus cycles.

Abstract: Methods and apparatus provide for: assigning each of a plurality of requesters to a respective one of a plurality of requester groups; receiving tokens from a plurality of resources, where each token is an exchange medium for permitting one of the requesters having the token to access an associated one of the resources for a period of time; receiving requests for the tokens from one or more of the requesters; allocating the tokens to at least one of the respective requester groups and the requesters thereof based on token allocation criteria; and dynamically re-assigning one or more of the requesters among the requester groups based on feedback information concerning at least some prior token allocations.

Abstract: The method and system for data transfer between the master device and the slave device through the bus are presented.

Abstract: A bus arbitration method for arbitrating a bus in a computer capable of executing a plurality of tasks by a plurality of devices connected to the bus is provided and includes: acquiring a task information at a timing, the information containing a priority of each of the tasks and a usage rate of each of the devices for executing each of the tasks; producing an information of a bus use condition of each of the devices on the basis of the priority and the usage rate so that that the bus is preferentially assigned to a device necessary to execute a task having high priority; and arbitrating the bus between the devices according to the information of the bus use condition.

Abstract: An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving module that receives multiple asynchronous requests for providing a final output. The request resolving module includes one or more arbiter stages cascaded with each other and operatively coupled with logic units.

Abstract: Collisions are resolved in a database replication system. The system includes a plurality of nodes arranged in either a master-slave or network configuration. Each node includes a database, wherein changes made at the databases of each node are replicated to the databases at one or more of the other nodes. When a collision is detected during data replication between multiple nodes, the collision is resolved by a rule that gives precedence to certain nodes over other nodes.

Abstract: A system includes at least one memory and at least one processor. The at least one memory is operable to store a resource object associated with a resource. The at least one memory is also operable to store a plurality of requester objects associated with at least a portion of one or more processes. The one or more processes are associated with production of one or more products using the resource. The at least one processor is operable to arbitrate between multiple arbitration requests from multiple ones of the requester objects. Each arbitration request indicates that one of the requester objects is attempting to acquire the resource object so that the associated resource is used to produce one of the products. The at least one processor is operable to use one or more user-defined strategies to arbitrate between the multiple arbitration requests.

Abstract: A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Abstract: A PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the PCI bus. An arbiter state machine is coupled to the phase table and looks at the port assignment for the next plurality of phases, for example, 3 phases. If the arbiter determines that the next plurality of phases is assigned to a single port, that port is selected as the next bus master.

Abstract: In the method for controlling access of a plurality of requestors to a shared memory, the following steps are repeated for successive time-windows: receiving access requests from various requestors (S1), determining a type of access requested by the requests, comparing the requested access type with an access type authorized for a respective time-window according to a back-end schedule, generating a first selection of the incoming requests which have the prescribed access type for the relevant time-window, dynamically selecting one of the requests from the first selection.

Abstract: The present invention provides an arbitration circuit capable of stable operation regardless of timings for read and write requests. A latch signal of a predetermined pulse width is generated in accordance with a read request signal or a write request signal and supplied to latches. Flip-flops or FFs respectively fetch therein write and read requests produced within the time of the latch signal. The latches respectively output the fetched requests as signals at the same timing. Thus, since the timings for the signals coincide with each other even when the write request and the read request are made at close intervals while the latch signal is being outputted from a latch controller, a write control signal or a read control signal can be stably outputted in accordance with the order of priority defined in advance by a delay unit.

Abstract: This invention provide a data processor capable of multiplexing data transfers with desired data transfer characteristics guaranteed, without multiplexing buses. The data processor includes: a transfer path that mutually connects plural processors and plural transfer element circuits such as memory; an arbitration circuit that controls data transfer in the transfer path; and a control register that defines the priority and minimum guaranteed bandwidth of data transfer. The arbitration circuit decomposes data packets sent from plural data transfer sources into subunits, and reconstructs plural data packets having the same data transfer target, based on priority and minimum guaranteed bandwidth stored in a control register. Thereby, the one reconstructed data packet can include subunits of plural data packets from transfer sources having different priorities, and data amounts of subunits contained in it can satisfy minimum guaranteed bandwidth of data transfer.

Abstract: Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The multiple primary components send requests to bus arbitration logic. The bus arbitration logic uses a request vector and an arbitration vector to determine a grant vector. The grant vector indicates what primary component should be allowed bus access.

Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.

Abstract: An arbitration device is provided, which is designed to be connected between, on the one hand, a first and a second module and, on the other hand, storing means forming a memory workspace. This arbitration device includes a detector for detecting one or more requests coming, concurrently or not, from the first and second modules, for the purpose of accessing the memory workspace.

Abstract: An electronic system comprises a defined number N of functional modules, including a defined number P of initiator modules and a defined number Q of target modules, where N, P and Q are integer numbers such that 2?P?N and 1?Q?N. In the event of a plurality of conflicting requests to access a common resource originating from a plurality of respective initiator modules, an arbitration unit grants an exclusive right of access to the resource to a defined one of these initiator modules. The arbitration unit is constructed either to apply a standard arbitration mechanism to these respective initiators, or to apply as a priority a specific arbitration mechanism only to the members of a subset of these initiator modules, for each of which it receives a linked privileged access signal.

Abstract: An arbiter circuit (100) can include a latch circuit (102) that latches competing input signals (MATCH1 and MATCH2) to generate signals on latch output (110-0 and 110-1). A filter section (104) can prevent metastable states of latch output signals from propagating through to output signals (BUSY2 and BUSY1). In addition, filter section (104) can generate output signals (BUSY2 and BUSY1) having one set of values when both inputs are inactive, and a second set of values when latch (102) is in the metastable state.

Abstract: A storage system is disclosed for performing control to match data among cache memories corresponding to shared volumes when multiple disk controllers containing cache memories are accessing shared volumes formed in the storage device. The storage system contains a switch for switching and connecting the multiple disk controllers containing cache memories, with a disk array containing the shared volumes capable of being commonly accessed from the multiple disk controllers. The switch performs exclusive access control of the multiple disk controllers' writing on the shared volumes, and performs control to match data other than modified data among the cache memories.

Abstract: A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus.

Abstract: A system and method is provided for delaying a priority boost of an execution thread. When a thread prepares to enter a critical section of code, such as when the thread utilizes a shared system resource, a user mode accessible data area is updated indicating that the thread is in a critical section and, if the kernel receives a preemption event, the priority boost that the thread should receive. If the kernel receives a preemption event before the thread finishes the critical section, the kernel applies the priority boost on behalf of the thread. Often, the thread will finish the critical section without having to have its priority actually boosted. If the thread does receive an actual priority boost then, after the critical section is finished, the kernel resets the thread's priority to a normal level.

Abstract: A method for controlling access to content by an Acquisition Point to Presentation Points in clusters in a domain. The AP receives from a PP an access content request comprising the PPs cluster identity and the PP's priority. The AP verifies if access is granted to a PP in the cluster and, if so, grants access to the requesting PP. If not, the AP verifies (603) if access is granted to PPs in a maximum number of clusters. If not, the AP grants access. If the maximum is reached, the AP verifies if the requesting PP's priority is higher than the priority of every PP in another cluster. If not, access is denied; if so, the AP grants access to the requesting PP and denies access to the PPs in the cluster with the lowest priority values. An Acquisition Point is also claimed.

Abstract: An adaptive weighted arbitration algorithm that is user configurable is discussed. The arbitration logic and algorithm considers past arbitration history events and is dynamic to allow for losing bidders to increase their probability of being selected to access the resource based on an accumulator value and a weight value.

Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Abstract: In an arbitration device, the entire transfer efficiency is improved without increasing the operating frequency and the number of pins. An overflow monitor mechanism generates an alarm once detecting a danger of occurrence of an overflow in an internal buffer group. An arbiter dynamically changes the priority order of arbitration once receiving the alarm from the overflow monitor mechanism and gives priority to processing of a request from a buffer having a danger of occurrence of an overflow.

Abstract: Data bus system and method are provided for controlling service engagements for bus users. At least one bus user provides services and other bus users use these services. A resource manager stores information about the available services and information about the service-providing bus users. The resource manager reserves a service from a providing bus user if the service can be used, and sends a response to a requesting bus user, allowing the requesting bus user to use the service from the providing bus user via the data bus. Information about the provided services is provided on the data bus via a standard interface by the bus users and a change in the provision of a service by a bus user is made available to the resource manager via the standard interface. The resource manager controls the service engagement on the basis of a priority information item.

Abstract: A method and computer system for accessing initialization data stored in a boot memory space. After the power supply starts up, the south bridge starts up and sends an initiating signal to the north bridge for starting up the north bridge. Once the north bridge has started up, it sends the south bridge a transaction which requests that the south bridge reads the initialization data from the memory space and sends the initialization data to the south bridge. Then, the CPU starts up and operates normally after the CPU receives an initiating signal and the initialization data sent by the north bridge.

Abstract: A request from a first processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the first processor at a first clock frequency. A request from a second processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the second processor at a second clock frequency that is lower than the first clock frequency.

Abstract: An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of the functional blocks via high level primitives. Each agent generates in response a critical rank vector comprising at least first and second components. An arbitrator receives the critical rank vectors generated by rival the agents and applies a maximum or minimum extracting mechanism to at least one of the two components of the critical rank vectors to uniquely identify the block accessing the resource. Thus, functional blocks can be separated from arbitration control, the agents implementing the arbitration control and being solely responsible for it.

Abstract: An arbitration diagnostic circuit and method provide diagnostic information in arbitration-based systems and/or provide detection of and response to excessive arbitration delays. For example, in one embodiment, an arbitration diagnostic circuit maintains a chronological memory trace of arbitration events, including resource request events and corresponding resource grant events for two or more entities having arbitrated access to a shared resource. The trace, which may be regarded as a running, ordered list, may comprise time-stamped event identifiers, which aid the analysis of arbitration related errors or failures. Indeed, in one or more embodiments, an arbitration diagnostic circuit is configured to track elapsed times for resource requests, and to detect resource grant delay violations.

Abstract: A task management system that inherit priority and that can reduce the queue operation required for transition to/return from a mutual exclusion awaiting state The task management system can execute a task without considering its priority, start or stop a server task and inherit priority without operating the dispatch queue. The task management system includes activity retaining information, context retaining information, and a dispatch queue used to select the highest priority task. Information on a task is divided and managed by the activity and the context, where each activity is inserted into/deleted from the dispatch queue. When the priority of a task is inherited by another task, only the correspondence between activity and context is changed.

Abstract: Various methods and apparatuses are described in which an interconnect couples to a plurality of initiator network resources and a plurality of target network resources. The interconnect may include a first stage of circuitry, a second stage of circuitry, and an arbitration controller. The first stage of circuitry receives incoming transactions from the plurality of initiator network resources. The second stage of circuitry passes outgoing transactions to the plurality of target network resources connecting to the interconnect. The arbitration controller arbitrates transactions from the plurality of initiator network resources destined to one or more of the target network resources. The target network resources supply their availability to service a transaction to the arbitration controller.

Abstract: A method, system and computer program product for creating and dynamically selecting an arbiter design within a data processing system on the basis of command history is disclosed. The method includes selecting a first arbiter for current use in arbitrating between requestors for a resource. During operation of said data processing system, an arbiter selection unit detects requests for the resource and selects a second arbiter in response to the detected requests for the resource.

Abstract: A method for designing an integrated circuit where the integrated circuit includes a plurality of modules and where each module includes an initiator port and a target port coupled to a distributed routing network. The initiator port is implemented by configuring whether the initiator or the distributed routing network is responsible for ordering responses to requests issued by the initiator port and defining the maximum number of requests that are permitted to be outstanding at the same time. The initiator port is further configured to define whether a delay stage is required in said initiator port. The distributed routing network is defined by the number of routing resources between the initiator and the target, an arbitration method for arbitrating between requests and an association between the routing resources and the targets.

Abstract: A system and method for managing access to a shared resource employs mutually exclusive flags. The flags enable arbitration between all applications requesting the use of the shared resource and ensure that each application has exclusive and continuous use of the shared resource. The preferred embodiment uses hardware to realize the flags and the flag arbitrating means. In one embodiment, the applications control and observe the flags through read/write registers. Alternative embodiments provide a unique read/write register for each application using the shared resource.

Abstract: Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.

Abstract: In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the occupancy level of data in the receiving buffer and the vacancy level of data in the transmitting buffer are determined. Access to the system bus is granted based on the determination result. Buffers in the transmitting and receiving paths are treated as a single virtual transmitting buffer and a single virtual receiving buffer, respectively. Bus priority is determined by the data occupancy level in each virtual buffer and any change in the occupancy level. Therefore, it is possible to prevent or reduce underflow of the transmitting buffer and overflow of the receiving buffer, thereby impartially arbitrating which of the buffers can access the memory.

Abstract: A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight to each of the processors in a second tier. The bus arbiter may sequentially grant bus access to the one or more processors during an initial portion of a bus interval based on the assigned second tier weights, and grant bus access to any one of the processors during the initial portion of the bus interval in response to a request from said any one of the processors having a first tier weight. When multiple processors are requesting access to the bus, the bus arbiter may grant bus access to the requesting processor with the highest weight in the highest tier.

Abstract: A system-on-chip (SoC) integrated circuit (IC) has reduced bus contention and improved bus utilization. The SoC IC includes a bus controller. Masters interconnected with the bus controller issue requests for data and receive requested data in response to the requests. Slaves interconnected with the bus controller receive the requests for data and provide the requested data to the requesting masters. Control signals issued by the bus controller indicate to each slave which masters are not ready to receive the data it requested from that slave. The slaves delay transferring data to any masters that are not ready for the requested data, and provide data to different masters that are ready to receive the data they requested from the slaves.

Abstract: A single chip, embedded symmetric multiprocessor (ESMP) having parallel multiprocessing architecture composed of identical processors includes a single program memory. Program access arbitration logic supplies an instruction to a single requesting central processing unit at a time. Shared memory access arbitration logic can supply data from separate simultaneously accessible memory banks or arbitrate among central processing units for access. The system may simulate an atomic read/modify/write instruction by prohibiting access to the one address by another central processing unit for a predetermined number of memory cycles following a read access to one of a predetermined set of addresses in said shared memory.

Abstract: A dynamic priority scheme is provided that uses information including the status of the target and data availability in deciding which PCI master should be assigned ownership of the bus. The target uses delayed transactions to complete a read access targeted to it. The target also integrates a buffer management scheme, in one embodiment an input/output cache, for buffer management. The present invention optimizes the performance and utilization of the PCI bus.

Abstract: A bus controller is provided including a processing means for performing processings of levels having cycle numbers which are different dependent on requesters which respectively issue an access request to a common memory. When it is expected from the present cycle number that a limit cycle number is exceeded, the bus controller selects a processing level with which the processing is performed with a smaller cycle number, or performs a control of giving no permission to a non-realtime bus access request. Thereby, it is possible to design a system with a cycle number that is smaller than the total sum of the maximum access cycle numbers multiplied by the maximum access times over all requesters.