Abstract: A polling-based communication apparatus and system. The apparatus of the invention, connected to a host computer through a peripheral bus, comprises an arbiter and multiple addressable entities. Each addressable entity corresponds to one of queues maintained in the host computer. The arbiter can determine which queue is to be served next in accordance with a quality of serve policy. The host computer polls each addressable entity by issuing a query packet. Depending on the queue chosen to be served next, the arbiter grants the corresponding addressable entity access to the peripheral bus, causing this granted addressable entity to respond to the host computer's polling with an acknowledgement packet. Thus the host computer initiates transactions to transfer data packets from the chosen queue through the peripheral bus to the corresponding addressable entity.

Abstract: An arbiter circuit (100) can include a latch (106) that latches competing input signals (Req_A and Req_B) to generate latch output signals (latn1 and latn2). A filter section (108) can prevent metastable states of latch output signals (latn1 and latn2) from propagating through to output signals (Sel_A and Sel_B). If both input signals (Req_A and Req_B) are activated, a feedback circuit (110) can activate a feedback signal (fb) after a predetermined delay (?), provided both output signals (Sel_A and Sel_B) remain inactive.

Abstract: In a first aspect, a first method is provided for allocating memory bandwidth. The first method includes the steps of (1) assigning a fixed priority of access to the memory bandwidth to one or more direct memory access (DMA) machines; and (2) assigning a programmable priority of access to the memory bandwidth to a processing unit. The programmable priority of the processing unit allows priority allocation between the one or more DMA machines and the processing unit to be adjusted dynamically. Numerous other aspects are provided.

Abstract: Power is conserved in a data processing system that includes a processor core and system circuitry coupled to the processor core. A first method for conserving power includes entering a low power state by the processor and the system circuitry and enabling bus arbitration by the processor while the processor core remains in the low power state. One embodiment further contemplates a method of conserving power by granting bus access to a requesting device and entering a power conservation mode by the processor core in response thereto. Bus operations are then performed while the processor core remains in the power conservation mode. Another embodiment contemplates a method of debugging a data processing system in which a debug state is entered by the processor and the system circuitry and, thereafter, bus arbitration is enabled by the processor while the processor core remains in the debug state.

Abstract: An edge detecting circuit detects an input level change (edge) of a synchronous signal provided from a synchronous signal input terminal. A data latch unit latches digital data provided from an external data input terminal. An address generating circuit provides an address signal. A write control unit activates/deactivates a write enable signal for writing to a RAM. An arbitration circuit monitors a write control enable signal, a read enable signal and a write enable signal, and detects a cycle, in which a CPU does not access the RAM.

Abstract: A method and apparatus of deprioritizing a high priority client. An isochronous data stream request is generally referred to as a “high priority” client. These high priority requests are sensitive to time, such that a certain amount of data must be retrieved within a certain amount of time. The fetching of this data will cause increased latencies on lower priority clients making requests for data. A method and apparatus for deprioritizing a high priority client is needed to improve the efficiency in handling data traffic requests from both high priority and lower priority clients.

Abstract: An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.

Abstract: A statistic method for arbitration is provided, implementing in an arbitration system comprising a bus, a main controller connected to the bus, and a plurality of peripheral devices able to be accessed by the main controller through the bus. The statistic method for arbitration is in response to various conditions where a bus is shared by peripheral devices, characterized in that a host at arbitration dynamically modulates the peripheral devices' access through the bus by utilizing an attenuation function to perform operation on a preceding cycle and a statistic value representing the use of the bus by the peripheral devices in response to the peripheral devices' access through the bus.

Abstract: In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. A machine check abort (MCA) handling mechanism is disclosed, which works with the semaphore control mechanism in the multiprocessor to provide improved system availability and reliability. The MCA handling mechanism provides for synchronization of multiple processors and shared resources and for timely execution resumption within the processors that remain on-line.

Abstract: A two-stage arbiter system comprises a first-stage arbiter to grant a request to one of a plurality of requestors in accordance with a first arbitration scheme and a second-stage arbiter to grant one of the remaining requests in accordance with a second arbitration scheme. The first arbitration scheme may be a fast arbitration scheme such as a fixed-priority scheme, and the second arbitration scheme may be a rotating priority-based arbitration scheme or a least-recently-granted arbitration scheme. The first-stage arbiter may operate in a first pipelined stage, and the second-stage arbiter may operate in a second pipelined stage. Two-stage arbitration may help improve access of lower-priority requestors in a pipelined system. In one embodiment, a rotating-priority arbitrator includes a pseudo-random number generator to generate an amount for rotating priorities prior to arbitration. The rotating-priority arbiter may use either a counter or linear-feedback shift register to rotate priorities of requests.

Abstract: In a system having a plurality of bus masters, system and method for enhancing data bus utilization are disclosed. This system comprises: a data bus connected to a peripheral apparatus and composed of a plurality of unit data buses each capable of carrying out data transfer independently; a plurality of bus masters each for sending a request signal requesting a use of the data bus in unit data buses, and using the data bus in unit data buses requested when a request by means of the request signal is granted; and a bus controller for giving a grant signal which grants the use of the data bus in unit data buses requested in unit data buses to the bus masters in accordance with an availability of the data bus in unit data buses, thereby split-controlling the data bus in unit data buses for the plurality of bus masters.

Abstract: A bus arbitration system employs counters respectively provided for an encoding section and an decoding section that are started when there is a request signal from the respective encoding section and decoding section. The counter values are outputted to respective comparators that compare the counter values with predetermined values and the results of the comparisons are fed to an arbitration controller. The arbitration controller in turn determines priority rankings for the encoding section and the decoding section based on the signals inputted from the comparators and outputs an acknowledgement signal to the module that has the highest priority.

Abstract: A processor is connected to a configurable system interconnect (CSI) bus. A CSL is connected to the CSI bus. The CSL comprises a first set of signal lines to send a data transfer request and a second set of signal lines to receive a grant associated with the data transfer request. A bus master unit (BMU) is coupled with the CSL through the first set of signal lines and the second set of signal lines. The BMU is connected to the CSI bus. The BMU arbitrates to take control of the CSI bus on behalf of the CSL enabling the CSL to perform data transfer to or from the CSI bus bypassing the processor.

Abstract: A method for accessing a device, such as a memory device and an interface device, by a processor is disclosed. The method involves the processor requesting access permission for the transfer of data. The bridge device grants access permission. The processor in response to the granting of access permission indicates that the processor is busy with the access. The processor also generates address and control signals for the access. The bridge device indicates that data is ready for transfer. A processing system including the processor and the bridge device is also disclosed.

Abstract: A resource allocation arbitration system. The system includes a plurality of storage devices, a plurality of indicators, and a plurality of mask bits. Each storage device stores requests for resources. Each indicator enables indication of a condition in which the request stored in each storage device is almost empty. Furthermore, the mask bits enable preemption of one request by another request.

Abstract: A method for arbitrating a bus grant among a plurality of master devices for access to a shared bus is disclosed. The method includes the steps of starting to accumulatively count time in response to a data transfer request signal outputted by one of the master devices for requesting a data transfer, and re-estimating a bus-utility condition for the one of the master devices to access to the shared bus when a preset threshold value of time is counted up. In addition, an arbiter for a bus grant among a plurality of master devices for access to a shared bus is disclosed. The arbiter is characterized by including a plurality of timer devices in communication with the plurality of master devices, respectively.

Abstract: A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.

Abstract: A method and apparatus are provided in a computing environment for scheduling access to a resource. The method grants access to the resource by a non-real-time request when the non-real-time request can be completed before the latest possible start time at which a first real-time request must start service to timely complete all actual and anticipated real-time requests, otherwise granting the first real real-time request access to the resource.

Abstract: An observation paradigm that works with a collection of the abovementioned elements, to provide a way of observing information infrastructures and data movement in a chosen time frame. The user (human observer) is provided sophisticated controls and interaction mechanisms that will make it easier for them to detect computer network intrusion and critical security management events in real time as well as allow them to better analyze past events. Embodiments may include various combinations of a framework for “intelligent agents”; an event handling system and a high-performance multi-layer observation facility presenting the user with a semantically dense depiction of an information source under consideration, such as a computer network.

Abstract: Various approaches grant access to a shared resource. An arbitration circuit includes request shapers that each receive a request from one of the requestors and assign a respective predetermined priority level and age to each of the requests. An arbiter core receives the requests and grants access to the shared resource to each of the requestors corresponding to the requests. The arbiter core includes a mask circuit that includes a plurality of mask registers each corresponding to a respective one of the priority levels. The age of a respective one of the requests increases when the corresponding one of the requestors is not granted access to the shared resource. The priority level of a respective one of the requests increases according to the age of the respective one of the requests.

Abstract: An arbitration circuit and a data processing system which ensure fair bus access are provided. An arbitration circuit (1) has a priority check block (21) and a round robin block (22). The priority check block (21) checks pieces of priority information provided from processors, specifies a processor that is presenting priority information with the highest priority, i.e. a processor with the highest priority level, and outputs the result of the check (CHK) to the round robin block (22). The round robin block (22), holding the results of the previous arbitration process, generates and outputs a processor selecting signal (SE) on the basis of the priority check result (CHK) and a round robin order generated from the previous results.

Abstract: A bus system and a method of deciding a data transmission path are provided. The bus system includes a plurality of functional blocks; a ring bus which transmits data in a single direction; an arbiter which generates a bus grant signal according to a predetermined algorithm in response to a bus request from one of the functional blocks; and a plurality of bus connectors each of which connects a corresponding functional block to the ring bus, transmits data from the corresponding functional block to the ring bus, and transmits data from the ring bus to the corresponding functional block. The method includes synthesizing and laying out a bus system, simulating a case where a short-cut bus is used when data is transmitted between functional blocks and a case where the short-cut bus is not used, and generating a bus selection table, to be referred to for selection of a bus, based on the simulation results.

Abstract: Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.

Abstract: A resource management device of the present invention, used in a system where at least one bus master is connected to each of a plurality of buses, includes: a bus arbitration section for arbitrating an amount of access to be made from the buses to a shared resource; an arbitration information management section for managing, as bus arbitration information, a bus priority order and a highest access priority pattern for ensuring a predetermined access bandwidth to the shared resource for each bus for an arbitration operation by the bus arbitration section; and a resource control section for controlling, based on characteristics of the shared resource, an access to the shared resource from the bus whose access request has been granted by the bus arbitration section. Thus, it is possible to guarantee a minimum bandwidth for access to the shared resource for each of the plurality of bus masters.

Abstract: A method to control a network device in a network comprising several devices includes a first controller that operates to prevent another controller from performing an unwanted overtaking of a network device that is currently controlled by the first controller. In one embodiment, the first controller has the ability to reserve a controllable network device to thereby become its primary controller, so that the first controller may maintain control over the controllable network device against control demands of other controllers present in the network.

Abstract: An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for transferring data, the second agent having priority over the first agent for access to the interface. A pre-emptive arbiter provides arbitration between the first agent and the second agent when at least one of a first transfer request signal is asserted by the first agent for requesting access to the interface by the first agent and a second transfer request signal is asserted by the second agent for requesting access to the interface by the second agent. The pre-emptive arbiter is capable of synthesizing a transfer completion signal on the interface for preempting access of the first agent to the interface so that access may be granted to the second agent.

Abstract: A system for selecting bus mastership in a multi-master system includes master devices and at least one slave device. The master devices generate control signals relating to bus mastership in the multi-master system. The slave device(s) receive the control signals from the master devices, determine whether a conflict exists based on the control signals, generate one or more alternate control signals for selecting bus mastership when a conflict is determined to exist, and select bus mastership using the one or more alternate control signals.

Abstract: A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the memory subsystem and the at least one microprocessor. At least one arbitration port is coupled to the memory controller and configured to receive an external arbitration signal.

Abstract: A microprocessor prioritizes cache line fill requests according to request type rather than issuing the requests in program order. In one embodiment, the request types include blocking accesses at highest priority, non-blocking page table walk accesses at medium priority, and non-blocking store allocation and prefetch accesses at lowest priority. The microprocessor takes advantage of the fact that the core logic clock frequency is a multiple of the processor bus clock frequency, typically by an order of magnitude. The microprocessor accumulates the various requests generated by the core logic each core clock cycle during a bus clock cycle. The microprocessor waits until the last core clock cycle before the next bus clock cycle to prioritize the accumulated requests and issues the highest priority request on the processor bus.

Abstract: Methods and structure for enhanced flexibility in bus arbitration without requiring modification to a standard arbiter circuit. Parameters for determining the priority of each channel involved in the arbitration are provided to a computational element to apply predicate functions thereto and thereby generate an index value. The index value is then used to access the lookup table for that channel to determine the present priority of the channel in an arbitration structure. The use of a lookup table permits simple modification to the arbitration structure for a particular application. The predicate evaluation of selected parameters further enhances flexibility in adapting the arbitration structure to the requirements of a particular application.

Abstract: A bus arbiter for arbitrating bus access requests from N bus requestor devices. The bus arbiter comprises N one-hot registers, each one-hot register associated with a corresponding bus requester device. Each one-hot register contains N priority bits rank-ordered from a lowest priority bit to a highest priority bit. Only one priority bit is enabled to indicate a priority of the corresponding bus requester device. The bus arbiter compares the priority bits in each one-hot register with a plurality of request signals received from the bus requester devices and grants bus access to the highest priority bus requester device.

Abstract: A loop of delayed read commands is established from a larger set of queued commands. Upon recognizing a delay in completing a first read command which is followed by a second read command, the loop is established by setting loop start pointer to identify the first delayed read command and setting a loop end pointer to identify the second read command. Upon recognizing a delay in completing the second read command which is followed by a third read command, the loop end pointer is advanced to identify the third read command. All of the read commands in the loop at and between the loop start pointer and the loop end pointer are completed before attempting to complete other commands in the queue not within the loop.

Abstract: A bus arbiter for a group of masters and a bus access control method. An arbitration priority control section output basic priority data for each of the masters. An arbitration priority generating section is provided for each of the masters, and combines the basic priority data for the corresponding master with request indication data indicating existence or non-existing of a bus access request from corresponding master to generate arbitration priority data. An arbitration priority comparing section compares the arbitration priority data for the masters with each other to determine the arbitration priority data which has the highest priority, and outputs a comparison resultant signal containing data for specifying the master corresponding to the arbitration priority data with the highest priority. An arbitration result notifying section outputs a bus use permission signal to the corresponding master with the highest priority in response to the comparison resultant signal.

Abstract: A distributed arbitration scheme includes arbiters with each agent. The arbiters receive request signals indicating which agents are arbitrating for the bus. Additionally, the agent currently using the bus broadcasts an agent identifier assigned to that agent. The arbiters receive the agent identifier and use the agent identifier as an indication of the winner of the preceding arbitration. Accordingly, the arbiters determine if the corresponding agent wins the arbitration, but may not attempt to calculate which other agent wins the arbitration. In one embodiment, the arbiter maintains a priority state indicative of which of the other agents are higher priority than the corresponding agent and which of the other agents are lower priority. In one implementation, the bus may be a split transaction bus and thus each requesting agent may include an address arbiter and each responding agent may include a data arbiter.

Abstract: A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An input gate is responsive to the status of the slave device and to receipt of a command from a master device when the slave device status is busy to set a bit in the non-queued split master vector identifying that the transaction with the corresponding master device is split. An output gate is responsive to a not busy status of the slave device to output the non-queued split master vector to the arbiter to re-arbitrate use of the data bus among the previously-split non-queued master devices.

Abstract: A crossbar switch is disclosed. The crossbar switch comprises a plurality of input sorting units and a plurality of merge and interleave units. Each input sorting unit is capable of receiving from a respective device an access request to any one of a plurality of physical memory devices. Each merge and interleave unit is capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests and forwarding the selected request for implementation on a respective memory device. Also disclosed is method implemented by the crossbar switch.

Abstract: An external bus control device 2 has first and second bus controllers 15, 16 and an external bus arbiter 17. The bus controllers 15, 16 correspond to devices (for example, SRAM, DRAM) connected to an external bus EXBUS respectively. The bus controllers 15, 16 respectively output external bus use request signals BRQ1 and BRQ2, and obtain the right for using the external bus EXBUS. When the bus controllers 15, 16 end use of the external bus EXBUS, the bus controllers 15, 16 stop to output the external bus use request signals BRQ1 and BRQ2 and output off-time signals OFT1 and OFT2 immediately thereafter.

Abstract: A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per memory. The buses are interconnected by at least one bridge. A processor is connected to a bus, and the data processing device comprises at least one memory table specifying with which memory an exchange of a data item between a processor and the memory system must be effected.

Abstract: A target device in a computer bus system allocates resources by selecting a priority requester for allocation of scarce resources. In a non-bus arbiter configuration, the first initiator device to receive a retry response to a transaction request after the resources are exhausted is designated as a priority requester. In a bus arbiter configuration, the priority requester is chosen on a round-robin basis from initiator devices that received a retry response to the initiator's most recent transaction request. If only one resource is available when an initiator sends a transaction request, the initiator receives a retry response unless the initiator is the priority requester.

Abstract: A circuit generally comprising a memory element and a controller. The memory element may define a semaphore allocatable to a resource. The controller may be configured to (i) present a granted status in response to a processor reading a first address while the semaphore has a free status, (ii) set the semaphore to a busy status in response to presenting the granted status, and (iii) present the busy status in response to the processor reading the first address while the semaphore has the busy status.

Abstract: Systems, devices, structures, and methods are provided to allow resources to be shared among a plurality of processors. An exemplary system includes a mechanism to grant exclusive control of a resource to a processor, while at the same time, the fast memory of such a processor is maintained in a coherent state. An exemplary structure includes data structures that help to identify the portion of the fast memory of the processor to be maintained in a coherent state. An exemplary method includes a determination of past and present processors that have had access to the resource so as to maintain the coherency of the fast memory of the processor.

Abstract: A method for dynamic preemption of read returns over a half-duplex bus during heavy loading conditions involves asserting a preempt signal by a first agent to indicate that the first agent has a read request pending for transmission over the half-duplex bus. A second agent then samples the preempt signal sent by the first agent. The second agent relinquishes ownership of the half-duplex bus responsive to the preempt signal to allow the read request to be sent across the half-duplex bus.

Abstract: A method and apparatus of deprioritizing a high priority client. An isochronous data stream request is generally referred to as a “high priority” client. These high priority requests are sensitive to time, such that a certain amount of data must be retrieved within a certain amount of time. The fetching of this data will cause increased latencies on lower priority clients making requests for data. A method and apparatus for deprioritizing a high priority client is needed to improve the efficiency in handling data traffic requests from both high priority and lower priority clients.

Abstract: An integrated circuit comprising a plurality of functional modules and interconnected via a packet router for conveying request and response packets is described. Transactions involve the dispatch of request packets and receipt of corresponding response packets. Each packet conveys a number of transaction attributes which can control how the packet is managed by control circuitry which controls the flow of packets on the packet router. For example the transaction attributes can include a transaction number, a grouping indicator, a priority indicator and a post indicator.

Abstract: Disclosed is a bus arbitration system and method which assume that each operation using the bus requires from one to five bus clock cycles. Each potential bus master has a dedicated bus request line and a dedicated bus grant line, both of which are connected to a centralized bus arbiter in the bus arbitration system of the present invention. When a potential bus master wants to use the bus for, for instance, three bus clock cycles, the bus master activates its dedicated bus request line for the same number of bus clock cycles as it would need of bus use (i.e. three bus clock cycles). This three clock wide bus request pulse is recorded in a bus request recording circuit in the centralized bus arbiter. Access to the bus can be granted by the centralized bus arbiter to a winning bus master under any bus arbitration policies.

Abstract: An I/O control device that transfers data according to transfer control information, comprising a transfer control information memory means that stores transfer control information, a state detecting means that detects the processed state of the transfer control information stored in the transfer control information memory means, and a transfer control information memory control means by which new transfer control information is stored in the transfer control information memory means in place of the transfer control information upon completion of transfer control information-dependent transfer processing as a result of the detection by the state detecting means.

Abstract: A computer system with a bus arbitration system adaptively assigns priority to devices on the bus based upon workload. A bus arbiter receives request signals from bus devices that require bus access, and also receives a signal indicating the pending workload of that device, as measured by the number of operations pending in a queue in that device. Based on the workload signal, the bus arbiter breaks any arbitration conflicts by assigning priority to the device with the greatest workload. In the event of ties, the bus arbiter may use other arbitration schemes to break ties between devices with equal workloads.

Abstract: A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles processing non-expedite requests during the monitoring window.

Abstract: A spin lock for shared memory is disclosed. A lock flag for a lock on a memory section is attempted to be set. If the lock flag is successfully set, the lock on the memory section is held so that the memory section may be processed. Upon being ready to release the lock on the memory section, and in response to determining that one or more units are spinning for the lock on the memory section, one of the spinning units is selected, and a spin flag for the selected unit is reset. If no units are spinning for the lock, however, the lock flag for the lock is reset.

Abstract: A bus arbiter (34) monitors characteristics associated with the type of information that is transferred via a global data bus (12) during burst transactions of information. A user-controlled arbitration policy register (56) may be programmed with values that are decoded to control whether interruption by a requesting bus master are permitted. Various factors can be used to determine interrupt permissions. Examples of such factors include the type of requesting device, whether a burst transaction is bounded or unbounded, whether a transaction is a read or a write of a system memory and the identity of the particular device requesting bus mastership.