Abstract: Implementations of the present specification provide an inter-thread interrupt signal sending method and apparatus. In the inter-thread interrupt signal sending method, a processor in which a first thread is located sends a notification message to a PCI device via a PCI bus by using an MMIO write operation. The MMIO write operation is implemented based on a virtual space address of the first thread to which a memory address of an MMIO memory of the PCI device is mapped. The PCI device generates an interrupt signal for a second thread in response to receiving the notification message, and sends the interrupt signal to a processor in which the second thread is located based on an interrupt signal sending manner configured in interrupt configuration information of the PCI device.

Abstract: A SIMD microprocessor is configured to execute programs divided into discrete phases. A scheduler is provided for scheduling instructions. A plurality of resources are for executing instructions issued by the scheduler, wherein the scheduler is configured to schedule each phase of the program only after receiving an indication that execution of the preceding phase of the program has been completed. By splitting programs into multiple phases and providing a scheduler that is able to determine whether execution of a phase has been completed, each phase can be separately scheduled and the results of preceding phases can be used to inform the scheduling of subsequent phases. In one example, different numbers of threads and/or different numbers of data instances per thread may be processed for different phases of the same program.

Abstract: A Turing incomplete smart contracting source code for use in a blockchain network is disclosed that allows for static analysis of a smart contract at the time of publishing.

Abstract: Techniques are disclosed relating to a shared control bus for communicating between primary control circuitry and multiple distributed graphics processor units. In some embodiments, a set of multiple processor units includes first and second graphics processors, where the first and second graphics processors are coupled to access graphics data via respective memory interfaces. A shared workload distribution bus is used to transmit control data that specifies graphics work distribution to the multiple graphics processing units. The shared workload distribution bus may be arranged in a chain topology, e.g., to connect the workload distribution circuitry to the first graphics processor and connect the first graphics processor to the second graphics processor such that the workload distribution circuitry communicates with the second graphics processor via the shared workload distribution bus connection to the first graphics processor.

Abstract: An apparatus and method for handling stash requests are described. The apparatus has a processing element with an associated storage structure that is used to store data for access by the processing element, and an interface for coupling the processing element to interconnect circuitry. Stash request handling circuitry is also provided that, in response to a stash request targeting the storage structure being received at the interface from the interconnect circuitry, causes a block of data associated with the stash request to be stored within the storage structure. The stash request identifies a given address that needs translating into a corresponding physical address in memory, and also identifies an address space key. Address translation circuitry is used to convert the given address identified by the stash request into the corresponding physical address by performing an address translation that is dependent on the address space key identified by the stash request.

Abstract: An intra-chassis device multi-management domain system includes a chassis housing a host processing system connected to first device(s), a secondary processing system connected to second device(s), and a management system connected to the first and second device(s). The management system may receive a first request for management access including first management domain access credentials, determine that the first management domain access credentials allow first access to a host domain associated with the host processing system and, in response, provide the first access to the first device(s) connected to the host processing system.

Abstract: Controlling a vehicle comprises: providing, from an activation port, an activation signal for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit that includes two or more processor cores during the high-speed activation time interval. The managing includes: receiving the activation signal from the activation port, in response to the activation signal, executing at least a portion of stored code by a first subset of fewer than all of the processor cores at a first power level, and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more of the processor cores at a second power level lower than the first power level.

Abstract: An apparatus comprises an interrupt distributor to distribute virtual interrupts to one or more physical processors, each virtual interrupt to be handled by one of a plurality of virtual processors mappable to said one or more physical processors; and control circuitry to maintain virtual processor interrupt tracking information corresponding to a given virtual processor. The virtual processor interrupt tracking information includes a pending interrupt record tracking which types of virtual interrupts are pending for the given virtual processor, and separate from the pending interrupt record, a pending interrupt status indication indicating a pending interrupt status for the given virtual processor. The pending interrupt status indicates whether the number of pending virtual interrupts for the given virtual processor is zero.

Abstract: A virtual machine that includes a plurality of processes executes on a computer processor. A record-replay file, trace annotations, and an application program interface request are received into the computer processor. The trace annotations and application program interface request are translated into record-replay commands. The record-replay commands capture data from the record-replay file, and the captured data can be accessed via a programmatic interface.

Abstract: A method includes asserting a field of an event flag mask register configured to inhibit an event handler. The method also includes, responsive to an event that corresponds to the field of the event flag mask register being triggered: asserting a field of an event flag register associated with the event; and based the field in the event flag register being asserted, taking an action by a task being executed by the data processor core.

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

Abstract: A context-based protection system uses tiered protection structures including master protection units, shared memory protection units, a peripheral protection units to provide security to bus transfer operations between central processing units (CPUs), memory array or portions of arrays, and peripherals.

Abstract: A data processing apparatus is provided comprising first processing circuitry. Interrupt generating circuitry generates an outgoing interrupt in response to the first processing circuitry becoming unresponsive. Interrupt receiving circuitry receives an incoming interrupt, which indicates that second processing circuitry has become unresponsive, and in response to receiving the incoming interrupt, causes the data processing apparatus to access data managed by the second processing circuitry.

Abstract: A storage system and an access control method thereof are provided. The storage system receives a first I/O request from at least one hypervisor. The first I/O request is used for accessing a first disk file of disk files. The storage system then operates a first I/O operation of a first virtual disk of virtual disks according to the first I/O request since the disk files correspond to the virtual disks. The storage system reads a QoS data of the first disk file and determines a first delay period according to the QoS data. The storage system transmits a first I/O response to the at least one hypervisor after the first delay period.

Abstract: A system for controlling a robot.

Abstract: A microprocessor system (1) includes a host processor (2), a graphics processing unit (GPU) (3) that includes a number of processing cores (4), and an exception handler. When a thread that is executing on a processing core (4) encounters an exception in its instruction sequence, the thread is redirected to the exception handler. However, the exception event is also communicated to a task manager (5) of the GPU 3. The task manager (5) then broadcasts a cause exception message to each processing core (4). Each processing core then identifies the threads that it is currently executing that the cause exception message relates to, and redirects those threads to the exception handler. In this way, an exception caused by a single thread is broadcast to all threads within a task.

Abstract: A transceiver for sending and receiving data from a controller area network (CAN) bus I disclosed. The transceiver is configured to detect if a node, after losing an arbitration, has sent a dominant bit on the CAN bus. The transceiver further configured to send a predefined bit pattern on the CAN bus after receiving the dominant bit from the node.

Abstract: Technologies are presented that allow application events to be recorded and replayed in a reliable and deterministic manner. A computing system may include a memory and a processor communicatively coupled with the memory. The processor may execute application logic of an application, record events associated with the application based on invocation of functions associated with the events, and store the recorded events in the memory for future playback. Recorded events may include, for example, user interactions, timing events, network downloads, callbacks, web worker tasks, etc. The recording of the events may include recording top-level functions of each event according to their order, and recording associated data including function parameters and/or return values. The recorded events may be replayed in order using the recorded associated data while suppressing non-recorded events.

Abstract: Event data for an application execution is accessed from a table of logged events, the event data comprising a sequence, a hierarchy, and a start time and duration for each event. Dependency data for each event is also accessed to determine whether the start time for an event is dependent on the prior completion of at least one other event. A waterfall representation is then generated, the representation including an entry for each event in the sequence, with a start time and duration represented for each event. Based on the dependencies and hierarchy, it is determined, for each event with a start time that is later than the start time of an event which precedes it in the sequence, whether the event's start time is dependent on the prior completion of at least one preceding event. The start time for each event may then be advanced based on the determination.

Abstract: A Turing incomplete smart contracting source code for use in a blockchain network is disclosed that allows for static analysis of a smart contract at the time of publishing.

Abstract: Aspects include receiving, at a pass-through server executing in a replay mode, a request directed to a backend resource. The request is received from an application that is connected to the pass-through server. The pass-through server executing in the replay mode identifies a response that corresponds to the request by: forming a key that includes an identifier of the current execution phase of the application and at least a subset of the request; accessing trace data that includes a plurality of keys and corresponding responses that were previously recorded in the trace data by the pass-through server executing in a recording mode; and using the key to locate, in the trace data, the response corresponding to the request. The identified response is relayed, by the pass-through server executing in the replay mode, to the application.

Abstract: Systems and methods for dynamic and adaptive interrupt coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device notifies the host device, via an interrupt, of entries on the completion queue. However, excessive interrupts become a burden to the host device. In that regard, the memory device includes a dynamic and adaptive interrupt coalescing methodology according to one or more parameters including: the completion queue; the commands; the queue depth; latency; and memory device firmware settings. In this way, the memory device may reduce the number of interrupts while still notifying the host device in a timely manner.

Abstract: In an approach to validation of correctness of interrupt triggers and delivery a computer allocates one or more flags of a gang of flags. The computer allocates one or more interrupt source numbers, wherein each interrupt source number of the one or more interrupt source numbers corresponds to a flag of the gang of flags. The computer allocates one or more virtual processors to process the one or more interrupt source numbers. The computer schedules the one or more virtual processors. The computer receives one or more interrupt triggers corresponding to the one or more interrupt source numbers. The computer updates the one or more flags corresponding to the one or more received interrupt triggers. The computer determines whether all of the one or more flags in the gang of flags is updated. The computer determines a lost interrupt source number.

Abstract: Methods, devices, and systems are described to modify the life cycle of a Google Android® application, in its application manifest file and byte code, such that the execution of the application can be controlled via policies and security governed by a workspace application installed on an Android-based device. Dummy wrapper classes are inserted into the byte code for network and I/O system calls that call security code before calling the original classes.

Abstract: Systems and techniques for memory and resource management in a virtual computing environment are disclosed herein. For example, in some embodiments, an apparatus for memory management in a virtual computing environment may include: a storage device; memory page comparison logic, coupled to the storage device, to determine that a first memory page of instructions, stored in the storage device, for a guest machine in the virtual computing environment is identical to a second memory page of instructions, stored in the storage device, for a host machine in the virtual computing environment, wherein the guest machine is hosted by the host machine; and merge logic, coupled to the memory page comparison logic, to, in response to a determination that the first memory page is identical to the second memory page, map the first memory page to the second memory page. Other embodiments may be disclosed and/or claimed.

Abstract: A method is implemented by a network device to configure the operation of a Peripheral Component Interconnect Express (PCIe) switch to enable an efficient transition from a first active processor in a first root complex to a backup processor in a second root complex. The method involves determining the first active processor in the first root complex and a set of backup processors and a set of root complexes, and configuring each root complex for independent PCIe switch communication. The method further includes detecting a failure of the active processor in the first root complex, selecting and notifying the backup processor and the second root complex to transition to be a second active processor and second root complex, and starting communication with PCIe devices using previously configured independent PCIe switch communication for the second processor of the second root complex.

Abstract: A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.

Abstract: Event data for an application execution is accessed from a table of logged events, the event data comprising a sequence, a hierarchy, and a start time and duration for each event. Dependency data for each event is also accessed to determine whether the start time for an event is dependent on the prior completion of at least one other event. A waterfall representation is then generated, the representation including an entry for each event in the sequence, with a start time and duration represented for each event. Based on the dependencies and hierarchy, it is determined, for each event with a start time that is later than the start time of an event which precedes it in the sequence, whether the event's start time is dependent on the prior completion of at least one preceding event. The start time for each event may then be advanced based on the determination.

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate multiple of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate a single processing core of the plurality of processing cores to be the bootstrap processor.

Abstract: At start-up of a computer apparatus, a CPU executes a first initialization procedure included in a RAS module to initialize resources to be used by the RAS module. After execution of the first initialization procedure, the CPU executes an initialization procedure included in an OS to initialize resources to be used by the OS. After execution of the initialization procedure, the CPU executes a second initialization procedure included in the RAS module to copy an interrupt determining part included in the OS to the RAS module, and to set the interrupt detection unit such that upon detecting an interrupt the interrupt detection unit calls an interrupt determining part copied to the RAS module, instead of the interrupt determining part in the OS.

Abstract: This invention relates to methods for controlling and monitoring access to network servers. In particular, the process described in the invention includes client-server sessions over the Internet. In this environment, when the user attempts to access an access-controlled file, the server subjects the request to a secondary server which determines whether the client has an authorization or valid account. Upon such verification, the user is provided with a session identification which allows the user to access to the requested file as well as any other files within the present protection domain.

Abstract: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.

Abstract: A method, system, and computer program product for performing user-initiated logging and auto-correction in hardware/software systems. Embodiments commence upon identifying a set of test points and respective instrumentation components, then determining logging capabilities of the instrumentation components. The nature and extent of the capabilities and configuration of the components aid in generating labels to describe the various logging capabilities. The labels are then used in a user interface so as to obtain user-configurable settings which are also used in determining auto-correction actions. A measurement taken at a testpoint may result in detection of an occurrence of a certain condition, and auto-correction steps can be taken by retrieving a rulebase comprising a set of conditions corresponding to one or more measurements, and corrective actions corresponding to the one or more conditions.

Abstract: Embodiments include method, systems and computer program products for a parallel ordering queue using an encoded command type. In some embodiments, a command may be receive from a receiver of a first bus, wherein the command is to be sent to a second bus. The command may be decoded. The command may be associated with an encoded command type. The command may be placed in an ordering queue. A first entry of a second queue may be popped based on the encoded command type of the first entry of the ordering queue. The first entry of the ordering queue may be removed from the ordering queue.

Abstract: A storage controller of a data storage system maintains, for each interrupt vector, (1) a pending status that indicates whether one or more completions are pending in the completion queue (CQ) associated with the interrupt vector, and (2) an in-progress status that indicates whether or not the storage controller is currently in the process of composing an interrupt. The storage controller utilizes these two statuses to reduce or eliminate spurious interrupts by preventing an interrupt from being composed if there are no completions in the CQ, by preventing an interrupt from being composed if the corresponding interrupt mask has been set before composition of the interrupt begins, and by preventing an interrupt from being sent to the host system in cases where the interrupt mask was set after composition of the interrupt began, but before the interrupt has been sent to the host system.

Abstract: Embodiments are directed to systems and methodologies for allowing a computer program code to efficiently respond to and process events. For events having a multiple stage completion sequence, and wherein several of the events occur within relatively close time proximity to each other, portions of the multiple stages may be coalesced without adding latency, thereby maintaining responsiveness of the computer program. The disclosed coalescing systems and methodologies include state machines and counters that in effect “replace” certain stages of the event sequence when the frequency of events increases.

Abstract: A shell device with minimal software and/or hardware resources can download from a server configuration information and/or user data in order to allow the shell device to communicate with other computing devices (whether cell phones, personal digital assistants, laptops, and the like). Various security features can also be used herein, including a shell device password and a server network access password. In another aspect, any time code and/or data is downloaded from the server to the shell device, such code and/or data resides on the shell device during the time of a communication between the server and the shell device; thereafter, it can be deleted, thereby returning the shell device to its minimalistic resource state. When the shell device contacts the server again and attempts to establish another communication, such code and/or data can be downloaded anew, and after the communication it can be deleted again.

Abstract: A multiprocessor device is provided that includes a plurality of processors in which each processor of the plurality of processors includes an interrupt controller, and a symmetric interrupt crossbar having a plurality of interrupt inputs in which each interrupt input that is not reserved is coupled to a respective interrupt output of an interrupt source of a plurality of interrupt sources, and a plurality of interrupt outputs in which each interrupt output is coupled to a respective interrupt input of an interrupt controller of one of the plurality of processors, in which the symmetric interrupt crossbar is programmable to map an interrupt signal from any interrupt source of the plurality of interrupt sources coupled to the symmetric interrupt crossbar to any interrupt input of any interrupt controller coupled to the symmetric interrupt crossbar.

Abstract: A ticket request is transmitted from an execution engine to an authentication engine. In response, a ticket comprising privileges is received from the authentication engine. The ticket is transmitted to a client, and a service request including the ticket is received back from the client. A service is executed in response to the ticket received from the client and results are transmitted to the client.

Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.

Abstract: A drive control device includes: an embedded microcontroller including a program for outputting a drive control signal to a driving unit; a first timer circuit for outputting a cyclic signal to the embedded microcontroller, wherein the embedded microcontroller reads the cyclic signal outputted from the first timer circuit and transmits the cyclic signal to output a transmission signal as part of operation of the program; and a second timer circuit provided externally to the embedded microcontroller, wherein the transmission signal is inputted to the second timer circuit, the second timer circuit obtains temporal change of the transmission signal for a time set in advance, and the second timer circuit outputs, based on the obtained result, a signal indicating one of different operation states of the embedded microcontroller depending on whether or not there is continuous temporal change of the transmission signal.

Abstract: Methods, devices, and systems are described to modify the life cycle of a Google Android® application, in its application manifest file and byte code, such that the execution of the application can be controlled via policies and security governed by a workspace application installed on an Android-based device. Dummy wrapper classes are inserted into the byte code for network and I/O system calls that call security code before calling the original classes.

Abstract: With N_Port ID Virtualization (NPIV), a managed system can be configured so that multiple logical partitions (LPARs) can access independent physical storage through the same physical fiber channel adapter. An NPIV client recovery component of a virtualization management component, such as a Power Hypervisor (pHYP), provides the emulation mapping between server and client virtual fiber channel adapters. The pHYP also provides a mechanism that prevents client partition crashes when the NPIV server (e.g., a VIOS logical partition) goes down. When the NPIV server is rebooted or powers down, the pHYP handles the client LPARs to avoid a crash by removing processing resources from the client logical partition. Thereby, the client logical partition is prevented from attempting to access a root volume group in physical storage via the NPIV server. The pHYP allocates processor resources to the client LPAR when the NPIV server is again available for I/O processing.

Abstract: A signal switching circuit allows a PCIe card access to additional data channels when installation of the PCIe cards on first and second PCIe connectors are detected. First and second PCIe connectors output a first detection signal when each of the first and second PCIe connectors receives a PCIe card. The first and second PCIe connectors output a second detection signal when each of the first and second PCIe connectors does not receive a PCIe card. A first multiplexer receives the first or second detection signal and connects an input terminal to first or second output terminal of the first multiplexer, to transmit PCIe signals to the first or second PCIe connector. A second multiplexer receives the first or second detection signal and connects an input terminal to first or second output terminal of the second multiplexer, to transmit PCIe signals to the first or second PCIe connectors.

Abstract: One embodiment describes a fault tolerant transmission system that includes a programmable logic device. The programmable logic device includes a first serial port communicatively coupled to a first serial link, in which the first serial port receives a first transmission signal from the first serial link, and a second serial port communicatively coupled to a second serial link, in which the second serial port receives a second transmission signal from the second serial link. The first serial link and the second serial link are disposed in parallel with each other and communicate over a first single conduit, and the first communication signal and the second communication signal are representative of identical information.

Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

Abstract: Methods and systems for conducting a transaction between a virtual USB device driver and a USB device client are provided. A hypervisor of a computer system receives one or more data packets from the client. The hypervisor stores the one or more data packets in a buffer. The hypervisor dequeues a data packet from the buffer. The hypervisor transmits the data packet to the virtual USB device driver.

Abstract: A method and system for distributing audio, visual, data, annunciator and other information within an educational facility utilizes a bit-wise addressing scheme to route UDP message packets to individual classrooms. The audio/video network system includes a central processor that controls a plurality of audio/video sources (e.g., DVD players, cable TV receivers, etc.). Output from audio/video sources is encoded by audio/video encoders for transmission via a local area network. Classroom control hubs within each classroom recognize data packets addressed with the bit-wise addressing scheme and in combination with a video decoder, recover the encoded audio/video signal for presentation within the classroom, such as by a video projector and classroom speakers. Transmitting audio/video information in UDP packets addressed with the bit-wise addressing scheme enables near simultaneous presentation of audio and video programs throughout the educational facility.

Abstract: Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that in turn includes various indicators corresponding to processing elements. In some embodiments, the interrupt processing unit may be configured to receive an interrupt and determine whether a first processing element associated with the interrupt is available to receive interrupts. The system may initiate a corrective action if the first processing element is not available to receive interrupts. In some embodiments, the corrective action may include redirecting the interrupt to a second processing element. In some embodiments, the interrupt processing unit may include a dropped interrupt management register to store information corresponding to the second processing element.

Abstract: A computing apparatus determines that a virtual processor of a guest has been moved from a first physical processor of a host to a second physical processor of the host. The computing apparatus identifies a device that is controlled by the virtual processor, wherein device interrupts for the device are forwarded to the virtual processor. The computing apparatus updates at least one of the device or an interrupt controller to cause at least one of the device or the interrupt controller to send the device interrupts to the second physical processor of the host, wherein the second physical processor of the host forwards the device interrupts to the virtual processor running on the second physical processor without generating an inter-processor interrupt.