Abstract: The present invention relates to a device for an interrupt verification support mechanism and the method for operating said device comprising a processor and an input for external interrupt requests or interrupt pseudo-instructions communicatively coupled to the processor. The method comprises the steps of processing at least one actual instruction in the processor in an instruction pipeline, and if an external interrupt request is received by the processor, the actual instruction is replaced with the pseudo-instruction. Pursuant to the method, instructions are concurrently processed in the processor in an instruction pipeline with several stages. In the instruction pipeline, instructions are processed by an instruction fetch stage, an instruction decode stage, an instruction issue stage, an execute stage and a result write-back stage. Thereby, interrupt requests are only processed at the fetch stage of the instruction pipeline.

Abstract: In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the host code. A patching mechanism evaluates the operating system version, processor, and code to be patched. If patchable, low-level interfaces are created dynamically; a dispatcher is written into an unused location in vector space, and instructions copied from each interrupt vector to be patched to a guest interrupt vector. For an interrupt, the new, patched instructions branch to the dispatcher, which then branches to the appropriate patched interrupt guest code. If the processor is operating as a virtual machine, the guest interrupt code handles the interrupt, otherwise the original copied instructions are replayed, followed by execution at the original host instruction in vector space that exists after the copied and patched instructions.

Abstract: A system and method that abstracts an interrupt from a group of interrupts, which may occur in a module, to call another module. Abstracting one interrupt from a group of interrupts allows the called module to deal with only one interrupt. The choice of the interrupt may be based on the configuration of the module from which the interrupts are originated. In an embodiment of the present invention, the abstracted interrupt triggers an event. When the triggered event is completed, an interrupt may be fired off to the target module. An interrupt handler in the target module or an external interrupt handler may handle the interrupt that calls the target module.

Abstract: System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated using a real-time clock (RTC) residing on a chipset. A flag indicating a periodic interrupt is entered into a status register associated with the RTC in firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending. An interrupt handler associated with the RTC attempts to handle the periodic interrupt, if pending. If the periodic interrupt is pending after a preset interval of time elapses, a basic-input-output system (BIOS) residing on a memory unit coupled to the chipset generates a system-management interrupt (SMI). If the periodic interrupt is pending after the preset interval of time elapses, a firmware SMI handler residing on the memory unit clears the pending periodic interrupts from the status register.

Abstract: A system and method have been provided for pushing cacheable control messages to a processor. The method accepts a first control message, identified as cacheable and addressed to a processor, from a peripheral device. The first control message is allocated into a cache that is associated with the processor, but not associated with the peripheral device. In response to a read-prompt the processor reads the first control message directly from the cache. The read-prompt can be a hardware interrupt generated by the peripheral device referencing the first control message. For example, the peripheral may determine that the first control message has been allocated into the cache and generate a hardware interrupt associated with the first control message. Then, the processor reads the first control message in response to the hardware interrupt read-prompt. Alternately, the read-prompt can be the processor polling the cache for pending control messages.

Abstract: An interrupt notification block stored in host memory is disclosed that contains an image of the interrupt condition contents that may be stored in a host attention register in a host interface port. The interrupt notification block is written by the host interface port and pre-fixed into the port pointer array of a host at the time the host interface port updates the pointers stored in a port pointer array in host memory. The host may then read the interrupt notification block to determine how to process a response or an interrupt rather than having to read the host attention register in the host interface port across the host bus.

Abstract: A method of providing media content (e.g., audio and/or video) and processing data received over a network. Received data may be processed at a reduced rate while at least one media application is running. Received packets may be processed in batches, and media data may be processed in between processing the batches. The method may provide for reducing or eliminating glitches in the media content caused by receiving data over a network while providing the media content.

Abstract: A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.

Abstract: An apparatus and a method for controlling power consumption in a system having a plurality of modems are provided. In the method, whether an interrupt is generated in each modem is detected. An amount of current consumption of the system at a processing point of the generated interrupt is determined. The amount of current consumption of the system is compared with a threshold, so that the processing point of the generated interrupt is controlled.

Abstract: A method for restoring system configuration information of a network attached storage includes the steps of: setting system configuration information of an network attached storage as a backup file; registering an interrupt handler; pressing down an input key (16) to turn off a power switch (K1) and generate an interrupt signal; invoking the interrupt handler to process the interrupt signal and returning interrupt GPIO information; determining whether an operating system receives the interrupt GPIO information from the interrupt handler; sending a periodical voltage to a second pin (P2) for blinking a LED (L1) if the operating system receives the interrupt GPIO information from the interrupt handler; invoking the backup file to restore the system configuration information of the network attached storage; and sending a high voltage command to the second pin for powering off the LED, which indicates that the system configuration information has been restored.

Abstract: Device, system, and method of utilizing PCI Express packets having modified headers. For example, an apparatus includes a credit-based flow control interconnect device to generate a credit-based flow control interconnect Transaction Layer Packet in which one or more bits of an ID field carry non-ID data.

Abstract: A system comprises processing logic. The system also comprises a first interrupt controller coupled to the processing logic and configured to manage interrupts provided to the processing logic. The system further comprises a second interrupt controller coupled to the first interrupt controller. The second interrupt controller is programmable to distribute received interrupts to the first interrupt controller via different output ports.

Abstract: Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

Abstract: An embedded system and an interruption handling method are provided. A plurality of interruption requests are received, and corresponding service routines are triggered with priority control. In the embedded system, a memory device comprises a plurality of service routines stored at different entry addresses, each related to an interruption request. A processor receives an enable signal to initialize one of the service routines through a branch instruction. A control unit buffers the interruption requests to schedule executions of corresponding service routines. When a specific service routine is to be executed, the control unit provides the branch instruction pointing to entry address of the specific service routine and asserts the enable signal to the processor, such that the processor executes the branch instruction to initialize the specific service routine.

Abstract: The invention relates to a real time-capable control system essentially consisting of a software-implemented SPS application that exchanges the output data and input data by means of a field bus connecting module. The SPS application runs on a computer under the control of a non-real time-capable operating system, whereby the full functionality of the non-real-time-capable operating system is maintained. The real time capability makes the field bus connecting module ready for use, and the data are exchanged between the field bus connecting module and the SPS application via the host interface located inside the computer.

Abstract: An even-driven interrupt processing is efficiently carried out in a multiprocessor system. A main control unit 112 executes a main process as a processing for controlling an apparatus in a unified manner. A sub-control unit 116 executes a task assigned by the main control unit 112 during the execution of the main process, as a sub-process. An event detector 162 detects an event occurrence upon which an interrupt task is to be preferentially executed during the execution of the main process. An interrupt notification unit 164 notifies the sub-control unit 116 of interrupt information indicative of an interrupt task in response to the detected event. The sub-control unit 116 notified of the interrupt information executes the interrupt task specified by the interrupt information, as a sub-process.

Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system is provided. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

Abstract: An improved meter and its operation is described. The meter can be a part of a larger automated meter reading process that allows for remote reading of the meter though power line communication. Using a microcomputer core, the meter processes incoming analog data and can calculate several relevant data values need by utility providers. The meter can also be used to monitor and detect tampering dry connect/voltage free devices, such as gas and water meters, connected to the meter.

Abstract: An interrupt controller for managing interrupt requests comprises interrupt control circuitry in a first domain, the first domain being switchable to a low-power mode, and interrupt request monitoring circuitry in a second domain. The interrupt control circuitry is responsive to a low power request signal received by the interrupt controller to communicate interrupt select information to the interrupt request monitoring circuitry prior to the first domain being switched to a low power mode, the interrupt select information identifying interrupt requests which indicate exit from the low power mode. The interrupt request monitoring circuitry comprises a select information store configured to store the select information communicated to the interrupt request monitoring circuitry by the interrupt control circuitry.

Abstract: A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the processors that results from an initial mapping of the interrupts to the processors. The interrupt daemon determines whether there is a sufficient imbalance of the interrupts among the processors. If so, the interrupt daemon triggers a reassignment routine that generates a new mapping of the interrupts among the processors, and if not, the interrupt daemon goes to sleep for a specified time period. If the new mapping produces a sufficient improvement in the distribution of interrupts among the processors, based on the same criteria used to detect the imbalance, the new mapping is used by the central hub for subsequent distribution of interrupts to the processors. However, if the new mapping does not provide a sufficient improvement, the original mapping continues to be used.

Abstract: A data processing system 2 supporting interrupt handling is provided with an interrupt controller 24. The interrupt controller is responsive to save state data when interrupt processing is commenced by pre-emption of existing processing, whether that be background processing or another interrupt. If a further interrupt is required to be executed immediately after the interrupt which triggered the pre-emption, then the speed with which interrupt processing can be started is advantageously increased if that subsequent interrupt processing is performed without restoring and then resaving the original state data. The interrupts in this arrangement can be considered to be chained together without intervening save and restore operations.

Abstract: A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.

Abstract: A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of the expansion modules. The master module then receives completion signals from all of the active slave modules and then provides only one interrupt to the central processing unit for that task.

Abstract: A system (150) and method provide for the transfer of at least one packet (194) comprising data between a user space (152) and a kernel space (154) associated with a server (156) that is positioned in a distributed network arrangement (192) with a plurality of clients (158, 160, 162, 164). A distribution program (168) associated with the user space (152) is operable to accumulate the at least one packet (194). An application program interface (174) associated with the user space (152) transfers the at least one packet (194) to the kernel space (154) with a number of software interrupts (204). A driver (176) associated with the kernel space (154) is operable to distribute the at least one packet (194) to a subset of the plurality of clients (158, 160, 162, 164) in response to receiving the number of software interrupts (204). The number of software interrupts (204) is less than one software interrupt per packet per client.

Abstract: A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered.

Abstract: Executing application function calls in response to an interrupt including creating a thread; receiving an interrupt having an interrupt type; determining whether a value of a semaphore represents that interrupts are disabled; if the value of the semaphore represents that interrupts are not disabled: calling, by the thread, one or more preconfigured functions in dependence upon the interrupt type of the interrupt; yielding the thread; and if the value of the semaphore represents that interrupts are disabled: setting the value of the semaphore to represent to a kernel that interrupts are hard-disabled; and hard-disabling interrupts at the kernel.

Abstract: A controller in a processing system can detect programmable bit sequences sent from a host processor to an external device, such as a memory, indicating whether a response from the external device needs to be read. The controller can also read a response from the external device and act appropriately, e.g., determine if an error has occurred by comparing the device's actual response to one or more programmably determined responses. Upon reading a particular response, e.g., a response indicating an error, the controller can issue an interrupt request to the host processor for further action. The controller can also track which external device access caused a particular response to occur.

Abstract: A method and a system for automatically diagnosing disability of computer peripheral devices are provided. In the method, a set of interrupt configuration data relevant to a disabled PCI peripheral device, including relevant setting values of a hardware IRQ routing, is input and compared with a PCI IRQ routing table pre-stored in a boot control unit. Then, whether errors exist in the current setting values of the relevant control parameters and flags of all the relevant control units are automatically checked. If an incorrect setting value is found, a corresponding diagnosis result message is displayed for informing the user to make a modification. Therefore, users can know the reasons that cause the computer peripheral device to operate abnormally and make the modification quickly and effectively.

Abstract: A method for dynamically arranging interrupt pins is provided, which is suitable for arranging a plurality of interrupt pins of a control chip. In this method, a number of interrupts sent from each of a plurality of device paths in a unit time is detected. The device paths are sorted according to the interrupt numbers thereof. Then, from the one in the head of the sequence, the devices paths are arranged to the interrupt pins. Herein, when arranging a device path, an interrupt checking number required to check the device path sending the interrupt every time an interrupt is produced in each of the interrupt pins is calculated. Then, when arranging the next device path, the device path is arranged to the interrupt pin with the least interrupt checking number.

Abstract: A control and communication unit is provided between a terminal and at least one microcircuit card. The unit includes a control module for a number of input signals to the card; a module for generation of a number of time diagrams for the card communication protocols; a request generation module for transmission and reception of characters based on information received from the control module, the requests being transmitted to an external module; and an interruption generation module for creating an interruption in the case of an error in a time diagram or a character received or transmitted, based on information received from the control module and for processing the interruption without a loss of characters. The generation of an interruption does not cause an interruption in the process of request generation.

Abstract: A communication program causes a computer to perform communication processing of received packets in response to reception of interrupt processing, the interruption processing being a packet reception notification after the lapse of a predetermined holding time. The communication program causes the computer to perform a packet counting process of counting the number of received packets received per unit time, and a parameter value changing process of changing, based on a counting result of the packet counting process, a timer parameter value for determining the time packets are held before processing.

Abstract: An information processing apparatus improves the efficiency of use of a program capable of dynamically interrupting another program with a process. The program capable of dynamically interrupting another program with a process is received via a network and applied to the other program. A setting is received indicating whether the predetermined program should be applied to the other program when, after the predetermined program is applied, a supply of power to at least a part of the information processing apparatus is terminated and then resumed. Reapplication necessity information indicating the setting is stored in a storage unit. The predetermined program is reapplied to the other program when, after the application of the predetermined program, the supply of power to the at least a portion of the information processing apparatus is terminated and then resumed, based on the reapplication necessity information.

Abstract: A bus arbitration section and a resource control section are interposed between a shared resource and a plurality of bus masters. The minimum number of receivable access permissions within a given period is set as bus arbitration information for each of the bus masters. If two or more of the bus masters issue access requests at the same time, the bus arbitration section preferentially gives access permission to a bus master which gained access permission a number of times less than a set value in the bus arbitration information within the given period, out of the two or more access bus masters.

Abstract: A method for dynamically allocating interrupt pins is provided. The present method is used for allocating a plurality of interrupt pins of a control chip. In the present method, a hardware routing table is read first and a plurality of slots that have used the interrupt pins is found out from the hardware routing table. These slots are sorted according to the number of interrupt pins used by each slot. Then, from the slot in the first order of the sequence, the interrupt pins are allocated for a plurality of registers in the control chip corresponding to these slots by turns. The allocation is repeated once the last interrupt pin is allocated until all the registers for the slots are allocated with an interrupt pin.

Abstract: An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.

Abstract: In a method of detecting and protecting a hard disk of a falling portable computer, a falling sensor detects a falling state of a portable computer and sends an interrupt signal to a keyboard controller of the computer, and a falling state signal is responded at a default signal port of the keyboard controller. A software monitoring driver executes polling via an I/O driver about the falling state signal at the default signal port of the keyboard controller, and determines based on the falling state signal whether to actuate a hard disk protection mechanism, in which the software monitoring driver interrupts hard disk data access on the computer via a hard disk driver, and causes a system BIOS of the computer to send a parking control signal to the hard disk.

Abstract: In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.

Abstract: A method for synchronizing processors during a system management interrupt caused from a memory hot plug event in multiple processor systems is disclosed. In one embodiment, a method for synchronizing processors during an assertion of a system management interrupt (SMI) in an information handling system including, for each processor, identifying whether the processor is an interrupt handling processor assigned to perform processing tasks necessary for resolving the SMI or a non-interrupt handling processor not assigned to perform the processing tasks necessary for resolving the SMI. The method further includes creating a task structure operable to cause non-interrupt handling processors to perform at least one task for each interrupt handling processor. The method further includes automatically performing the at least one task during the SMI for each non-interrupt handling processor.

Abstract: A device for high-assurance processing is disclosed. A processing circuit uses an access controller to assure that the processing circuit operates properly. The processing circuit runs software programs and is programmable. The access controller is programmable, but not programmable by the processing circuit. Peripherals or segments of the address space of the processing circuit is regulated. In a particular state, the peripherals that are available are regulated by the access controller. In some embodiments, the transition from state-to-state can also be regulated by the access controller.

Abstract: A real-time control system for executing exactly a cyclic task, preventing a delay of the processing start time due to accumulation of a plurality of overhead times, thereby executing control enabling a more detailed response and control enabling a quick and reliable response to a plurality of instructions is provided. The real-time control system includes a driver unit for receiving an input signal and outputting an interruption signal corresponding to each task process, a polling unit for polling on the basis of the concerned interruption signal, and a task processor for performing a task process on the basis of the interruption signal, wherein the polling unit outputs a task processing signal on the basis of the polling when the task is finished and the task processor performs the task process on the basis of the task processing signal.

Abstract: An apparatus and method for interrupt source signal allocation is provided. An interrupt controller may include an interrupt source allocation unit, an interrupt pending register, a control register, a priority register, and/or an interrupt request signal generator. The interrupt source allocation unit may output one or more interrupt source signals based on one or more priorities, and may allow a user to move an individual interrupt source signal without moving other interrupt source signals. The interrupt pending register may set bits in one or more registers corresponding to the interrupt source signals. The control register may control and transmit the interrupt source signals corresponding to the set bits. The priority register may determine the priorities of the interrupt source signals. The interrupt request signal generator may output an interrupt request signal in response to one or more interrupt source signals received from the priority register.

Abstract: The setting of interruption initiatives is directly initiated by external adapters. An adapter external to the processors at which the initiative is to be made pending sends a request directly to a system controller coupled to the adapter and the processors. The system controller then broadcasts a command to the processors instructing the processors to set the interruption initiative.

Abstract: In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the host code. A patching mechanism evaluates the operating system version, processor, and code to be patched. If patchable, low-level interfaces are created dynamically; a dispatcher is written into an unused location in vector space, and instructions copied from each interrupt vector to be patched to a guest interrupt vector. For an interrupt, the new, patched instructions branch to the dispatcher, which then branches to the appropriate patched interrupt guest code. If the processor is operating as a virtual machine, the guest interrupt code handles the interrupt, otherwise the original copied instructions are replayed, followed by execution at the original host instruction in vector space that exists after the copied and patched instructions.

Abstract: Method, computer program product and system for handling multiple system management interrupt (SMI) events in a multiprocessor system. In response to receiving an SMI event, processors enter system management mode (SMM) and execute SMI handler code. An SMI handler that determines fewer than all of the processor are in the SMI handler for the event will schedule an further SMI event based upon the content of the detected SMI event, then issues a resume (RSM) instruction and exits the SMI handler. The method recovers lost SMI events caused by latency between multiple processors entering or exiting SMM.

Abstract: The present invention relates to an adaptive interrupts coalescing system with recognizing minimum delay packets. The adaptive interrupts coalescing system of the invention comprises a first calculating device, a packet header parser, a second calculating device, and an interrupt controller. The first calculating device is used for calculating packet information of a plurality of packets. The packet header parser is used for recognizing the type of service field in each packet and for generating a minimum delay control signal. The second calculating device is used for determining a coalescing interrupt number signal according to the packet information and the minimum delay control signal. The interrupt controller is used for transmitting an interrupt control signal to process the packet according to the coalescing interrupt number signal.

Abstract: A microcontroller (MC) has integrated functional modules (FM) encompassing a first functional module (FM1) which is configured so as to activate or deactivate interrupts (INT). High-frequency triggering events for interrupts are common especially in the preferred field of application of such microcontrollers, i.e. the equipment and operation of digital tachographs, because the signal of a speed sensor has to be recorded also at high speeds. This may affect the process stability when other request sequences are processed. In order to prevent this from happening, the first functional module (FM1) deactivates an interrupt (INT) once requests (IRQ) have been processed and activates said interrupt (INT) again following a delay period (IED) that is associated with the interrupt (INT). The procedure combines the advantages of controlling processes by time intervals and the advantages of an interrupt controller.

Abstract: One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt mask value is written to the TPR. In addition, the interrupt mask value is also written into a shadow copy of the TPR. The shadow copy is written each time that the TPR is written. Another embodiment disclosed relates to a method of reducing a latency to read a TPR of an IPF type microprocessor. When a command is received to read an interrupt mask value from the TPR, the interrupt mask value is read from the shadow copy at a memory location, instead of from the task priority register itself.

Abstract: A monitor method of computer system is provided, applying within an interrupt service routine. According to the application of interrupt service, when the interrupt controller sends an interrupt signal to the CPU, the CPU executes a corresponding interrupt service routine based on the interrupt signal, in the meantime, the daemon program generates an entrant code. Before the interrupt service routine stops, the daemon program generates an exit code and saves both the entrant code and the exit code in a storage device. It is benefit for solving the problems occurred in the debugging process according to the entrant code and the exit code of the storage device, and speeding up the process of testing and researching steps.

Abstract: New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

Abstract: A computer includes a processor, an input device and a read only memory (“ROM”). One or more passwords are flashed in the ROM in encoded form. The encoding process may include any well-known encryption or hash process. The password may include a power-on password usable to change the operating state of the computer and/or an administrator password. Such configuration data preferably also is stored on the ROM in encoded form. The encoded nature of the passwords makes it difficult for an unauthorized entity to gain access to the usable form of the passwords. Further, by storing the passwords and configuration in ROM, such as the computer's main system ROM, it is possible to control write access to the ROM because a computer's ROM can generally only be flashed using SMI code which operates outside the control of the computer's operating system and requires entry of a correct password.