Abstract: The client requests from the authentication and authorization server a capability for accessing the target server. The authentication and authorization server sends client a capability (capC,S) comprising the public key (pubC) of the client, said capability being signed with a private key (privAA) of the authentication and authorization server. The client sends the capability (capC,S) to the target server. If the capability is valid, the target server grants the client access and a data exchange session can be initiated. The disclosed protocol is scalable, as it does not require individual configuration of each target server device, allows revocation of user access within reasonable time, stores no compromisable secret data on any target server device, enables individual access permission per user, and accountability of each user.

Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.

Abstract: A process for managing interrupts, which may be performed using electronic circuitry, includes: receiving interrupts bound for a processing device, where the interrupts are received from hardware devices that are configured to communicate with the processing device; generating data containing information corresponding to the interrupts; and sending the data to the processing device.

Abstract: An interrupt controller coupled to a plurality of processors is provided to rout at least one interrupt request event to at least one of the processors. The interrupt controller includes a receiving circuit and a controlling circuit. The receiving circuit receives at least one interrupt input, and the controlling circuit, generates the at least one interrupt request event based on the received at least one interrupt input and routes the at least one interrupt request event generated to the at least one of the processors. The plurality of processors including at least a first processor and a second processor, the first and second processors arranged to process interrupt request event(s), and the controlling circuit is arranged to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor.

Abstract: CPU architecture is modified so that content of the interrupt mask register can be changed directly based on a decoding result of an instruction decoder of a CPU. Such modification does not require a great deal of labor in changing a CPU design. In addition, an extended CALL instruction and an extended software interrupt instruction are added to the CPU, and each of the extended CALL instruction and the extended software interrupt instruction additionally has a function of changing the value of the interrupt mask register. Atomicity is achieved by: allowing such a single instruction to concurrently execute a call of a process and a value change of the interrupt mask register; and disabling other interrupts during execution of the single instruction.

Abstract: Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities.

Abstract: A computing apparatus identifies that a first physical processor of a host has forwarded information regarding a device interrupt for a device to a second physical processor executing at least one of a virtual processor that controls the device or an application thread that controls the device. After identifying that the first physical processor has forwarded the information regarding the device interrupt to the second physical processor and in response to determining that one or more update criteria have been satisfied, the computing apparatus updates at least one of the device or an interrupt controller to cause at least one of the device or the interrupt controller to send future device interrupts for the device to the second physical processor.

Abstract: Numerous embodiments of a method and apparatus for processing latency sensitive electronic data with interrupt moderation are disclosed.

Abstract: A method and apparatus to operate programmable routing logic comprise receiving, from a fixed function block, a first request, responsive to the first request, forwarding the first request to a first resource of one or more controllers, the first resource allocated to the fixed function block. The method and apparatus further comprise receiving, from a programmable function block, a second request, and responsive to the second request, forwarding the second request to a second resource of the one or more controllers, the second resource allocated to the programmable function block.

Abstract: An apparatus, method, system, and computer-readable medium are disclosed. In one embodiment the apparatus is a processor. The processor includes thread remapping logic that is capable of tracking hardware thread interrupt equivalence information for a first hardware thread and a second hardware thread. The processor also includes logic to receive an interrupt issued from a device, wherein the interrupt has an affinity tied to the first hardware thread. The processor also includes logic to redirect the interrupt to the second hardware thread when the hardware thread interrupt equivalence information validates the second hardware thread is capable of handling the interrupt.

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract: One particular example implementation of an apparatus that includes logic, the logic at least partially comprising hardware logic to: trigger a particular interrupt based, at least in part, on input/output (I/O) activity when a predetermined state is activated on a platform; generate a system control interrupt based, at least in part, on a source associated with the particular interrupt; and route the system control interrupt to a custom system control interrupt handler.

Abstract: A microprocessor includes a storage element having a plurality of locations each storing decryption key data associated with an encrypted program. A control register field (may be x86 EFLAGS register reserved field) specifies a storage element location associated with a currently executing encrypted program. The microprocessor restores from memory to the control register a previously saved value of the field in response to executing a return from interrupt instruction. A fetch unit fetches encrypted instructions of the currently executing encrypted program and decrypts them using the decryption key data stored the storage element location specified by the restored field value. A kill bit associated with each storage element location may be employed if the location is clobbered because more encrypted programs are multitasked than available locations in the storage element, in which case an exception is generated to re-load the clobbered decryption key data in response to the return from interrupt instruction.

Abstract: A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.

Abstract: A method and apparatus are provided for controlling system management interrupts is disclosed. The method comprises: receiving an interrupt signal; determining a type associated with the interrupt signal; using the determined type to access control information indicating an action to be applied to the determined type of interrupt; and blocking, passing or remapping the interrupt signal in response to the control information. The apparatus comprises a memory, an interrupt unit and a logic circuit. The memory is adapted to store control information regarding a plurality of types of interrupt signals. The interrupt unit is adapted to receive the interrupt signal, and use the interrupt type contained in the interrupt signal to access the control information stored in the memory. The logic circuit is adapted to block, pass or remap said interrupt signal in response to the control information.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores.

Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.

Abstract: A method of enabling multiple different operating systems to run concurrently on the same RISC computer, comprising selecting a first operating system to have a relatively high priority (the realtime operating system, such as C5); selecting at least one secondary operating system to have a relatively lower priority (the general purpose operating system, such as Linux); providing a common program (a hardware resource dispatcher similar to a nanokernel) arranged to switch between said operating systems under predetermined conditions; and providing modifications to said first and second operating systems to allow them to be controlled by said common program.

Abstract: Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed.

Abstract: A computer program execution record and replay system providing recorded execution event breakpoints is described. In one embodiment, for example, in the record and replay system, a method for providing recorded execution event breakpoints, the method comprising: recording information about one or more execution events that occur during a recorded execution of a computer program; during a replay execution of the computer program in which a particular execution event of the one or more execution events is faithfully reproduced, determining whether a breakpoint is to be set in the replay execution of the computer program based on the recorded information about the particular execution event; and if the breakpoint is to be set, then setting a breakpoint in the replay execution of the computer program such that the replay execution breaks at a point corresponding to the faithful reproduction of the particular execution event.

Abstract: A system, method and computer program product are provided. In use, code is executed in user mode. Further, the execution of the code is intercepted. In response to the interception, operations are performed in kernel mode.

Abstract: Implementations of systems, methods and apparatus include aspects of resource conservation strategies that may be useful for a USB compliant device that experiences resource limitations over durations longer than contemplated by the USB standards. Implementations of systems, methods and apparatus disclosed herein enable a USB compliant device to selectively process interrupts and/or other overhead resulting from USB communications between a host and the device. By not processing some interrupts and/or other overhead, based in part on the current level of resource utilization, a device can free up resources needed to process relatively high data-rate incoming traffic from the host. In some implementations, when locally implemented techniques prove to be insufficient, the device may optionally request that the host reduce the data-rate on the downlink.

Abstract: Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities.

Abstract: A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor unit is specified and receiving an interrupt signal and an interrupt control circuit receiving the interrupt request signal from each of the plurality of processor units and transmitting the interrupt signal to each of the plurality of processor units, wherein, the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is not in a low power consumption state and transmits the interrupt signal to another processor unit different from the processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is in the low power consumption state.

Abstract: Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

Abstract: In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of a processor on which the task has been scheduled, reassigning the task to a coldest idle core of the processor, and sending the task to the coldest idle core and maintaining the processor in a turbo mode. Other embodiments are described and claimed.

Abstract: An audio-video (AV) playback chain and rendering peripheral device 300 for generating two or more interrupts 306, 308 with a programmable delay 304 between them. Such are configured to prevent two processors 310, 314 from racing to access the same system resources in their respective interrupt service routines.

Abstract: A processor receives interrupts of a same type from hardware. The processor determines a rate at which the interrupts are being received. The processor compares the rate at which the interrupts are being received to a threshold rate. In response to determining that the rate at which the interrupts are being received is greater than the threshold rate, the processor sends just the first received interrupt to firmware for processing. All other of the interrupts are not sent from the processor to the firmware but instead are suppressed by the processor. By comparison, in response to determining that the rate at which the interrupts are being received is less than the threshold rate, the processor can send all the interrupts from the processor to firmware for processing.

Abstract: In a computer system, a method of controlling coalescence of interrupts includes dynamically basing a current level of interrupt coalescing upon a determination of outstanding input/output (I/O) commands for which corresponding I/O completions have not been received. Deliveries of interrupts are executed on the basis of the current level and in an absence of enabling timing-triggered delivery of an interrupt.

Abstract: Generally, this disclosure describes systems (and methods) for moderating interrupts in a virtualization environment. An overflow interrupt interval is defined. The overflow interrupt interval is used for triggering activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used.

Abstract: One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used.

Abstract: The latency of virtual interrupt delivery in virtual machines is reduced by normalizing and exposing the virtual interrupt routing information of each VM to a privileged domain such as the VMkernel in an organized manner to enable virtual interrupt delivery that minimizes the number of VCPU hops. A computer implemented method of processing the virtual I/O request comprises receiving the virtual I/O request, responsive to completing a physical I/O corresponding to the virtual I/O request, referring to a virtual CPU set including information on a destination virtual CPU designated by the guest operating system for handling a virtual interrupt corresponding to the virtual I/O request, and generating the virtual interrupt corresponding to the virtual I/O request to the destination virtual CPU determined by referring to the virtual CPU set.

Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model, The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.

Abstract: A communication processing apparatus (101) includes: a MAC unit (106) receiving a packet; a classification unit (107) classifying the received packet; a transfer control unit (104) transferring data of the classified packet to a main memory (102); a first memory (112m) storing an interrupt management table (112); an interrupt control unit (111) specifying, with reference to the interrupt management table (112), an interrupt control method associated with the classification of the packet classified by the classification unit (107) and outputting an interrupt signal to a CPU (103) using the specified interrupt control method; and a setting unit (110) registering the classification and the interrupt control method into the interrupt management table (112) according to instructions from an application program activated in the CPU (103) so as to update the interrupt management table (112).

Abstract: A method and an apparatus for controlling an interrupt in a portable terminal are provided. The method includes executing an application based on user's control, determining whether an event occurs during the application execution, displaying information representing the event occurrence on a screen while continuing the application execution, and determining whether to interrupt the application by the event based on user's control.

Abstract: Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

Abstract: A computing apparatus determines that a virtual processor of a guest has been moved from a first physical processor of a host to a second physical processor of the host. The computing apparatus identifies a device that is controlled by the virtual processor, wherein device interrupts for the device are forwarded to the virtual processor. The computing apparatus updates at least one of the device or an interrupt controller to cause at least one of the device or the interrupt controller to send the device interrupts to the second physical processor of the host, wherein the second physical processor of the host forwards the device interrupts to the virtual processor running on the second physical processor without generating an inter-processor interrupt.

Abstract: A computing apparatus identifies that a first physical processor of a host has forwarded information regarding a device interrupt for a device to a second physical processor executing at least one of a virtual processor that controls the device or an application thread that controls the device. After identifying that the first physical processor has forwarded the information regarding the device interrupt to the second physical processor and in response to determining that one or more update criteria have been satisfied, the computing apparatus updates at least one of the device or an interrupt controller to cause at least one of the device or the interrupt controller to send future device interrupts for the device to the second physical processor.

Abstract: An information processing device in which interrupts are generated when some events are occurred. The information processing device includes: an interrupt generating unit to generate an interrupt; an interrupt control unit to receive the generated interrupt, count an interrupt reception count per unit time, notify of the interrupt and delay, if the counted interrupt reception count per unit time exceeds a predetermined value, the interrupt notification; and an interrupt processing unit to process the notified interrupt.

Abstract: A concurrent grouping operation for execution on a multiple core processor is provided. The grouping operation is provided with a sequence or set of elements. In one phase, each worker receives a partition of a sequence of elements to be grouped. The elements of each partition are arranged into a data structure, which includes one or more keys where each key corresponds to a value list of one or more of the received elements associated with that key. In another phase, the data structures created by each worker are merged so that the keys and corresponding elements for the entire sequence of elements exist in one data structure. Recursive merging can be completed in a constant time, which is not proportional to the length of the sequence.

Abstract: Methods, computer-readable media, and systems for interrupt handling in Java™ are provided. In some illustrative embodiments, a method for interrupt handling in Java software that executes on a processor comprising creating a Java representation of an interrupt vector table, instantiating a first Java object comprising a first Java method for handling an interrupt, inserting a reference to the first Java object in the Java representation of the interrupt vector table at a location corresponding to a level of the interrupt, and updating a location in the system level interrupt vector table corresponding to the level of the interrupt using the contents of the location in the Java representation.

Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.

Abstract: A network terminal includes an operating system on which a plurality of user environments can run in parallel, a plurality of calling units corresponding to the plurality of user environments respectively, and a plurality of cooperative units corresponding to the plurality of user environments respectively. Priorities different from one another is assigned to the plurality of user environments respectively. Each calling unit is configured to convert a first telephone signal received from an interface and a second telephone signal received from an IP telephone terminal so that an IP telephone communication is performed between the interface device and the IP telephone terminal. Each cooperative unit is configured to communicate the interface with the corresponding calling unit in response to a calling request received from the IP telephone terminal.

Abstract: An anti-virus system for enforcing a virus monitoring and scanning process, the anti-virus and firewall system comprises a master CPU card, a plurality of slave CPU cards and a programmable logic. The master CPU card is used for controlling the virus monitoring and scanning process and dividing the virus monitoring and scanning process into a plurality of sub-processes. The plurality of slave CPU cards are controlled by the master CPU card in a software level and a hardware level, each of the plurality of slave CPU cards receives and processes one of the plurality of sub-processes then sends back to the master CPU card. The programmable logic controlled by the master CPU card for monitoring and controlling said plurality of slave CPU cards at a hardware level.

Abstract: A method includes delivering a user-level interrupt message indicative of a user-level interrupt to one or more recipients according to a user-level interrupt delivery configuration selected from a plurality of user-level interrupt delivery configurations. The one or more recipients correspond to one or more application threads executing on one or more processor cores of a plurality of processor cores in a multi-core system. A method includes generating an indicator of a user-level interrupt being undeliverable to one or more intended recipients of a user-level interrupt message according to a failed delivery notification mode configuration. The user-level interrupt may be issued by an application thread executing on a first processor core of a plurality of processor cores in a multi-core system.

Abstract: Various technologies and techniques are disclosed that provide fast context switching. One embodiment provides a method for a context switch comprising preloading a host virtual machine context in a first portion of a processor, operating a guest virtual machine in a second portion of the processor, writing parameters of the host virtual machine context to a memory location shared by the host virtual machine and the guest virtual machine, and operating the host virtual machine in the processor. In this manner, a fast context switch may be accomplished by preloading the new context in a virtual processor, thus reducing the delay to switch to the new context.