Abstract: A data transfer system includes: a processor; a main memory that is connected to the processor; a peripheral controller that is connected to the processor; and a peripheral device that is connected to the peripheral controller and includes a register set, wherein the peripheral device transfers data stored in the register set to a predetermined memory region of the main memory or the processor by a DMA (Direct Memory Access) transfer, and the processor reads out the data transferred to the memory region by the DMA transfer without accessing to the peripheral device.

Abstract: A virtualization processing method and apparatuses, and a computer system are provided. Where a computing node includes: a hardware layer, a Host running on the hardware layer, and at least one virtual machine (VM) running on the Host, the hardware layer includes an I/O device, several corresponding virtual function (VF) devices are virtualized from the I/O device, the Host has several VF software instances, the several VF software instances and the several VF devices are in one-to-one correspondence; the Host further has a back-end instance (BE) of an I/O virtual device having the same type with the I/O device, the VM has a front-end instance (FE) of the I/O virtual device; the BE in the Host is bound with an idle VF software instance. The solutions of the embodiments of the present invention are beneficial to optimization of the performance and compatibility of a virtualization system.

Abstract: A method and system for managing direct memory access (DMA) in a computer system that hosts virtual machines and allows memory overcommit. The computer receives an indication that a bus address is to be used by a device to perform DMA to a buffer. In response to the indication, the computer determines a host device identifier for the device, and pins a memory page addressed by a host address that is associated with the bus address and a guest address. The computer also records, in a host I/O memory management unit (IOMMU), a mapping of the bus address and the host device identifier to the host address. After the device completes the DMA, the computer removes the mapping from the host IOMMU to prevent further direct access to the host address.

Abstract: A method includes generating, by a first software process of the data processing system, a source partition descriptor for a DMA job which requires access to a first partition of a memory which is assigned to a second software process of the data processing system and not assigned to the first software process. The source partition descriptor comprises a partition identifier which identifies the first partition of the memory. The DMA unit receives the source partition descriptor and generates a destination partition descriptor for the DMA job. Generating the destination partition descriptor includes translating, by the DMA unit, the partition identifier to a buffer pool identifier which identifies a physical address within the first partition of the memory which is assigned to the second software process; and storing, by the DMA unit, the buffer pool identifier in the destination partition descriptor.

Abstract: APIs discussed herein promote efficient and timely interoperability between hardware and software components within the media processing pipelines of media content players. A PhysMemDataStructure API facilitates a hardware component's direct access to information within a memory used by a software component, to enable the hardware component to use direct memory access techniques to obtain the contents of the memory, instead of using processor cycles to execute copy commands. The PhysMemDataStructure API exposes one or more fields of data structures associated with units of media content stored in a memory used by a software component, and the exposed fields store information about the physical properties of the memory locations of the units of media content. SyncHelper APIs are used for obtaining information from, and passing information to, hardware components, which information is used to adjust the hardware components' timing for preparing media samples of synchronously-presentable media content streams.

Abstract: A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.

Abstract: Methods and apparatus are provided for managing interrupts within a virtualizable communication device. Through virtualization, one port of the device may be able to support multiple hosts (e.g., computers) and multiple functions operating on each host. Any number of interrupt resources may be allocated to the supported functions, and may include receive/transmit DMAs, receive/transmit mailboxes, errors, and so on. Resources may migrate from one function to another, such as when a function requests additional resources. Each function's set of allocated resources is isolated from other functions' resources so that their interrupts may be managed and reported in a non-blocking manner. If an interrupt cannot be immediately reported to a destination host/function, the interrupt may be delayed, retried, cancelled or otherwise handled in a way that avoids blocking interrupts to other hosts and functions.

Abstract: A method for dynamic buffering of disk I/O command chains for a computer system. The method includes receiving a plurality of disk I/O command chains from at least one thread executing on a processor of the computer system. A respective plurality of pointers for the disk I/O command chains are stored in a buffer of a disk controller. The disk I/O command chains are accessed for execution by the disk controller by serially accessing the pointers in the buffer.

Abstract: There is provided an image scanning apparatus including a setting section which sets an image generation condition based on the attribute value of the existing image data stored in the image file; a generator section which scans the manuscript to generate the scanned image data based on the image generation condition set by the setting section; and a storing section which adds the scanned image data generated by the generator section into the image file to store the added image file.

Abstract: An I/O controller and method are provided. The I/O controller to which an I/O device can be connected, and instructs the I/O device to execute a process includes a descriptor transfer device that transfers a descriptor indicating contents of a process to be executed, and execution instruction unit that instructs the I/O device to execute the process, based on the descriptor transferred from the descriptor transfer device, wherein the descriptor transfer device includes a memory for storing the descriptor; descriptor reading unit that reads, according to an indication regarding a descriptor read source from a processor, an indicated descriptor from a main memory or said memory which stores the descriptor, and descriptor transfer unit that transfers the read descriptor to the execution instruction unit.

Abstract: An information processing apparatus includes a plurality of processors configured to form a pipeline, a plurality of communication units configured to transfer communication data between a processor in an upstream stage of the pipeline and another processor in a downstream stage and to temporarily store the communication data output from the processor in the upstream stage to the processor in the downstream stage into an internal FIFO buffer, and a memory configured to be accessible from each of the processors and each of the communication units.

Abstract: System for controlling data transfer between a host system and storage devices. A virtualization controller implements the data transfer and includes first ports for connection with the storage devices, a second port for connection with the host system, a processor, and a memory configured to store volume mapping information which correlates first identification information used by the host system to access a first storage area in one of the storage devices, with second identification information for identifying the first storage area, the correlation being used by the processor to access the first storage area. When data stored in the first storage area is transferred to a second storage area, the processor correlates the first identification information with a third identification information for identifying the second storage area and registers the first identification information and the third identification information in the volume mapping information.

Abstract: A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

Abstract: Techniques presented herein provide approaches for out-of-band host management via a management controller. In one embodiment, the management controller provides an application programming interface (API) specifying one or more functions for managing one or more applications executing on a host computer. The one or more functions may be invoked by a requesting entity.

Abstract: An augmented reality system and method for diagnosing and fixing a fault in a device. A mobile communication device can be operatively connected with a networked rendering device by reading a two-dimensional bar code associated with the rendering device. An image with respect to the rendering device can be captured by an image-capturing unit associated with the mobile communication device. The image can be augmented with additional information and a target area can be highlighted in order to indicate a fault component. An action to be taken with respect to the target area can be displayed on the mobile communication device. Such an approach permits an end user to address the device issue with increased quality of information and accuracy.

Abstract: Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer.

Abstract: A storage controller manages address conversion information denoting the correspondence relationship between a logical address and a physical address of storage area (for example, a physical block) inside a flash memory. The storage controller uses the above-mentioned address conversion information to specify a physical address corresponding to a logical address specified by an I/O request from a higher-level device, and sends an I/O command including I/O-destination information based on the specified physical address to a memory controller inside a flash memory module. The memory controller carries out the I/O with respect to a storage area inside a flash memory specified from the I/O-destination information of the I/O command from the storage controller.

Abstract: An integrated circuit (IC) card may include non-volatile memory portions, where external data files are storable, and including volatile memory portions and a microprocessor. The IC card further may include a serial interface that stores the external data file as received into the volatile memory portions, and at least an internal register that is programmable through the serial interface. The internal register manages according to the programming a serial storing into the non-volatile portions of the external data file already stored into the volatile memory portions. The serial interface and the internal register may manage the respective programming in a parallel manner.

Abstract: A system and method for clients, a control module, and storage modules to participate in a unified address space in order to and read and write data efficiently using direct-memory access. The method for reading data includes determining a first location in a first memory to write a first copy of the data, a second location in a second memory to write a second copy of the data, where the first memory is located in a first storage module including a first persistent storage and the second memory is located in a second storage module including a second persistent storage. The method further includes programming a direct memory access engine to read the data from client memory and issue a first write request to a multicast address, where the first location, the second location, and a third location are associated with the multicast address.

Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Abstract: Techniques described herein provide for sending and receiving messages. The messages are associated with streams. Indicators associated with the streams determine if the messages are sent.

Abstract: An information processing device collects status information for a large number of input and output devices simultaneously. A bridge circuit having a multicast function connects an information processing unit with a plurality of input and output devices. By setting the multicast to the bridge circuit, the bridge circuit forwards a packet which instructs a copy of the status information to the plurality of input and output devices by multicast, and a DMA circuit in the plurality of input and output devices simultaneously starts DMA transfer of the status information to the processing unit.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: A method and system for accessing a computer system memory without processor intervention is disclosed. In one embodiment, the method includes initiating a predetermined communication protocol between a first device and a second device, the first device including a first processor, a first memory and a first communication interface, the second device including a second processor, a second memory and a second communication interface. The predetermined communication protocol enables an access operation to be performed on the first or second memory without intervention by the first or second processor. In one embodiment, the predetermined communication protocol utilizes a plurality of predefined packet types which are identified by a packet header decoder.

Abstract: In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

Abstract: A scatter gather cache system and method are provided, which increase performance of scatter-gather DMA operations by reducing the time taken by the DMA engine to perform a logical to physical address translation. This is done primarily by two-dimensional caching of scatter-gather elements of selected scatter-gather lists using a novel indexing, line swapping and replacement methodology. The cache can also include a context victim table (CVT) for storing scatter-gather list contexts from evicted cache entries and also allows for pre-fetching of SGL elements from Scatter-Gather Lists (SGL). It also provides coherency support when there are multiple instances of the cache accessing the same memory space.

Abstract: Machine implemented method and system is provided. The method includes sending a packet to a device by a computing system; determining an address for the packet, where an interface logic for the device determines the address; updating a location associated with the address; where the interface logic for the device updates the location; updating a bitmap value associated with the location to indicate to a processor for the device that a location associated with the address has been updated; where the interface logic updates the bitmap value; clearing the bitmap value by writing a same value that is read by the processor for the device; and processing the packet received by the device.

Abstract: An input/output (I/O) device includes a memory buffer and off-loading hardware. The off-loading hardware is configured to accept from a host a scatter/gather list including one or more entries. The entries include at least a pattern-type entry that specifies a period of a periodic pattern of addresses that are to be accessed in a memory of the host. The off-loading hardware is configured to transfer data between the memory buffer of the I/O device and the memory of the host by accessing the addresses in the memory of the host in accordance with the periodic pattern at intervals indicated in the period.

Abstract: A method for performing direct memory access includes obtaining, by a application executing on a host, a kernel address space identifier of a first driver kernel memory. The application sends the kernel address space identifier to a second device driver. The second device driver obtains, using the kernel address space identifier, a cookie structure binding the first driver kernel memory to a second device driver address space for the first driver kernel memory. The application sends a request for a direct memory access operation. The request includes a location identifier of a location storing a data object in the first driver kernel memory. Based on the cookie structure, the second device driver performs, using the location identifier, the direct memory access operation to transfer the data object from the first driver kernel memory to a second driver kernel memory.

Abstract: An information processing apparatus, an execution control method, an execution control program, and an execution control medium storing the execution control program are described. The information processing apparatus has a processor, which concurrently performs: (1) initializing hardware resources needed for execution of the information processing apparatus; and (2) expanding an operating system and a file system image stored in a nonvolatile memory in a compressed format and transferring the expanded operating system and file system image to a volatile memory using a direct memory access controller.

Abstract: The present system enables an input/output (I/O) device to request memory for performing a direct memory access (DMA) of system memory. Further, the system uses an input/output memory management unit (IOMMU) to determine whether or not the system memory is available. The IOMMU notifies an operating system associated with the system memory if the system memory is not available, such that the operating system allocates non-system memory for use by the I/O device to perform the DMA.

Abstract: A method includes generating, by a first software process of the data processing system, a source partition descriptor for a DMA job which requires access to a first partition of a memory which is assigned to a second software process of the data processing system and not assigned to the first software process. The source partition descriptor comprises a partition identifier which identifies the first partition of the memory. The DMA unit receives the source partition descriptor and generates a destination partition descriptor for the DMA job. Generating the destination partition descriptor includes translating, by the DMA unit, the partition identifier to a buffer pool identifier which identifies a physical address within the first partition of the memory which is assigned to the second software process; and storing, by the DMA unit, the buffer pool identifier in the destination partition descriptor.

Abstract: An electronic device with improved flash memory compatibility and a method corresponding thereto are disclosed. The electronic device has a NAND flash, a processing unit and a program memory. The program memory stores application software and codes of an operating system, to be retrieved and executed by the processing unit. The application software requests for NAND flash access in accordance with a specific page size. The operating system acts as an intermediary between the application software and the NAND flash and provides a device driver which allocates a number of physical pages of the NAND flash to each virtual page of the specific page size for responding to NAND flash access requests from the application software by referring to the virtual pages.

Abstract: A Small Computer System Interface (SCSI) transport for fabric backplane enterprise servers provides for local and remote communication of storage system information between storage sub-system elements of an ES system and other elements of an ES system via a storage interface. The transport includes encapsulation of information for communication via a reliable transport implemented in part across a cellifying switch fabric. The transport may optionally include communication via Ethernet frames over any of a local network or the Internet. Remote Direct Memory Access (RDMA) and Direct Data Placement (DDP) protocols are used to communicate the information (commands, responses, and data) between SCSI initiator and target end-points. A Fibre Channel Module (FCM) may be operated as a SCSI target providing a storage interface to any of a Processor Memory Module (PMM), a System Control Module (SCM), and an OffLoad Module (OLM) operated as a SCSI initiator.

Abstract: Provided is a Direct Memory Access (DMA) controller which provides a function of searching for a specific pattern from data being transmitted during DMA transmission. The DMA controller stores at least one pattern value. The DMA controller compares data being transmitted to a pattern value while transmitting the data using a DMA method, and generates, in response to data matching the pattern value being detected, a signal indicating that the data matching the pattern value has been detected. The DMA controller stores an address of the data matching the pattern value in response to the generated signal.

Abstract: Device for real-time streaming to an array of solid state memory device sets, said device comprising receiving means for receiving data from data streams of individual data rate in parallel, an input cache for buffering received data, a bus system for transferring data from the input buffer to the solid state memory device sets, and a controller adapted for using a page-receiving-time t_r, a page-writing-time wrt_tm, the data amount p and the individual data rates for dynamically controlling the bus system such that data received from the first data stream is transferred to solid state memory device sets comprised in a first subset of said array of solid state memory device sets, only, and data received from the at least a second data stream is transferred to solid state memory device sets comprised in a different second subset of said array of solid state memory device sets, only.

Abstract: A method that includes creating a DMA group, adding a first I/O device to the DMA group, and adding a second I/O device to the DMA group. The method further includes instructing an I/O MMU to create a shared virtual DMA address, mapping a memory location to the shared virtual DMA address in the DMA group translation table, and providing the shared virtual DMA address to the device drivers. The method further includes determining that the first I/O device has received DMA group data, instructing a first DMA controller to transfer the DMA group data from the first I/O device to the shared virtual DMA address, determining that the shared virtual DMA address has received the DMA group data, and instructing a second DMA controller to transfer the DMA group data from the memory location corresponding to the shared virtual DMA address to the second I/O device.

Abstract: A system and method for clients, a control module, and storage modules to participate in a unified address space in order to and read and write data efficiently using direct-memory access. The method for reading data includes determining a first location in a first memory to write a first copy of the data, a second location in a second memory to write a second copy of the data, where the first memory is located in a first storage module including a first persistent storage and the second memory is located in a second storage module including a second persistent storage. The method further includes programming a direct memory access engine to read the data from client memory and issue a first write request to a multicast address, where the first location, the second location, and a third location are associated with the multicast address.

Abstract: The present invention is a system for implementing a meta-disk aggregation model for storage controllers. The system includes a storage controller configured for communicatively coupling with a server. The system further includes a meta-disk drive group having a plurality of disk drives, the meta-disk drive group configured for being communicatively coupled with the storage controller, each of the plurality of disk drives including a drive interface connector. Additionally, each drive interface connector of the plurality of disk drives of the meta-disk drive group is configured for being communicatively coupled to each of the remaining drive interface connectors of the plurality of disk drives, thereby allowing the plurality of disk drives to communicate as a single device with the storage controller.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: A data transfer control device that selects one of a plurality of DMA channels and transfers data to or from memory includes a request holding section configured to hold a certain number of data transfer requests of the plurality of DMA channels and a request rearranging section configured to select and rearrange the data transfer requests that are held in a basic transfer order so that the data transfer requests of each of the plurality of DMA channels are successively outputted for a number of successive transfers set in advance.

Abstract: An information processing device collects status information for a large number of input and output devices simultaneously. A bridge circuit having a multicast function connects an information processing unit with a plurality of input and output devices. By setting the multicast to the bridge circuit, the bridge circuit forwards a packet which instructs a copy of the status information to the plurality of input and output devices by multicast, and a DMA circuit in the plurality of input and output devices simultaneously starts DMA transfer of the status information to the processing unit.

Abstract: A memory access control apparatus receives from a DMA requestor an access request command, which contains an IOID, for a DMA address space that is a memory area used for a DMA transfer, and determines whether the access is permitted or not and executes the access if it is permitted. The operating system on the PU sets in MMU the correspondence relationship between the logical address space of a user process and the DMA address space. When the user process instructs to access the DMA address space by specifying a logical address, the MMU translates the logical address into a physical address of the DMA address space.

Abstract: Users of a computer are prevented from directly accessing certain hardware for which a driver is installed on the computer. The users are provided a limited, indirect manner to access the hardware for a specific purpose or to do a specific job. One example of such hardware is a wireless hardware communication interface. The wireless activity of the computer may be restricted so that the wireless hardware communication interface is prevented from communicating with any devices compatible with the wireless hardware communication interface other than one or more specific devices.

Abstract: The present invention enables the transparent bridging of an audio controller over a network between a host PC and a remote user interface system by providing a host module that presents the interface of an audio controller to a system bus of a host computer and a remote module that presents an audio link interface to codecs in a remote system. By bridging the controller at these interfaces, the effects of network delays and data loss can be controlled inside the user's human perception limits without introducing signal timing problems at the two specified interfaces.

Abstract: Techniques are disclosed relating to detecting and interjecting a programmed input/output (PIO) operation into a direct memory access (DMA) operation. In one embodiment, an integrated circuit may include a DMA controller that may contain a control circuit, a DMA unit, and a PIO unit. The control circuit may be configured to detect a pending PIO operation during a DMA operation and interject the PIO operation onto a shared path during the same clock cycle as or the first clock cycle following the detection of the pending PIO operation. The DMA operation may consist of multiple single-clock-cycle beats. In one embodiment, a PIO operation may be interjected onto the shared path between beats of a DMA operation, on consecutive clock cycles. At the next clock cycle following the PIO operation, the control circuit may resume the next beat of the DMA operation.

Abstract: A memory card, connected to a host, includes a NAND flash memory and a memory controller. The NAND flash memory includes multiple pages, and each page includes multiple sectors. The memory controller receives sector data and a corresponding sector address from the host. The memory controller enables the sector data to be transferred to the NAND flash memory over a first data bus, via a buffer memory, when the sector address is an address for accessing a first sector in a selected page. The memory controller enables the sector data to be transferred to the NAND flash memory over a second data bus, bypassing the buffer memory, when the sector address is an address for accessing a sector other than the first sector in the selected page.

Abstract: A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.

Abstract: A method, system and program are provided for dynamically allocating DMA channel identifiers by virtualizing DMA transfer requests into available DMA channel identifiers using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once an input value associated with the DMA transfer request is mapped to the selected DMA channel identifier, the DMA transfer is performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfer. When there is a request to wait for completion of the data transfer, the same input value is used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.