Using Addressing Patents (Class 710/26)
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Publication number: 20120226831Abstract: Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.Type: ApplicationFiled: May 14, 2012Publication date: September 6, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Ik Jae CHUN, Chun Gi Lyuh, Se Wan Heo, Sang Hun Yoon, Tae Moon Roh, Jong Kee Kwon, Jong Dae Kim
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Patent number: 8260980Abstract: Disclosed is a method that simultaneously transfers DMA data from a peripheral device to a hardware assist function and processor memory. A first DMA transfer is configured to transfer data from the peripheral to a peripheral DMA engine. While receiving the data, the DMA engine simultaneously transfers this data to processor memory. The DMA engine also transfers a copy of the data to a hardware assist function. The DMA engine may also simultaneously transfer data from processor memory to a peripheral device while transferring a copy to a hardware assist function.Type: GrantFiled: June 10, 2009Date of Patent: September 4, 2012Assignee: LSI CorporationInventors: Bret S. Weber, Timothy E. Hoglund, Mohamad El-Batal
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Patent number: 8260981Abstract: A direct memory access controller including: a transfer module that transfers data from several data sources to at least one addressee for these data, through several buffer memories each including a predetermined number of successive elementary memory locations; a read management module that reads data stored in the buffer memories and that transfers them in sequence to the addressee; and a storage module that stores read pointers associated respectively with each buffer memory, each read pointer indicating an elementary location of the buffer memory with which it is associated and in which data can be read, wherein the buffer memories are associated respectively with each data source, and for each buffer memory, the controller includes means for executing a firmware that reads data and updates a read pointer associated with this buffer memory, and for synchronising execution of the firmwares as a function of a predetermined order of data originating from buffer memories required in a data sequence to be traType: GrantFiled: September 24, 2010Date of Patent: September 4, 2012Assignee: Commissariat a l'énergie atomique et aux énergies alternativesInventors: Yves Durand, Christian Bernard
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Patent number: 8250254Abstract: In one embodiment, the present invention includes a method for receiving a request for a direct memory access (DMA) operation in an input/output (I/O) hub, where the request includes a device virtual address (DVA) associated with the DMA operation, determining in the I/O hub whether to perform an address translation to translate the DVA into a physical address (PA), and sending the request with the DVA from the I/O hub to a processor coupled to the I/O hub if the I/O hub determines not to perform the address translation. Other embodiments are described and claimed.Type: GrantFiled: July 31, 2007Date of Patent: August 21, 2012Assignee: Intel CorporationInventor: Ramakrishna Saripalli
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Patent number: 8230133Abstract: A microcomputer has: a CPU; memory; a direct memory access controller which controls access to the above memory without passing through the CPU; a plurality of peripheral resources, each having prescribed functions corresponding to a given real resource number, and issuing an access request to the direct memory access controller to perform data transfer with the memory; and, a resource conversion unit, which performs signal conversion between the direct memory access controller and the plurality of peripheral resources. A portion of the peripheral resources among the plurality of peripheral resources are associated with logical resource numbers of the direct memory access controller by the resource conversion unit.Type: GrantFiled: January 18, 2005Date of Patent: July 24, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Minoru Usui
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Patent number: 8214554Abstract: In one cycle for transferring data, a controller forming a data transfer circuit stores pointer information P_A for periodic transfer and pointer information P_B for non-periodic transfer read from a memory respectively in first and second storage areas. The controller sequentially transfers, to a communication bus, data D_A for periodic transfer and data D_B for non-periodic transfer read from the memory by referring to the P_A and P_B. If transfer by a data length indicated in the P_B has not been completed upon the transfer of the D_B, the controller updates the data length to a data length of the remaining data, and updates an address indicated in the P_B to an address on the memory of the remaining data. In the next cycle for transferring data, the controller reads the remaining data from the memory by referring to the P_B, and transfers the remaining data to the communication bus.Type: GrantFiled: February 24, 2011Date of Patent: July 3, 2012Assignee: Renesas Electronics CorporationInventors: Keisuke Nomura, Tomokazu Kondo, Yousuke Sasaki
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Patent number: 8209446Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: GrantFiled: August 30, 2011Date of Patent: June 26, 2012Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
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Publication number: 20120159015Abstract: Disclosed is an operating method of a direct memory access (DMA) controller having first and second DMA channels. The operating method includes iteratively performing a DMA transfer operation of the first DMA channel based upon loop information and transfer information of the first DMA channel; iteratively performing a DMA transfer operation of the second DMA channel based upon loop information and transfer information of the second DMA channel; reconfiguring the transfer and loop information of the first and second DMA channels; and again performing the iteratively performing a DMA transfer operation of the first DMA channel and the iteratively performing a DMA transfer operation of the first DMA channel based upon the reconfigured transfer and loop information of the first and second DMA channels.Type: ApplicationFiled: September 23, 2011Publication date: June 21, 2012Applicant: Electronic and Telecommunications Research InstituteInventors: Ik Jae Chun, Chun-Gi Lyuh, Jung Hee Suk, Sanghun Yoon, Tae Moon Roh
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Publication number: 20120151104Abstract: Techniques are disclosed relating to detecting and interjecting a programmed input/output (PIO) operation into a direct memory access (DMA) operation. In one embodiment, an integrated circuit may include a DMA controller that may contain a control circuit, a DMA unit, and a PIO unit. The control circuit may be configured to detect a pending PIO operation during a DMA operation and interject the PIO operation onto a shared path during the same clock cycle as or the first clock cycle following the detection of the pending PIO operation. The DMA operation may consist of multiple single-clock-cycle beats. In one embodiment, a PIO operation may be interjected onto the shared path between beats of a DMA operation, on consecutive clock cycles. At the next clock cycle following the PIO operation, the control circuit may resume the next beat of the DMA operation.Type: ApplicationFiled: December 13, 2010Publication date: June 14, 2012Inventors: Joseph P. Bratt, Lakshmi Rao
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Patent number: 8176252Abstract: A scatter gather element based caching system is provided along with a modified scatter gather element, that supports efficient logical to physical address translation for arbitrarily aligned and arbitrarily sized fragment (segment) based memory management schemes. This is different from modern CPU implementations with MMUs that support page-based implementations. A primary application of embodiments of the present invention is in DMA applications. The system enables frequent switching of contexts between I/Os using a novel caching technique. An embodiment of the present invention also includes the modification of the conventional scatter-gather element used in DMA for supporting multiple memory spaces, backward list traversals, better error recovery and debugging.Type: GrantFiled: September 3, 2008Date of Patent: May 8, 2012Assignee: PMC-Sierra US, Inc.Inventors: Praveen Alexander, Heng Liao
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Patent number: 8156277Abstract: A storage controller manages address conversion information denoting the correspondence relationship between a logical address and a physical address of storage area (for example, a physical block) inside a flash memory. The storage controller uses the above-mentioned address conversion information to specify a physical address corresponding to a logical address specified by an I/O request from a higher-level device, and sends an I/O command including I/O-destination information based on the specified physical address to a memory controller inside a flash memory module. The memory controller carries out the I/O with respect to a storage area inside a flash memory specified from the I/O-destination information of the I/O command from the storage controller.Type: GrantFiled: July 7, 2008Date of Patent: April 10, 2012Assignee: Hitachi, LtdInventor: Jun Kitahara
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Patent number: 8151013Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.Type: GrantFiled: February 15, 2011Date of Patent: April 3, 2012Assignee: Hitachi, Ltd.Inventors: Kazuyoshi Serizawa, Yasutomo Yamamoto, Norio Shimozono, Akira Deguchi, Hisaharu Takeuchi, Takao Sato, Hisao Homma
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Publication number: 20120079141Abstract: An information processing apparatus includes a plurality of processors configured to form a pipeline, a plurality of communication units configured to transfer communication data between a processor in an upstream stage of the pipeline and another processor in a downstream stage and to temporarily store the communication data output from the processor in the upstream stage to the processor in the downstream stage into an internal FIFO buffer, and a memory configured to be accessible from each of the processors and each of the communication units.Type: ApplicationFiled: September 23, 2011Publication date: March 29, 2012Applicant: CANON KABUSHIKI KAISHAInventor: Toru Ushiku
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Publication number: 20120072619Abstract: A method and system for managing direct memory access (DMA) in a computer system that hosts virtual machines and allows memory overcommit. The computer receives an indication that a bus address is to be used by a device to perform DMA to a buffer. In response to the indication, the computer determines a host device identifier for the device, and pins a memory page addressed by a host address that is associated with the bus address and a guest address. The computer also records, in a host I/O memory management unit (IOMMU), a mapping of the bus address and the host device identifier to the host address. After the device completes the DMA, the computer removes the mapping from the host IOMMU to prevent further direct access to the host address.Type: ApplicationFiled: September 16, 2010Publication date: March 22, 2012Applicant: RED HAT ISRAEL, LTD.Inventors: Michael Tsirkin, Christopher M. Wright
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Publication number: 20120066416Abstract: An information processing apparatus, an execution control method, an execution control program, and an execution control medium storing the execution control program are described. The information processing apparatus has a processor, which concurrently performs: (1) initializing hardware resources needed for execution of the information processing apparatus; and (2) expanding an operating system and a file system image stored in a nonvolatile memory in a compressed format and transferring the expanded operating system and file system image to a volatile memory using a direct memory access controller.Type: ApplicationFiled: September 8, 2011Publication date: March 15, 2012Applicant: Ricoh Company, LimitedInventor: Fumiyuki Yoshida
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Patent number: 8135923Abstract: In a method for enabling a root device to access a plurality of memory locations in an address space in an endpoint device, a first access is sent to the endpoint device by transmitting a first header and a first address. The header includes a continue bit that is set at a first state that indicates that the first access is accessing a selected first memory location that the address is being sent. A first memory location is accessed when the continue bit is in the first state. A second access, which accesses accessing a second memory location that is contiguous to an immediately previously accessed memory location, is sent to the endpoint device by transmitting a header that includes a continue bit set to a second state and not sending an address. The second memory location corresponds to the first address plus a predetermined address offset.Type: GrantFiled: April 26, 2007Date of Patent: March 13, 2012Assignee: International Business Machines CorporationInventors: Ryan S. Haraden, Adalberto G. Yanes
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Publication number: 20120054380Abstract: Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.Type: ApplicationFiled: November 8, 2011Publication date: March 1, 2012Inventors: David J. Harriman, Andrew F. Glew
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Patent number: 8103809Abstract: A method, computer readable medium, and a system for communicating with networked clients and servers through a network device includes establishing a plurality of direct memory access (DMA) channels across a host system bus over which a plurality of executing applications each having a respective application driver communicate with a network through a network device configured to receive and transmit network data packets. At a first port in the network device, a first network data packet destined for an executing application is received. A first DMA channel over which to transmit the first network data packet towards the destined executing application is identified, and the first network data packet is transmitted to the destination executing application over the designated DMA channel mapping to the first port.Type: GrantFiled: January 19, 2010Date of Patent: January 24, 2012Assignee: F5 Networks, Inc.Inventors: Timothy Michels, William R. Baumann
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Patent number: 8090790Abstract: Aspects of a system for splicing RDMA transactions in an RDMA system may include a main processor within a main server that may receive read requests from a client device. The main processor may translate a data reference contained in each read request to generate a physical buffer list (PBL). The processor 206 may communicate the PBL to a local processor within a NIC. The local processor may utilize the PBL perform RDMA operations to retrieve data stripes contained in one or more DDP segments received from a plurality of auxiliary servers. The local processor may enable the generation of TCP packets each containing the data stripes, which may then be sent to the client. The retrieval of DDP segments and generation of TCP packets may occur within the NIC without transferring retrieved data stripes via a system bus within the main server.Type: GrantFiled: November 16, 2007Date of Patent: January 3, 2012Assignee: Broadcom CorporationInventor: Caitlin Bestler
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Publication number: 20110314186Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: ApplicationFiled: August 30, 2011Publication date: December 22, 2011Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
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Patent number: 8078771Abstract: A system for sending large Command Descriptor Block (CDB) structures in a serial attached SCSI (SAS) controller includes a CDB Transmit Block, a CDB Memory, a Context Memory, a Direct Memory Access (DMA) Queue, a Transmit DMA Engine, and a SAS Interface. The CDB Transmit Block receives one or more Message Frames. If the CDB is small (32 bytes or less), the CDB Transmit Block reads data from the Message Frame and transmits a SAS Command Frame over the SAS interface. If the CDB is large (33 bytes or more), the CDB Transmit Block places a large CDB entry into the DMA Queue. The Transmit DMA Engine receives the large CDB entry from the DMA queue, utilizes an address pointer from the Message Frame to the CDB Memory to fetch large CDB information into a DMA buffer, and transmits a SAS Command Frame over the SAS interface.Type: GrantFiled: December 5, 2008Date of Patent: December 13, 2011Assignee: LSI CorporationInventors: Brian A. Day, Ajay Dawra, Parameshwar A. Kadekodi
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Patent number: 8073990Abstract: A method and apparatus for transferring data from a first to a second memory of a computer system. The method comprises (i) initializing a descriptor with a description of physical addressing of a first section of a first array of the first memory; (ii) updating a mask associated with the descriptor with an indication for transferring data from a first sub-section of the first section to the second memory, the mask and the data managed by an application on a first virtual machine of the computer system, the application isolated from the physical addressing of the first section; (iii) responsive to the updated mask, (a) determining physical addresses of the first sub-section based on the description, and (b), transferring the data from the first sub-section to the second memory; and (iv) clearing at least a portion of the updated mask to indicate completion of transferring the data.Type: GrantFiled: September 23, 2009Date of Patent: December 6, 2011Assignee: Teradici CorporationInventors: Charles Peter Baron, Daniel Jean Donat Doucette, Paul Andrew Helter, Bradley Reginald Quinton
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Patent number: 8055805Abstract: Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.Type: GrantFiled: March 31, 2009Date of Patent: November 8, 2011Assignee: Intel CorporationInventors: David J. Harriman, Andrew F. Glew
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Patent number: 8041849Abstract: The present invention is a method for handling an operation system kernel-provided command via a software-based device driver. The method includes receiving the operation system kernel-provided command from an operation system kernel. The method further includes determining if a kernel virtual address is required for responding to the command. The method further includes initiating a Direct Memory Access (DMA) operation for providing data to the operating system kernel in response to the command when a kernel virtual address is not required for responding to the command. The method further includes allocating a device driver buffer with a DMA address and a virtual address when a kernel virtual address is required for responding to the command.Type: GrantFiled: July 2, 2008Date of Patent: October 18, 2011Assignee: LSI CorporationInventors: Atul Mukker, Sreenivas Bagalkote, Jose K. Manoj
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Patent number: 8037215Abstract: Apparatus for evaluating the performance of DMA-based algorithmic tasks on a target multi-core processing system includes a memory and at least one processor coupled to the memory. The processor is operative: to input a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; to evaluate performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and to provide results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.Type: GrantFiled: May 30, 2008Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: John A. Gunnels, Shakti Kapoor, Ravi Kothari, Yogish Sabharwal, James C. Sexton
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Patent number: 8032686Abstract: A data storage system includes an input/output server and a storage unit. The input/output server includes a processor, memory, and a host channel adapter. The storage unit includes a processor, memory, and a storage module. The storage module includes a storage controller, and an interface block for connecting the storage module to a corresponding memory-mapped interface. The storage unit further includes a host channel adaptor. The storage unit host channel adapter is connected to a corresponding memory-mapped interface. The storage unit host channel adapter is capable of remote direct memory access to the input/output server. Protocol translation logic is configured to intercept a memory access request from the storage controller, and initiate a corresponding remote direct memory access to the input/output server through the storage unit host channel adapter and the input/output server host channel adapter.Type: GrantFiled: April 30, 2009Date of Patent: October 4, 2011Assignee: Oracle America, Inc.Inventors: John Timothy O'Brien, George F. DeTar, Jr.
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Publication number: 20110225325Abstract: In one cycle for transferring data, a controller forming a data transfer circuit stores pointer information P_A for periodic transfer and pointer information P_B for non-periodic transfer read from a memory respectively in first and second storage areas. The controller sequentially transfers, to a communication bus, data D_A for periodic transfer and data D_B for non-periodic transfer read from the memory by referring to the P_A and P_B. If transfer by a data length indicated in the P_B has not been completed upon the transfer of the D_B, the controller updates the data length to a data length of the remaining data, and updates an address indicated in the P_B to an address on the memory of the remaining data. In the next cycle for transferring data, the controller reads the remaining data from the memory by referring to the P_B, and transfers the remaining data to the communication bus.Type: ApplicationFiled: February 24, 2011Publication date: September 15, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Keisuke NOMURA, Tomokazu KONDO, Yousuke SASAKI
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Patent number: 8001297Abstract: Systems and methods for intermediate buffering of data for the purpose of controlling its delivery to the consumer. The systems and methods for buffering data can arbitrate between the incoming data flow from the generating component and the outgoing data flow to the consumer. In doing so, the systems and methods for buffering of data seek to honor the delivery demands and/or constraints of the consumer, while avoiding the loss of the data generated by the producer. The delivery demands of the consumer may include requirements pertaining to maximum acceptable incoming data rate, the desired incoming data rate, incoming data aggregation, the desired freshness of the data, and tolerance for event loss. The generation component constraints may include the space limitations on buffering data within the data buffer.Type: GrantFiled: April 25, 2005Date of Patent: August 16, 2011Assignee: Microsoft CorporationInventors: Michael D. Volodarsky, Patrick Yu-Kwan Ng
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Patent number: 7984252Abstract: A controller including an interface module and an index module. The interface module is configured to connect devices. The index module is configured to include, in a table stored in memory, an entry for each of the devices. Each entry includes an address field. The index module is configured to: receive a frame of data including an address of one of the devices; compare the address to the address fields associated with the entries in the table; in response to the address matching one of the address fields, access an index value identifying an entry of the table when the address matches one of the address fields; and in response to the address not matching one of the address fields, generate the index value. The index value is used to connect the device associated with the matching one of the address fields with the one of the devices.Type: GrantFiled: July 9, 2010Date of Patent: July 19, 2011Assignee: Marvell International Ltd.Inventors: Leon A. Krantz, Kha Nguyen, Michael J. North
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Patent number: 7979601Abstract: An embedded controller capable of providing direct memory access (DMA) to memory for a host. The controller may include a processor, a memory medium, and an interface coupled to the memory medium. The interface may be configured to couple to a host and receive a DMA request. The DMA request may include a request to read data from a memory location in the memory medium or a request to write data to a memory location in the memory medium. The DMA request may include a relative memory address. The interface may be configured to translate the relative memory address into a first address of the memory medium. Accordingly, the interface may perform operations according to the DMA request using the first address of the memory medium. The processor may be configured to operate according to data stored in the memory medium.Type: GrantFiled: August 5, 2008Date of Patent: July 12, 2011Assignee: Standard Microsystems CorporationInventors: Alan D. Berenbaum, Eileen M. Marando
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Patent number: 7970961Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: GrantFiled: November 11, 2008Date of Patent: June 28, 2011Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Publication number: 20110153878Abstract: Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.Type: ApplicationFiled: September 14, 2010Publication date: June 23, 2011Applicant: Electronics and Telecommunications Research InstituteInventors: Ik Jae CHUN, Chun Gi Lyuh, Se Wan Heo, Sang Hun Yoon, Tae Moon Roh, Jong Kee Kwon, Jong Dae Kim
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Publication number: 20110153873Abstract: A method and a device for the detection of erroneous or inopportune transactions of any entity of a microprocessor or microcontroller includes programming counters internal or external to the microcontroller, which is configured to count the number of transactions in the target area of the target interface of the microcontroller; count the total number of transactions on the target interface, and verify that the number of transactions outside of the target area of the target interface of the microcontroller is zero. Equality between the number of transactions in the target area of the target interface and the total number of transactions on the target interface of the microcontroller is verified.Type: ApplicationFiled: December 21, 2010Publication date: June 23, 2011Applicant: THALESInventors: Sébastien CAMAND, Tarik AEGERTER
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Publication number: 20110153877Abstract: Techniques for performing direct memory access (“DMA”) in an architecture wherein an interconnect separates I/O means from a DMA engine for handling DMA requests of the I/O means. In an embodiment, the I/O means sends via the interconnect a DMA request including an address-non-specific identifier of a queue which is a target of the DMA request. In another embodiment, the DMA engine determines an address-specific identifier of a location in the queue in response to the sending of the DMA request.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Inventor: Steven R. King
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Patent number: 7966432Abstract: A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data.Type: GrantFiled: July 19, 2005Date of Patent: June 21, 2011Assignee: ST—Ericsson SAInventors: Patrick Fulcheri, Francois Chancel
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Publication number: 20110138086Abstract: Provided is a Direct Memory Access (DMA) controller which provides a function of searching for a specific pattern from data being transmitted during DMA transmission. The DMA controller stores at least one pattern value. The DMA controller compares data being transmitted to a pattern value while transmitting the data using a DMA method, and generates, in response to data matching the pattern value being detected, a signal indicating that the data matching the pattern value has been detected. The DMA controller stores an address of the data matching the pattern value in response to the generated signal.Type: ApplicationFiled: November 17, 2010Publication date: June 9, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-Seok KWON, Jae-Un Park, Suk-Jin Kim
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Publication number: 20110125936Abstract: A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no load on the CPU(s) of the receiving processing node is disclosed. The data channel has a defined frame structure with one or more data structures, wherein each data structure comprises a plurality of data locations. A receiver selects data from a fixed data location in each data structure as a data descriptor for each respective data structure. The receiver configures a direct memory access (DMA) function using each data descriptor.Type: ApplicationFiled: January 27, 2011Publication date: May 26, 2011Inventors: Philippe Malleth, Sebastien Tomas, Mario Giani, Francois Badaud
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Patent number: 7937447Abstract: Methods and apparatus are provided for improving communication between processors in separate computer systems. Components and peripherals in individual computer systems communicate using input/output (I/O) buses such as PCI Express buses. The I/O buses are extended to allow interconnection between computer systems without having to introduce network infrastructure. A transfer controller supporting Direct Memory Access (DMA) is provided to allow even more efficient communication between computer systems.Type: GrantFiled: March 21, 2005Date of Patent: May 3, 2011Assignee: Xsigo SystemsInventors: Ariel Cohen, Shreyas Shah, Raymond Lim, Greg Lockwood
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Patent number: 7934043Abstract: A data processing apparatus contains a first bus connected to a first memory, a first central processing unit (CPU) being accessible to the first memory via the first bus, a first Direct Memory Access (DMA) controller being accessible to the first memory via the first bus, and a monitor circuit connected to the first bus and monitoring addresses transferred on the first bus. The addresses transferred on the first bus are transmitted from the first DMA controller to the first memory via the first bus. The monitor circuit compares the address transferred on the first bus with a preset monitor target address. The CPU acquires the comparison results by the monitor circuit. If the comparison results show an address match, then the CPU accesses the first memory. The CPU can in this way access the first memory at a correct timing.Type: GrantFiled: August 6, 2007Date of Patent: April 26, 2011Assignee: Renesas Electronics CorporationInventor: Kenichi Takeda
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Patent number: 7934025Abstract: A Content-Terminated Direct Memory Access (CT-DMA) circuit autonomously transfers data of an unknown length from a source to a destination, terminating the transfer based on the content of the data. Filter criteria are provided to the CT-DMA prior to the data transfer. The filter criteria include pattern data that are compared to transfer data, and transfer termination rules for interpreting the comparison results. Data are written to the destination until the filter criteria are met. Representative filter criteria may include that one or more units of transfer data match pattern data; that one or more units of transfer data fail to match pattern data; or that one or more units of transfer data match pattern data a predetermined number of times.Type: GrantFiled: January 24, 2007Date of Patent: April 26, 2011Assignee: QUALCOMM IncorporatedInventors: Kevin Allen Sapp, James Norris Dieffenderfer
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Patent number: 7930445Abstract: To improve throughput in data transfer in a remote I/O system, this invention provides a computer system including: a host computer; a device which communicates with the host computer; and a network which connects the host computer and the device, in which the device is coupled to the network via a device bridge including a bridge memory, and the host computer includes a host memory and a device driver. The device driver writes, when at least one of data and an address is written in the host memory, in the bridge memory the at least one of the data and address stored through the writing in the host memory; and sends a data transfer request to the device bridge, and the device bridge reads, upon reception of the data transfer request, an address from a predetermined area; and reads data from an area that is indicated by the read address.Type: GrantFiled: September 5, 2007Date of Patent: April 19, 2011Assignee: Hitachi, Ltd.Inventors: Jun Okitsu, Yoshiko Yasuda, Takashige Baba
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Patent number: 7929539Abstract: A method for controlling access by processes running on a host device to a communication network includes assigning to each of the processes a respective doorbell address on a network interface adapter that couples the host device to the network and allocating instances of a communication service on the network, to be provided via the adapter, to the processes. Upon receiving a request submitted by a given one of the processes to its respective doorbell address to access one of the allocated service instances, the adapter conveys the data over the network using the specified instance of the service, subject to verifying, based on the doorbell address to which the request was submitted, that the specified instance was allocated to the given process.Type: GrantFiled: January 27, 2009Date of Patent: April 19, 2011Assignee: Mellanox Technologies Ltd.Inventors: Michael Kagan, Gil Bloch, Diego A. Crupnicoff, Margarita Schnitman, Dafna Levenvirth
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Publication number: 20110087808Abstract: This direct access memory controller (10, 20) is programmed to transfer data from several data sources (121, . . . , 12i, . . . , 12n) to at least one addressee (14) for these data, through several buffer memories (161, . . . , 16i, . . . , 16n). It comprises a read management module (30) designed to read data stored in the buffer memories (161, . . . , 16i, . . . , 16n) and to transfer them in sequence to the addressee (14) and read pointers (PL1, PL2) storage means (38) associated respectively with each buffer memory respectively. For each buffer memory (161, . . . , 16i, . . . , 16n), the controller (10, 20) comprises means of executing a firmware (401, . . . , 40i, . . . , 40n) to read data and update the read pointer associated with this buffer memory, and it comprises means (30, 401, . . . , 40i, . . . , 40n) of synchronising execution of the firmwares as a function of a predetermined order of data originating from buffer memories required in the data sequence to be transferred to the addressee.Type: ApplicationFiled: September 24, 2010Publication date: April 14, 2011Applicant: COMMISSAR. A L'ENERG. ATOM. ET AUX ENERG. ALTERN.Inventors: Yves DURAND, Christian Bernard
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Patent number: 7917597Abstract: An embodiment of the invention provides an apparatus and method for performing RDMA (Remote Direct Memory Access) network configuration. The apparatus and method measure a performance of each RDMA operation for different data message sizes and determine an RDMA operation to be applied for a particular packet size sent by an application, based on the measured performance. As an example, the RDMA operations are, e.g., RDMA send/receive, RDMA write, RDMA read, memory registration and memory un-registration, or memory bind and memory unbind. The measured performance can be, for example, the total time to perform an RDMA operation for different packet sizes.Type: GrantFiled: November 2, 2006Date of Patent: March 29, 2011Assignee: NetApp, Inc.Inventor: James Lentini
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Patent number: 7912998Abstract: Methods and systems for performing direct memory access (DMA) transfers are described. An invalidate queue (or other storage device) contains an entry associated with a DMA transfer in progress. If the invalidate queue detects an invalidation of a memory page associated with that entry, then it is marked invalid. If the entry is marked invalid during the DMA transfer, then that DMA transfer is aborted. This enables, among other things, DMA transfers to unpinned virtual memory.Type: GrantFiled: January 6, 2006Date of Patent: March 22, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael Steven Schlansker, Erwin Oertli, Jean-Francois Collard
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Patent number: 7899909Abstract: A method, system, and program product for reserving resources in a networked environment, e.g. a storage area network. A resource is some object that a user must use or change to complete a task. When a user plans a task, the user selects some high-level resources and properties to reserve and a Reservation Service embodiment creates reservations for them. Accordingly, the method system and program product embodiments overcome inefficiencies in reserving resources in a data storage environment while still allowing such reservations to occur. The method includes reserving portions of properties for resources from more than one available choice.Type: GrantFiled: June 27, 2007Date of Patent: March 1, 2011Assignee: EMC CorporationInventors: Richard T. Simon, Andrew S. Becher, David Ohsie
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Patent number: 7899957Abstract: A memory controller, such as a SDRAM controller, controls the way in which data is retrieved, in order to make more efficient use of the bandwidth of the memory data bus. More specifically, when a memory access request requires multiple data bursts on the memory bus, the SDRAM controller stores the data from the multiple data bursts in respective buffers. Data is then retrieved from the buffers such that data is read from a part of the first buffer, then from the other buffers, and finally from the remaining part of the first buffer. Storing the required data in the remaining part of the first buffer avoids the need to occupy the memory bus with a new data burst.Type: GrantFiled: December 30, 2003Date of Patent: March 1, 2011Assignee: Altera CorporationInventor: Kulwinder Dhanoa
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Patent number: 7890669Abstract: Provided is a computer system in which an I/O card is shared among physical servers and logical servers. Servers are set in advance such that one I/O card is used exclusively by one physical or logical server, or shared among a plurality of servers. An I/O hub allocates a virtual MM I/O address unique to each physical or logical server to a physical MM I/O address associated with each I/O card. The I/O hub keeps allocation information indicating the relation between the allocated virtual MM I/O address, the physical MM I/O address, and a server identifier unique to each physical or logical server. When a request to access an I/O card is sent from a physical or logical server, the allocation information is referred to and a server identifier is extracted from the access request. The extracted server identifier is used to identify the physical or logical server that has made the access request.Type: GrantFiled: November 20, 2006Date of Patent: February 15, 2011Assignee: Hitachi, Ltd.Inventors: Keitaro Uehara, Yuji Tsushima, Toshiomi Moriki, Yoshiko Yasuda
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Patent number: 7877524Abstract: A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.Type: GrantFiled: November 24, 2008Date of Patent: January 25, 2011Assignee: PMC-Sierra US, Inc.Inventors: Babysaroja Annem, Heng Liao, Zhongzhi Liu, Praveen Alexander
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Patent number: 7865631Abstract: A method, system and program are provided for dynamically allocating DMA channel identifiers to multiple DMA transfer requests that are grouped in time by virtualizing DMA transfer requests into an available DMA channel identifier using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once the input values associated with the DMA transfer requests are mapped to the selected DMA channel identifier, the DMA transfers are performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfers. When there is a request to wait for completion of the data transfers, the same input values are used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.Type: GrantFiled: December 6, 2007Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Joaquin Madruga, Dean J. Burdick