Abstract: A memory allocation method for a direct memory access controller (DMAC) in a limited-memory-size computer system includes the steps of allocating a memory space having continuous memory addresses to form a buffer of the DMAC; dividing the memory space successively into a plurality of first memory blocks and a second memory block, wherein the size of the second memory block is equal to a maximum frame size possibly accessed by the DMAC; and assigning the plurality of first memory blocks and the second memory block to a plurality of descriptors in order, wherein each of the plurality of descriptors is utilized for recording a memory address of a corresponding memory block as a pointers for the corresponding memory block.

Abstract: An operational circuit for performing an operation of an arbitrary number of input data pieces by using a DMA transfer according to a descriptor control and output results. The arbitrary number of input data pieces are divided into a plurality of pieces to perform an operation processing without performing the operation of the arbitrary number of input data pieces at a time. The operational circuit once stores an intermediate result for each of the divided operations in an external storage device, performs an operation processing read with an intermediate result in the next operation processing, and obtains a final result by repeating these operation processings. The operation is performed at a cyclic unit of processing corresponding to the number of address registers provided in the operational circuit.

Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a control register configured to store a base address of a set of translation tables and control logic coupled to the control register. The control logic is configured to respond to an input/output (I/O) device-initiated request having an address within an address range of an address space corresponding to a peripheral interconnect. One or more operations other than a memory operation are associated with the address range, and the control logic is configured to translate the address to a second address outside of the address range if the translation tables specify a translation from the address to the second address, whereby a memory operation is performed in response to the request instead of the one or more operations associated with the address range.

Abstract: In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

Abstract: A system and method of transferring data of unknown length in a computer system includes providing an embedded device having a processing apparatus and a DMA engine, the processing apparatus processing the data and the DMA engine transferring the data from the embedded device to a component in the computer system, determining whether information from the embedded device is an address value or a data value, programming the DMA engine with the address value if the information is the address value, and transferring the data value to the address value in the component if the information is the data value.

Abstract: An IO adapter for guaranteeing the data transfer bandwidth on each capsule interface when multiple capsule interfaces jointly share the DMA engine of the IO adapter. An IO driver containing a capsule interface information table including bandwidth information and for setting the forming status of a pair of capsule interfaces and, during data transfer subdivides the descriptors for the capsule interfaces into multiple groups for each data buffer size satisfying the preset bandwidth information and, copies one group at each fixed sample time set by the descriptor registration means, into the descriptor ring and performs DMA transfer. To control this copy information, the IO driver contains a ring scheduler information table for managing the number of descriptor entries for the capsule interface cycle time and, a ring scheduler cancel means for renewing the entries in the ring scheduler information table each time one transmission of the descriptor group ends.

Abstract: A software process receives a command initiating creation of a zone naming policy for automatically generating zone names in a storage area network. During creation of a zone naming policy, the software process receives selection of one or more format elements to be used in the zone naming policy. The one or more format elements each identify which corresponding at least one type of characteristic associated with a given zone in the storage area network shall be used to automatically generate a respective zone name for the given zone. For example, the format elements in a zone policy may identify how to generate a respective zone name using identifiers associated with resources associated with the zone. Accordingly, a network manager can create a zone naming policy for automatically generating zone names in a storage area network rather than having to manually create zone names for each created zone.

Abstract: A method of dynamic data transfer width adjustment is provided. The method includes firstly detects a data size of a transfer data. A data transfer width mode is detected according to a data address of transferring data. The data transfer width mode includes at least one of a word mode, a half-word mode, and a byte mode. According to the data address, the data transfer width mode, and the data size, the data is transferred.

Abstract: A direct memory access (DMA) transfer apparatus configured to sequentially read, into a register, at least one transfer setting value for data transfer stored in a memory and to perform DMA transfer processing based on the read transfer setting value includes a unit configured to receive a No Operation (NOP) designation for designating no performance of DMA transfer as the transfer setting value, and a unit configured to generate, if the NOP designation has been performed with the transfer setting value read into the register, an NOP interrupt signal to end transfer processing without performing the DMA transfer.

Abstract: A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.

Abstract: A direct access memory system includes n (n>1) memory arrays (1.1 to 1.n), a address decoder (2), a data connecting circuit (3), and a write controlling circuit (4). The address decoder (2) includes a binary decoder (5), and n-1 selectors (6.1 to 6.n1). The direct access memory system has an address bus (01) for lead in address A, k (k>1), input/output data buses (02.1 to 02.k) for data transmission, and a control bus (03) for lead in write control signals. The data is stored by bytes, each data byte D being addressable by one address A. After the address A has been set on the address bus (01), in memory arrays (1.1 to 1.n) the memory locations are activated in which the data bytes DA, DA+1, . . . , DA+k?1 are stored. The data connecting circuit (3) connects the data interfaces of the memory arrays (1.1 to 1.n) with the data buses (02.1 to 02.k) so that the first data bus (02.1) transmits the data byte DA, and simultaneously the second data bus (02.2) transmits the data byte DA+1, . . .

Abstract: A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page.

Abstract: The present invention relates to a microcontroller including a central processing unit, at least one memory, a bus coupling the storage location to the central processing unit, and a data modification module for modifying data in the at least one memory. The data modification module includes a first interface being coupled to the bus for transferring data to the at least one memory over the bus, and a second interface being adapted to be coupled to an external device for receiving the data, wherein the data modification module is adapted to operate as a bus master and to transfer data received from the external device over the bus to the at least one memory.

Abstract: A method of transmitting data between storage virtualization controllers (SVCs) in a computer system is disclosed, in which there is an inter-controller communication channel (ICC) between the storage virtualization controllers. The method comprises the steps of: a central processing unit (CPU) of one storage virtualization controller (SVC) sending a data transfer request to an interface that establishes the ICC when the CPU needs to transmit information to the other SVC; and transmitting the information to the other SVC after the interface that establishes the ICC receives the data transfer request, and obtains the information.

Abstract: Method and system for processing packets received from a network is provided. The system includes an adapter having a processing module that separates a header of a network packet from data, forwards the header to a host system and stores data associated with the network packet in a memory device of the network adapter. The host system processes the header and determines a destination for the network packet data. The method includes determining header boundary in a network packet, wherein an adapter coupled to a host system determines the header boundary; ending header information to the host system; and storing data associated with the network packet in a memory device of the adapter.

Abstract: A method and system for transferring data between a host and a Serial Attached Small Computer Interface (“SAS”) device using a storage controller is provided. The storage controller includes, a World Wide Name (“WWN”) module that includes a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, an input/output counter value that tracks plural commands for a connection. A WWN index value represents the address of a row having plural entries. The method includes, comparing frame elements of incoming frames, including a unique WWN address with the WWN module entries; and if there is a match, updating a counter value for a connection between the storage controller and a device sending frames. The counter value is increased when a command frame is received and decreased when a command is executed and a response is sent to the device.

Abstract: A dual or triple access interface (e.g., hardware and software implementation) allows a CPU and at least one DMA peripheral, e.g., Universal Serial Bus (USB) DMA engine, to transfer data in and/or out of a common single port SRAM by negotiating access requests between the CPU and the DMA peripheral, and then subsequently forms memory cycles to the single port SRAM to satisfy both the CPU's and DMA peripheral's memory access throughput requirements. This allows the CPU and the at least one DMA peripheral to access a shared single port SRAM by time multiplexing granted accesses between, for example, two or three simultaneous memory access requests, thus eliminating the need for a dual port memory.

Abstract: A network device for processing packets. The network device includes a CPU processing module for transmitting information between at least one memory location on the network device and an external CPU memory location. The CPU processing module includes a first engine for performing bulk transfer of information from the at least one memory location on the network device to the external CPU memory location, wherein all entries of the at least one memory location on the network device are transferred to the external CPU memory location, and a second engine for performing bulk transfer of information from the external CPU memory location to at least one memory location on the switching chip, wherein a plurality of entries from the external CPU memory location is transferred to the memory locations on the switching chip. The second engine uses a bit received from a CPU to determine how entries will be added in the at least one memory location on the switching chip.

Abstract: An apparatus for performing downlink or uplink processing in a wireless communication system to maintain efficiency of system bandwidth includes at least one sharing-ring buffer, a MAC-PHY interface, a security engine, and a DMA processor. The sharing-ring buffer is for storing multi-format data. In a situation where the apparatus performs downlink processing, the MAC-PHY interface is for receiving input data, the security engine is for retrieving stored data from the sharing-ring buffer and decrypting the retrieved data, and the DMA processor is for accessing the sharing-ring buffer to obtain the decrypted data. In a situation where the apparatus performs uplink processing, the DMA processor is for receiving input data and storing the input data into the sharing-ring buffer, the security engine is for retrieving the stored data from the sharing-ring buffer and encrypting the retrieved data, and the MAC-PHY interface is for receiving the encrypted data from the sharing-ring buffer.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: An apparatus includes a virtual memory manager that moves data from a first block to second block in memory. When the virtual memory manager is ready to transfer data from the first block to the second block, a third, temporary block of memory is defined. The translation table in a DMA controller is changed to point DMA transfers that target the first block to instead target the temporary block. The virtual memory manager then transfers data from the first block to the second block. When the transfer is complete, a check is made to see if the DMA transferred data to the temporary block while the data from the first block was being written to the second block. If so, the data written to the temporary block is written to the second block. A hardware register is preferably used to efficiently detect changes to the temporary block.

Abstract: A direct memory access controller has a data register for transferring data from a source to a destination address. A pattern register is provided and a data comparator is coupled with the data register and the pattern register for comparing the content of the data register with the content of the pattern register. A control unit coupled with the comparator controls the data flow and stops a data transfer if the comparator detects a match of the data register and the pattern register.

Abstract: A method, device and system for storing data in a cache in case of power failure are disclosed. The method includes: in case of power failure of a storage system, receiving configuration information from a central processing unit (CPU); establishing a mapping relationship between an address of data in the cache and an address in a storage device according to the configuration information; sending a signaling message that carries the mapping relationship to the cache, so that the cache migrates the data to the storage device according to the signaling message.

Abstract: In a communication system having a master-slave arrangement communicating with each other using the RS485 protocol, an FPGA with a buffer memory is provided in the master and slave, respectively, to handle the actual communication. The CPUs of the master and slave transfer data to and from the respective buffer memory. The master's FPGA initiates and maintains communication with the slave's FPGA. The masters FPGA and the slave's FPGA communicate with each other using the RS485 protocol by transmitting requests, acknowledgements and data. From the standpoint of the CPUs of the master and slave, the communication appears to be full duplex, although the actual communication between the FPGAs is half duplex. One particular application of the communication method is a KVM switch system where the KVM switch acts as the master and the computers connected to the KVM switch act as slaves.

Abstract: A method and apparatus is described herein for supporting direct memory accesses between peer I/O devices. It is determined whether a guest physical address (GPA) referenced by an access generated from an I/O device, is within a range of GPAs associated with local I/O devices based at least in part on a GPA base and a GPA window size. If the GPA is within the window, then the GPA is translated to an HPA based at least in part on a base HPA associated with a local device and then forwarded to that local device. However, if the GPA is not within the window, then the access is forwarded upstream.

Abstract: An apparatus and method related to performing Remote Direct Memory Access Request (“RDMA”) is presented. In one embodiment, the apparatus comprises Remote direct memory access (“RDMA”) logic that executes a direct memory access (“DMA”) request from the remote peer. The apparatus further comprising a protection checking logic to verify a key and a target address in the DMA request and conversion logic to convert the target address to an input/output virtual address (“IOVA”) if the conversion is required. The IOVA is to be translated to the host physical address by an address translation unit at another hardware subsystem.

Abstract: Available buffers in the memory space of a guest operating system of a virtual machine are provided to a network interface controller (NIC) for use during direct memory access (DMA) and the guest operating system is notified accordingly when data is written into such available buffers. These capabilities obviate the requirement of using hypervisor memory as a staging area to determine which virtual machine to forward incoming data.

Abstract: A system control device comprises a system LSI section having a plurality of functional blocks, a system control microcomputer section for controlling the control register of each of the functional blocks, an address decoding section for decoding an access address to a predetermined byte in a control register which the system control microcomputer section attempts to access, and issuing an access control signal to the whole of a single control register including the predetermined byte, an access control section for changing the access control signal to the whole of the single control register to an access control signal to the predetermined bytes of the plurality of control registers included in the system LSI section, with respect to access to an address to the predetermined byte, and an access mode control register for indicating whether or not the changing by the access control section is to be performed.

Abstract: An embedded controller capable of providing direct memory access (DMA) to memory for a host. The controller may include a processor, a memory medium, and an interface coupled to the memory medium. The interface may be configured to couple to a host and receive a DMA request. The DMA request may include a request to read data from a memory location in the memory medium or a request to write data to a memory location in the memory medium. The DMA request may include a relative memory address. The interface may be configured to translate the relative memory address into a first address of the memory medium. Accordingly, the interface may perform operations according to the DMA request using the first address of the memory medium. The processor may be configured to operate according to data stored in the memory medium.

Abstract: A system is disclosed that comprises a processor, a memoryless first level page table addressable by the processor, and a second level page table stored in a memory coupled to the processor. The second level page table is addressable by at least one entry of the first level page table.

Abstract: The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software running on the processor generates cache management commands. The DMA mechanism carries out the commands, thereby enabling the software program management of the caches. The commands include commands for writing data to the cache, loading data from the cache, and for marking data in the cache as no longer needed. The cache can be a system cache or a DMA cache.

Abstract: A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller; and forming the source or destination address by combining the partial address with selected bits from a source register within the direct memory access controller.

Abstract: In a DMA control method in which a DMA controller transfers data in memory to an input/output device in accordance with the control information which is provided by a processing device to a DMA controller, a processing device implements a step in which the processing device sets an information block comprising the control information and the data in the memory; a step in which address information of the information block is provided by the processing device to the DMA controller; a step in which the DMA controller reads the information block from the memory based on the address information and extracts the control information; and a step in which the DMA controller transfers the data in the information block to the I/O device based on the control information.

Abstract: A method and system for memory address translation and pinning are provided. The method includes attaching a memory address space identifier to a direct memory access (DMA) request, the DMA request is sent by a consumer and using a virtual address in a given address space. The method further includes looking up for the memory address space identifier to find a translation of the virtual address in the given address space used in the DMA request to a physical page frame. Provided that the physical page frame is found, pinning the physical page frame al song as the DMA request is in progress to prevent an unmapping operation of said virtual address in said given address space, and completing the DMA request, wherein the steps of attaching, looking up and pinning are centrally controlled by a host gateway.

Abstract: A system and method for using a direct memory access (“DMA”) channel to reorganize data during transfer from one device to another are disclosed herein. A DMA channel includes demultiplexing logic and multiplexing logic. The demultiplexing logic is configurable to distribute each data value read into the DMA channel to a different one of a plurality of data streams than an immediately preceding value. The multiplexing logic is configurable to select a given one of the plurality of data streams. The DMA channel is configurable to write a value from the given data stream to a storage location external to the DMA channel.

Abstract: The serial communication device capable of reducing the load on the CPU is provided for a system using the serial communications such as the car navigation system. The attention is focused on the control method of the serial communication, in which a DMA controller is used for the data reception in the serial communication, and a number larger than the number of data received at a time is set in advance as the number of transfers of the receive DMA controller, and further, the function to generate the timeout interrupt when data is not received for a certain period is added to the serial interface, so that the serial communication can be controlled and performed without applying the load on the CPU.

Abstract: A computer system according to an example of the invention comprises SPEs and a global memory. The SPEs include a running SPE and an idling SPE. The running SPE and the idling SPE each have a processor core, local memory and DMA module. The local memory of the idling SPE stores data stored in the global memory and used by the processor core of the running SPE, before the data is used by the processor core of the running SPE. The DMA module of the running SPE reads the data from the local memory of the idling SPE, and transfers the data to the processor core of the running SPE.

Abstract: A video multiviewer system may include a video input/output (I/O) controller, a system memory, and a graphics processing unit (GPU) comprising a GPU memory. The system may further include a central processing unit (CPU) for operating the video I/O controller to transfer video data to the GPU memory via direct memory access (DMA) without being stored in the system memory, and a display for displaying multiple video windows based upon video data in the GPU memory.

Abstract: DMAC includes current transfer setting registers and next transfer setting registers. Each of the current transfer setting registers stores transfer source address, transfer destination address and transfer count. The next transfer setting registers stores a transfer setting of a DMA transfer carried out after completing a DMA transfer according to a current transfer setting stored in the current transfer setting registers as a next transfer setting. Further, flags are provided for controlling to write to each of the next transfer setting registers.

Abstract: A data transfer device for storing only transfer data for which updating is necessary in the storage unit of a transfer source, transferring the transfer data by a transfer control unit, temporarily storing the transfer data in a register provided in a transfer destination circuit, transferring the transfer data stored in the register to the discontinuous storage area of the transfer destination circuit according to the map information of a map register, and transferring data for which updating is necessary to the transfer destination circuit.

Abstract: A system for tracking using electronic addresses is disclosed. The system stores an identification code, an electronic address, and a counter. The electronic address is made up of either single values or pairs of single values. A pair of single values for at least one of value of the counter is made up of a pseudonumber and a unique address value. The pseudonumber is able to be disentangled to produce a second pair of single values for a different value of the counter, thereby producing a tracking history.

Abstract: A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base subaddress. In response to a first instruction of a user program that includes a virtual address, the virtual address is translated into a corresponding physical address, and the physical address is stored in a buffer register that is inaccessible to the user program. In response to a second instruction of the user program, the physical address stored in the buffer register is applied to the data bus and a first word including high-order bits indicating the base subaddress is applied to the address bus. The source or destination register is selected according to the first word applied to the address bus and the physical address applied to the data bus is stored in the selected register.

Abstract: The image processing apparatus (data processing apparatus) stores data in a storing unit (storing means), inputs and outputs the data to and from the storing unit via a storage control unit (input-output means) and processes the data outputted from the storing unit with a control unit (processing means). The storage control unit inputs and outputs image data to and from the storing unit by the DMA method through a path via a DMA control unit and inputs and outputs other data such as a control instruction to and from the storing unit by the PIO method through a path via a PIO control unit. Image data to be inputted and outputted to and from the storing unit by the DMA method is encrypted in an input operation and decrypted in an output operation by an encryption/decryption unit provided on the input-output path for DMA method.

Abstract: A control machine which uses a data amount stored in an FIFO as a trigger and allows a DMA transfer to be started according to a capacity of the FIFO allows a control machine for preparing for the DMA transfer to start to prepare a command and the like for the DMA transfer. The control machine for preparing for the DMA transfer issues the prepared command to a control machine for transferring DMA data, so that a process according to the command is started. At the time of the DMA transfer, a burden on a host CPU is reduced.

Abstract: A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. Recently retrieved clusters are stored in an on-chip cache, and a cached cluster can be used to translate any virtual address in its range without accessing the address translation table again.

Abstract: An inkjet print control apparatus connected with a processor and a memory through a bus. The memory stores print image data. The inkjet print control apparatus fetches the print image data stored in the memory for further data operation in order to drive one or more inkjet heads. The inkjet print control apparatus includes a DMA controller, an instruction RAM and a capture processor. The instruction RAM stores a capture instruction for the print image data fetched. The capture processor is connected to the instruction RAM and the DMA controller for computing an address accessed by the DMA controller to the memory according to the capture instruction. The DMA controller accesses the print image data according to the address.

Abstract: A DMA transfer control device includes a setting register group for setting transfer informations, a number-of-transfers register to which the number of transfers to be performed is set, and which updates a value thereof every time one DMA transfer is completed, a transfer control unit, a secondary setting register group for setting other transfer informations different from the transfer informations, and a specified ordinal-number-of-transfer register. Every time one DMA transfer is initiated, either a value of the setting register group or a value of the secondary setting register group is selected for each of the transfer informations in accordance with a result of an arithmetic operation between a value of the number-of-transfers register and a value of the specified ordinal-number-of-transfer register, and inputted to the transfer control unit. As a result, by making settings for one DMA transfer, it is possible to temporarily change the transfer informations.

Abstract: A data transfer controlling device is mounted in an IC card having: a communication device for data communication with an external device; a memory device for storing data received from and transmitted to the external device; and an operation processing device for controlling the memory device and the communication device, and controls a data transfer process. The controlling device comprises: a status information acquiring section for acquiring status information including at least error detection information from the communication device; a determination section for determining whether or not the data transfer process can be executed based on the status information acquired by the status information acquiring section when the data transfer process is being executed; and a data transfer process executing section for executing the data transfer process in accordance with a result of determination as to whether or not the data transfer process can be executed by the determination section.

Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

Abstract: Techniques are described for providing mechanisms of data distribution to and collection of data from multiple memories in a data processing system. The system may suitably be a manifold array (ManArray) processing system employing an array of processing elements. Virtual to physical processing element (PE) identifier translation is employed in conjunction with a ManArray PE interconnection topology to support a variety of communication models, such as hypercube and such. Also, PE addressing nodes are based upon logically nested parameterized loops. Mechanisms for updating loop parameters, as well as exemplary instruction formats are also described.