Abstract: Selecting between basic and global persistent flush modes is described. In accordance with the described techniques, a system includes a data fabric in electronic communication with at least one cache and a controller configured to select between operating in a global persistent flush mode and a basic persistent flush mode based on an available flushing latency of the system, control the at least one cache to flush dirty data to the data fabric in response to a flush event trigger while operating in the global persistent flush mode, and transmit a signal to switch control to an application to flush the dirty data from the at least one cache to the data fabric while operating in the basic persistent flush mode.

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

Abstract: Embodiments herein describe memories in a processor system in an integrated circuit (IC) that can be assigned to either a cache coherent domain or an I/O domain, rather than being statically assigned by a designer of the IC. That is, the user or customer can assign the memories to domain that best suits their desires. Further, the memories can be reassigned to a different domain if the user later changes her mind.

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Abstract: Embodiments of the present invention provide systems, methods, and computer storage media directed to providing talk back automation for applications installed on a mobile device. To do so actions (e.g., talk back features) can be created, via the digital assistant, by recording a series of events that are typically provided by a user of the mobile device when manually invoking the desired action. At a desired state, the user may select an object that represents the output of the application. The recording embodies the action and can be associated with a series of verbal commands that the user would typically announce to the digital assistant when an invocation of the action is desired. In response, the object is verbally communicated to the user via the digital assistant, a different digital assistant, or even another device. Alternatively, the object may be communicated to the same application or another application as input.

Abstract: A L2 cache is set associative, has N ways, and is inclusive of a virtual L1 cache such that when the virtual address misses in the L1: a portion of the virtual address is translated into a physical memory line address (PMLA), the PMLA is allocated into an L2 entry, and a physical address proxy (PAP) for the PMLA is allocated into an L1 entry. The PAP for the PMLA includes a set and a way that uniquely identify the L2 entry. The L2 receives a physical memory line address for allocation, uses a set index portion of the PMLA, and for each L2 way, forms a PAP corresponding to the way. The L1, for each PAP, generates a corresponding indicator of whether the PAP is L1 resident. The L2 selects, for replacement, a way whose indicator indicates the PAP is not resident in the L1.

Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.

Abstract: An eyewear device that includes a plurality of SoCs that share processing workload, and a USB port configured to perform low-power debugging and automation of the plurality of SoCs, such as using either a Universal Asynchronous Receiver-Transmitter (UART) or a Serial Wire Debug (SWD). The eyewear includes a USB hub configured such that the USB port can simultaneously communicate with the plurality of SoCs. The USB hub can be shut down to disable the USB hub, and all the SoCs can enter their low-power modes without being kept awake by a persistent USB connection. The eyewear includes a first switch and a control logic, wherein the control logic controls the first switch and enables the USB port to perform low-power debugging and automation of the SoCs. The eyewear further includes a second switch, wherein the control logic controls the second switch to enable the USB port to perform low-power debugging and automation of the SoCs via a processor, or to enable the USB port to control each of the SoCs.

Abstract: In an embodiment, a method includes: receiving a global trigger with a first millimeter-wave radar; receiving the global trigger with a second millimeter-wave radar; generating a first internal trigger of the first millimeter-wave radar after a first offset duration from the global trigger; generating a second internal trigger of the second millimeter-wave radar after a second offset duration from the global trigger; start transmitting first millimeter-wave radar signals with the first millimeter-wave radar based on the first internal trigger; and start transmitting second millimeter-wave radar signals with the second millimeter-wave radar based on the second internal trigger, where the second offset duration is different from the first offset duration, and where the first and second millimeter-wave radar signals are transmitted sequentially so as to exhibit no temporal overlap.

Abstract: Ensuring the appropriate utilization of system resources using weighted workload based, time-independent scheduling, including: receiving an I/O request associated with an entity; determining whether an amount of system resources required to service the I/O request is greater than an amount of available system resources in a storage system; responsive to determining that the amount of system resources required to service the I/O request is greater than the amount of available system resources in the storage system: queueing the I/O request in an entity-specific queue for the entity; detecting that additional system resources in the storage system have become available; and issuing an I/O request from an entity-specific queue for an entity that has a highest priority, where a priority for each entity is determined based on the amount of I/O requests associated with the entity and a weighted proportion of resources designated for use by the entity.

Abstract: Bus system comprising a first bus and a second bus, wherein the first bus is connected to the second bus through a bridge and a multiplexer. A first master has access to the second bus via the first bus, the bridge and the multiplexer. A second master has access to the second bus via the multiplexer. The bridge comprises an arbitration unit which is arranged to allow both a first master and a second master access to the second bus in such a way that no access is disturbed or lost.

Abstract: A processor system includes a processor and a first memory area storing a boot program code. The boot program code starts execution of an operating system when executed by the processor, and performs a cryptographic operation when the processor executes the boot program code. A second memory area stores one or more cryptographic keys and is only accessible to the boot program code. A third memory area stores the operating system. The processor retrieves the boot program code from the first memory area and executes the boot program code to start the execution of the operating system. The processor re-executes the boot program code to cryptographically encrypt data upon the basis of the cryptographic keys stored in the second memory area.

Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.

Abstract: Techniques for non-deterministic operation of a stacked memory system are provided. In an example, a method of operating a memory package can include receiving a plurality of memory access requests for a channel at a logic die, returning first data to a host in response to a first memory access request of the plurality of memory access requests, returning an indication of data not ready to the host in response to a second memory access request of the plurality of memory access requests for second data, returning a first index to the host with the indication of data not ready, returning an indication data is ready with third data in response to a third memory access request of the plurality of memory access requests, and returning the first index with the indication of data ready.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed to store data and erased when data is invalidated. Traditional storage devices waited to erase memory devices until new data was ready to write to them in order to avoid baking in the erase state. However, the act of erasing adds time to the overall program cycle and is getting larger as storage device capacity and complexity increases. Because of newer configurations, the threat of baking in erase states is decreased, allowing memory devices within a memory array to be pre-erased prior to writing. This reduces write times and be dynamically implemented in response to one or more changing conditions. Pre-erasing can be accomplished by utilizing a pre-erase list that can indicate pre-erased memory devices and provide them in response to a write command prior to the use of non-erased memory devices.

Abstract: The method includes: an FPGA board feeds back the quantity of controllers and the total quantity of DDR memories after receiving a hardware information acquisition request from a host; after a data space application request is received from the host, on the basis of the data space application request, perform data slice processing on data to be calculated, wherein the data space application request carries the dedicated application space capacity of each DDR and the data to be calculated, and the total quantity of slices of the data to be calculated is the same as the total quantity of DDR memories; and transmit each sliced data to a corresponding DDR space, and according to a data storage position of the sliced data in each DDR, read the data from the DDR memory space in parallel by means of the plurality of controllers and calculate same.

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

Abstract: There are provided a memory system and an operating method thereof. The memory system includes: a memory device for storing data in a program operation, and reading stored data and temporarily store the read data in a read operation; and a controller for transmitting data to the memory device, wherein the controller includes: a flash direct memory access (DMA) for reading and outputting the data temporarily stored in the memory device in the read operation; a buffer memory for storing the data output from the flash DMA; and a host DMA for reading the data stored in the buffer memory and outputting the read data to a host, wherein a first operation of storing the data temporarily stored in the memory device in the buffer memory and a second operation of outputting the data stored in the buffer memory to the host are performed in parallel.

Abstract: An autonomous driving system having dual secure boot is provided. The autonomous driving system includes: a control system, a host, and a baseboard management controller (BMC). The control system includes a microcontroller, a first flash memory, and a second flash memory. The first flash memory stores first embedded-controller firmware and a first application image file. The second flash memory stores second embedded-controller firmware and a second application image file. When the autonomous driving system is turned on, the microcontroller executes a dual secure boot procedure to execute the first embedded-controller firmware or the second embedded-controller firmware. In response to the microcontroller successfully executing the first embedded-controller firmware or the second embedded-controller firmware, the microcontroller authenticates the first application image file or the second application image file.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.

Abstract: Applying a rate limit across a plurality of storage systems, including: determining a rate limit for paired storage systems; receiving, by a first storage system, an amount of I/O operations serviced by the second storage system during a previous predetermined period of time; determining whether the amount of I/O operations serviced by the second storage system is less than half of the rate limit for the paired storage systems; if so, setting local a rate limit for a next predetermined period of time for the first storage system to the difference between the rate limit for the paired storage systems and the amount of I/O operations serviced by the second storage system during the previous predetermined period of time; and otherwise, setting a local rate limit for a next predetermined period of time for the first storage system to half of the rate limit for the paired storage systems.

Abstract: Ensuring the appropriate utilization of system resources using weighted workload based, time-independent scheduling, including: receiving an I/O request associated with an entity; determining whether an amount of system resources required to service the I/O request is greater than an amount of available system resources in a storage system; responsive to determining that the amount of system resources required to service the I/O request is greater than the amount of available system resources in the storage system: queueing the I/O request in an entity-specific queue for the entity; detecting that additional system resources in the storage system have become available; and issuing an I/O request from an entity-specific queue for an entity that has a highest priority, where a priority for each entity is determined based on the amount of I/O requests associated with the entity and a weighted proportion of resources designated for use by the entity.

Abstract: An FPGA upgrade method is provided, including: delivering, by a host, an upgrade instruction to an FPGA; uninstalling a PCIe driver corresponding to the FPGA to let a status of the PCIe link be changed to link down; continuously monitoring, in a first expiration time, whether the status of the PCIe link is changed to link up; and if yes, reloading the PCIe driver. The method further includes: after the FPGA receives the upgrade instruction, continuously monitoring, in a second expiration time, whether the status of the PCIe link is changed to link down, if yes, loading the configuration data from the FPGA configuration memory for upgrade; and after upgrade is completed, negotiating, by the FPGA, with the host to restore the status of the PCIe link to link up that is used for reloading the PCIe driver upon detection by the host.

Abstract: One embodiment provides a system which facilitates data movement. The system allocates, in a volatile memory of a first storage drive, a first region to be accessed directly by a second storage drive or a first NIC. The first storage drive, the second storage drive, and the first NIC are associated with a first server. The system stores data in the first region. Responsive to receiving a first request from the second storage drive to read the data, the system transmits, by the first storage drive to the second storage drive, the data stored in the first region while bypassing a system memory of the first server. Responsive to receiving, from a third storage drive associated with a second server, a second request to read the data, the system retrieves, by the first NIC, the data stored in the first region while bypassing the system memory of the first server.

Abstract: Enabling an integrated circuit (IC) to accommodate a new peripheral component interconnect express (PCIe) capability of an updated PCIe specification. Firmware-programmable registers for the IC, spanning a target range of register and function numbers to accommodate the new capability, are created. A host issues configuration requests to the IC, which include a register and function number for the new capability. The IC returns a value of a target register when the register number and function number are in the target range. The host updates the value and triggers a firmware interrupt to add the new capability to a list of existing capabilities.

Abstract: An optical image stabilization (OIS) circuit, applied to an OIS device including a single sensor configured to provide sensor data is provided. The OIS circuit includes a main OIS circuit configured to output a control signal to the sensor, and receive the control signal from the sensor with sensor data, output an interruption signal to initiate a control operation, and control a main OIS operation, and a sub-OIS circuit configured to be synchronized with the main OIS circuit based on the control signal input with the sensor data, and control a sub OIS operation based on the interruption signal.

Abstract: Embodiments detailed herein include, but are not limited to, a hardware processor to execute instructions and security circuitry to perform pre-boot operations including signature verification of a portion of firmware in a firmware storage hardware and initiating recovery upon a signature verification failure. The hardware processor comprises a plurality of cores in some embodiments. The hardware processor a multicore processor in some embodiments.

Abstract: An electronic apparatus has a processor; a peripheral having a data interface and a data-attribute interface; a direct memory access (DMA) controller for the peripheral; a memory; a bus system connecting the processor, the DMA controller, and the memory; a data link between the DMA controller and the peripheral; and a data-attribute link between the DMA controller and the peripheral, separate from the data link. The DMA controller has data-transfer circuitry for transferring data between the memory and the data interface of the peripheral over the data link, and for transferring data-attribute information, associated with the data, between the memory and the data-attribute interface of the peripheral over the data-attribute link.

Abstract: A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.

Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.

Abstract: Methods and apparatus for transacting multiple data flows between multiple processors. In one such implementation, multiple data pipes are aggregated over a common transfer data structure. Completion status information corresponding to each data pipe is provided over individual completion data structures. Allocating a common fixed pool of resources for data transfer can be used in a variety of different load balancing and/or prioritization schemes; however, individualized completion status allows for individualized data pipe reclamation. Unlike prior art solutions which dynamically created and pre-allocated memory space for each data pipe individually, the disclosed embodiments can only request resources from a fixed pool. In other words, outstanding requests are queued (rather than immediately serviced with a new memory allocation), thus overall bandwidth remains constrained regardless of the number of data pipes that are opened and/or closed.

Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.

Abstract: A processing system identifies a subset of pages of memory allocated to a source guest virtual machine (VM) running at a first graphics processing unit (GPU) that were modified by the source guest VM and transferring only the subset to a destination guest VM running at a second GPU when performing a live migration from the source guest VM to the destination guest VM. The first GPU maintains a page table of system memory addresses or frame buffer addresses allocated to and accessed by the source guest VM during a session, including an indication of whether the data was modified. Based on the page table information, the processing system identifies and transfers only the modified pages from the source guest VM to the destination guest VM, thereby reducing the time and bandwidth used for migration.

Abstract: A cable termination assembly configured for mounting to an interior portion of a printed circuit board. The cable termination assembly has a frame shaped to receive a paddle card to which a plurality of cables are terminated. A lid, when closed, may force the paddle card into contact with an interposer, which in turn may be pressed into a printed circuit board on which the cable termination assembly is mounted. Electrical signals may pass between the cables and traces in the printed circuit board via the paddle card and interposer. The termination assembly may be mounted near a processor or other high speed component on the printed circuit board, enabling high speed signals to be coupled with low loss between a periphery of the printed circuit board, or even a location off the printed circuit board, and the high speed component.

Abstract: An Internet-of-things (IoT)/machine-to-machine (MTM) wireless transmitter is obtained that has a semiconductor device including variable-resistance elements each of which is nonvolatile and rewritable and is able to hold each internal state without electric energy, and a modulator for receiving information from the semiconductor device and transmitting the information as a wireless signal.

Abstract: The invention provides a data storage system having dual channels, which comprises a host. The host comprises a host-side control unit, a first data storage device, and at least one second data storage device. The first data storage device comprises a first data-side controller. The host-side control unit is connected to the first data storage device via a high-speed channel, and accesses data of the first data storage device via the high-speed channel. The first data storage device is connected to each of the second data storage devices via a low-speed channel, respectively. The low-speed channel is a bus of broadcast type. The first data-side controller of the first data storage device manages data exchanging, data copying, and data moving between the first data storage device and the second data storage device via the low-speed channel.

Abstract: Methods, systems, and devices for stacked memory dice and combined access operations are described. A device may include multiple memory dice. One die may be configured as a master, and another may be configured as a slave. The master may communicate with a host device. A slave may be coupled with the master but not the host device. The device may include a first die (e.g., master) and a second die (e.g., slave). The first die may be coupled with a host device and configured to output a set of data in response to a read command. The first die may supply a first subset of the data and obtain a second subset of the data from the second die. In some cases, the first die may select, based on a data rate, a modulation scheme (e.g., PAM4, NRZ, etc.) and output the data using the selected modulation scheme.

Abstract: A system and method for automatically generating a control bifurcation signal to configure ports of a PCIe IO unit on a computing device. The lanes of the PCIe IO unit are divided into initial ports of the lowest granularity. It is determined whether a PCIe device is connected to each of the initial ports. The bifurcation port configuration of the PCIe IO unit is determined based on the initial ports having a connected PCIe device. Ports for the PCIe IO unit are configured based on the bifurcation port configuration.

Abstract: An apparatus for memory management a high-speed fabric controller and a memory controller connected between a high-speed memory and a processor. The memory controller is configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory. The apparatus includes a high-speed data connection between the memory controller and the high-speed fabric controller and a data connection between a tier of persistent data storage and the high-speed fabric controller. The high-speed fabric controller is configured to control data transfers between the tier of persistent data storage over and the high-speed memory independent of the processor.

Abstract: A system and method for automatically generating a control bifurcation signal to configure ports of a PCIe IO unit on a computing device. The lanes of the PCIe IO unit are divided into initial ports of the lowest granularity. It is determined whether a PCIe device is connected to each of the initial ports. The bifurcation port configuration of the PCIe IO unit is determined based on the initial ports having a connected PCIe device. Ports for the PCIe IO unit are configured based on the bifurcation port configuration.

Abstract: One or more of a plurality of input ports (P11-P14) that allow input of a binary signal are allocated to a unique port, and the potential thereof is fixed to a ground potential, etc., using the electrical wires (43d, 43c) of a wire harness. The potential of the remaining input ports in the initial state is set to a high potential using a pull-up circuit, etc., and a combination of the potential of the unique port and the potential of the remaining ports is associated with the ID value of the corresponding node. In order to share the remaining ports in the reading of the ID and the reading of a signal, the ID is established after a standby until a given time has elapsed without a change in the potential when the potential of the input ports is read.

Abstract: A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.

Abstract: A system on chip includes a display serial interface (DSI) host device, a camera serial interface (CSI) host device, a first register, and a loopback control circuit. The first register is configured to store a first flag indicating whether the system on chip is operating in a loopback mode or a non-loopback mode. The loopback control circuit is configured to loop back data generated by the DSI host device to the CSI host device in response to the first flag indicating that the system on chip is operating in the loopback mode.

Abstract: A method comprises, at a network adapter of a first device, detecting a write request for storing data in a storage device of the first device, and the write request comprises a first indication for a first storage address of the data in the storage device. The method also comprises, in response to detecting the write request, storing the data at a second storage address in a memory of the network adapter. The method further comprises, storing the first indication in association with a second indication for the second storage address in the memory to enable the storage device to obtain the data. With the above method, by processing and storing data via the controller and the memory of the network adapter, not only a waste of the processor and the memory of the first device is reduced, but also latency of processing commands is decreased.

Abstract: Ensuring the appropriate utilization of system resources using weighted workload based, time-independent scheduling, including: receiving an I/O request associated with an entity; determining whether an amount of system resources required to service the I/O request is greater than an amount of available system resources in a storage system; responsive to determining that the amount of system resources required to service the I/O request is greater than the amount of available system resources in the storage system: queueing the I/O request in an entity-specific queue for the entity; detecting that additional system resources in the storage system have become available; and issuing an I/O request from an entity-specific queue for an entity that has a highest priority, where a priority for each entity is determined based on the amount of I/O requests associated with the entity and a weighted proportion of resources designated for use by the entity.

Abstract: A processing method of data redundancy is utilized for a Non-Volatile Memory express (NVMe) to transfer data via a fabric channel from a host terminal to a Remote-direct-memory-access-enable Network Interface Controller (RNIC) and a Just a Bunch of Flash (JBOF). The processing method comprises virtualizing a Field Programmable Gate Array (FPGA) of the RNIC into a Dynamic Random Access Memory (DRAM) and storing the data to the DRAM; replicating or splitting the data into a plurality of data packets and reporting a plurality of virtual memory addresses corresponding to the plurality of data packets to the RNIC by the FPGA; and reading and transmitting the plurality of data packets to a plurality of corresponding NVMe controllers according to the plurality of virtual memory addresses; wherein the FPGA reports to the RNIC that a memory size of the FPGA is larger than that of the DRAM.

Abstract: Smart sensors comprising one or more microelectromechanical systems (MEMS) sensors and a digital signal processor (DSP) in a sensor package are described. An exemplary smart sensor can comprise a MEMS acoustic sensor or microphone and a DSP housed in a package or enclosure comprising a substrate and a lid and a package substrate that defines a back cavity for the MEMS acoustic sensor or microphone. Provided implementations can also comprise a MEMS motion sensor housed in the package or enclosure. Embodiments of the subject disclosure can provide improved power management and battery life from a single charge by intelligently responding to trigger events or wake events while also providing an always on sensor that persistently detects the trigger events or wake events. In addition, various physical configurations of smart sensors and MEMS sensor or microphone packages are described.

Abstract: Methods and apparatus for transacting multiple data flows between multiple processors. In one such implementation, multiple data pipes are aggregated over a common transfer data structure. Completion status information corresponding to each data pipe is provided over individual completion data structures. Allocating a common fixed pool of resources for data transfer can be used in a variety of different load balancing and/or prioritization schemes; however, individualized completion status allows for individualized data pipe reclamation. Unlike prior art solutions which dynamically created and pre-allocated memory space for each data pipe individually, the disclosed embodiments can only request resources from a fixed pool. In other words, outstanding requests are queued (rather than immediately serviced with a new memory allocation), thus overall bandwidth remains constrained regardless of the number of data pipes that are opened and/or closed.

Abstract: Examples herein describe a peripheral I/O device with a domain assist processor (DAP) and a domain specific accelerator (DSA) that are in the same coherent domain as CPUs and memory in a host computing system. Peripheral I/O devices were previously unable to participate in a cache-coherent shared-memory multiprocessor paradigm with hardware resources in the host computing system. As a result, domain assist processing for lightweight processor functions (e.g., open source functions such as gzip, open source crypto libraries, open source network switches, etc.) either are performed using CPUs resources in the host or by provisioning a special processing system in the peripheral I/O device (e.g., using programmable logic in a FPGA). The embodiments herein use a DAP in the peripheral I/O device to perform the lightweight processor functions that would otherwise be performed by hardware resources in the host or by a special processing system in the peripheral I/O device.