Abstract: Examples herein describe a peripheral I/O device with a domain assist processor (DAP) and a domain specific accelerator (DSA) that are in the same coherent domain as CPUs and memory in a host computing system. Peripheral I/O devices were previously unable to participate in a cache-coherent shared-memory multiprocessor paradigm with hardware resources in the host computing system. As a result, domain assist processing for lightweight processor functions (e.g., open source functions such as gzip, open source crypto libraries, open source network switches, etc.) either are performed using CPUs resources in the host or by provisioning a special processing system in the peripheral I/O device (e.g., using programmable logic in a FPGA). The embodiments herein use a DAP in the peripheral I/O device to perform the lightweight processor functions that would otherwise be performed by hardware resources in the host or by a special processing system in the peripheral I/O device.

Abstract: Applying a rate limit across a plurality of storage systems, including: determining a rate limit for paired storage systems; receiving, by a first storage system, an amount of I/O operations serviced by the second storage system during a previous predetermined period of time; determining whether the amount of I/O operations serviced by the second storage system is less than half of the rate limit for the paired storage systems; if so, setting local a rate limit for a next predetermined period of time for the first storage system to the difference between the rate limit for the paired storage systems and the amount of I/O operations serviced by the second storage system during the previous predetermined period of time; and otherwise, setting a local rate limit for a next predetermined period of time for the first storage system to half of the rate limit for the paired storage systems.

Abstract: A method, device and computer program product are disclosed. The method includes: receiving a command that reads data; parsing the command to obtain information sets; reading data based on the information sets; and sending the data and the information sets. The device includes: a memory that stores data in physical pages; and a controller that receives a command that reads data, parses the command to obtain information sets, reads data based on the information sets, and sends the data and the information sets. The computer program product includes code to: receive a command that reads data; parse the command to obtain information sets; read data based on the information sets; and send the data and the information sets.

Abstract: A hybrid DDR5 DIMM device includes a PCB board with a host interface through one of two DDR5 sub-channels, and a plurality of DDR4 or slow DDR5 SDRAM chips on the PCB coupled to this single channel DDR5 host interface. An embodiment processing system includes a host CPU to access one or more pairs of hybrid DDR5 DIMM devices for 4×DDR5 memory capacities (4DPC), a first or second hybrid DDR5 DIMM including a plurality of half-speed SDRAM chips, and a first or second DDR5 sub-channel coupled the host with slow SRAM chips on DIMM. Mounting same data-buffer and RCD chips on hybrid DIMM to a server motherboard can double available DDR4 DIMMs' speed to DDR5 speed rate. Pairs of hybrid DDR5 DIMM devices cascaded one-by-one can aggregate more DDR5 DIMM devices to expand memory capacities at double speed of DDR4 or DDR5 SDRAM chips, beyond current DDR5 speed limit 6400 MT/s.

Abstract: Generally described, aspects of the present disclosure relate to a live update process of the virtual machine monitor during the operation of the virtual machine instances. An update to a virtual machine monitor can be a difficult process to execute because of the operation of the virtual machine instances. Generally, in order to update the virtual machine monitor, the physical computing device needs to be rebooted, which interrupts operation of the virtual machine instances. The live update process provides for a method of updating the virtual machine monitor without rebooting the physical computing device.

Abstract: A semiconductor storage device in an embodiment includes a memory cell array, a pad to which data is inputted, an ODT circuit connected to the pad, an ODT driver configured to drive the ODT circuit, and a control circuit configured to supply an enable signal and a resistance value control signal to the ODT driver. The pad is arranged between the memory cell array and a first end side of the semiconductor storage device, and the ODT circuit is arranged between the pad and the first end side. The ODT driver is arranged between the ODT circuit and the first end side. An ODT control signal line configured to transmit a resistance value control signal, and an ODT enable signal line configured to transmit an enable signal are arranged between the ODT driver and the first end side.

Abstract: Example methods are provided for a host to perform packet processing using a service chain in a software-defined networking (SDN) environment. The method may comprise establishing a datapath between a first virtualized computing instance and a second virtualized computing instance in the service chain, the datapath bypassing a forwarding element to which the first virtualized computing instance and the second virtualized computing instance are connected. The method may also comprise: the first virtualized computing instance obtaining a packet that requires processing by the service chain, and performing packet processing according to a first service. The method may further comprise: the second virtualized computing instance obtaining the processed packet via the datapath, and performing packet processing according to a second service.

Abstract: A cloned configuration of a source machine is created by determining a first set of physical location codes for a source machine. A map is generated based on the sorted physical location codes that maps the first set of physical location codes to a first set of generic location codes. A second set of physical location codes associated with a second set of adapter slots in a target machine is generated. A second map is generated based on the sorted second set of physical location codes that maps the second set of physical location codes to a second set of generic location codes. A third set of physical location codes is generated based on the first set of generic location codes and the second map. If an entry in the third set of physical location codes is not present the second set of physical location codes, an error is generated.

Abstract: Provided are a memory control device and a method. The memory control device may include a memory device, and a controller operatively coupled to the memory device. The controller may include a receiving unit configured to receive a plurality of commands from a host, and a command processing unit configured to process the commands and order the host to transmit next commands when processing of the commands reaches a trigger point.

Abstract: A semiconductor memory device including a memory cell array including a plurality of memory blocks, a voltage generator applying operation voltages to a selected memory block, among the plurality of memory blocks, a control logic generating converted data by converting data bit sets respectively corresponding to at least one set of program states among a plurality of program states, during a program operation, and a read and write circuit temporarily storing the converted data and performing a program operation by controlling potential levels of bit lines of the memory cell array in accordance with stored converted data.

Abstract: A method of real-time data acquisition in a processing component using chained direct memory access (DMA) channels includes receiving a DMA event signal in a DMA controller of the processing component, and executing, responsive to the DMA event signal, DMAs to read at least one data sample from a peripheral device. A last DMA performs a write operation to acknowledge completion of the DMA event.

Abstract: Systems, apparatuses, and methods for migrating memory pages are disclosed herein. In response to detecting that a migration of a first page between memory locations is being initiated, a first page table entry (PTE) corresponding to the first page is located and a migration pending indication is stored in the first PTE. In one embodiment, the migration pending indication is encoded in the first PTE by disabling read and write permissions. If a translation request targeting the first PTE is received by the MMU and the translation request corresponds to a read request, a read operation is allowed to the first page. Otherwise, if the translation request corresponds to a write request, a write operation to the first page is blocked and a silent retry request is generated and conveyed to the requesting client.

Abstract: A method, device, and system for implementing hardware acceleration processing, where the method includes memory mapping input/output (MMIO) processing being performed on a data buffer address of a hardware acceleration processor in order to obtain an address in addressing space of a central processing unit (CPU). In addition, a network adapter has a remote direct memory access (RDMA) or a direct memory access (DMA) function. Alternatively, a network adapter of a hardware acceleration device can directly send received data on which the hardware acceleration processing is to be performed to a hardware acceleration processor. In this way, resource consumption is reduced when the CPU of a computer device receives and forwards the data on which the hardware acceleration processing is to be performed, and in addition, storage space of a memory of the computer device is saved.

Abstract: A data transfer device includes a buffer unit temporarily storing transfer data to be transferred to a common bus, a write control unit writing input data as the transfer data to the buffer unit and outputs a notification signal, a read control unit reading the transfer data from the buffer unit, an interface unit transferring the transfer data to the common bus according to a predetermined bus protocol, and a band-smoothing unit which smoothes a band of the common bus by delaying the notification signal, generating a read control signal, and outputting the read control signal to the read control unit, wherein when previous transfer data which has been read from the buffer unit already exists and a DMA transfer receipt ACK responding to a DMA transfer request REQ is received by the interface unit, the read control unit reads current transfer data from the buffer unit.

Abstract: Ensuring the appropriate utilization of system resources using weighted workload based, time-independent scheduling, including: receiving an I/O request associated with an entity; determining whether an amount of system resources required to service the I/O request is greater than an amount of available system resources in a storage system; responsive to determining that the amount of system resources required to service the I/O request is greater than the amount of available system resources in the storage system: queueing the I/O request in an entity-specific queue for the entity; detecting that additional system resources in the storage system have become available; and issuing an I/O request from an entity-specific queue for an entity that has a highest priority, where a priority for each entity is determined based on the amount of I/O requests associated with the entity and a weighted proportion of resources designated for use by the entity.

Abstract: An embedded memory includes a memory interface circuit, a cell array, and a peripheral circuit. The memory interface circuit receives at least a clock signal, a non-clock signal, and a setup-hold time control setting, and includes a programmable path delay circuit that is used to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting. The clock path is used to deliver the clock signal, and the non-clock path is used to deliver the non-clock signal. The peripheral circuit is used to access the cell array according to at least the clock signal provided from the clock path and the non-clock signal.

Abstract: A method, data processing system and program product utilize dynamic logical storage volume sizing for burst buffers or other local storage for computing nodes to optimize job stage in, execution and/or stage out.

Abstract: Managing input/output (‘I/O’) queues in a data storage system, including: receiving, by a host that is coupled to a plurality of storage devices via a storage network, a plurality of I/O operations to be serviced by a target storage device; determining, for each of a plurality of paths between the host and the target storage device, a data transfer maximum associated with the path; determining, for one or more of the plurality of paths, a cumulative amount of data to be transferred by I/O operations pending on the path; and selecting a target path for transmitting one or more of the plurality of I/O operations to the target storage device in dependence upon the cumulative amount of data to be transferred by I/O operations pending on the path and the data transfer maximum associated with the path.

Abstract: A method of transferring data between a host and a PCI device is disclosed. The method comprises mapping a fixed memory-mapping control block in a host memory of the host to a control register of a memory-mapping unit of the PCI device; mapping a dynamic data-access memory block in the host memory to a default memory block in a memory of the PCI device, wherein the memory-mapping unit translates an address between the dynamic data-access memory block and a memory block in the memory of the PCI device; and dynamically modifying a value in the control register of the memory-mapping unit through the fixed memory-mapping control block such that an address of the dynamic data-access memory block in the host memory is translated to a different address in the memory of the PCI device based on the modified value in the control register of the memory-mapping unit.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor subsystem having access to a memory subsystem and a device communicatively coupled to the processor subsystem, the device having an endpoint assigned for access by an operating system executing on the processor subsystem such that the endpoint appears to the operating system as a logical hardware adapter, wherein the device is configured to discover a private device coupled to the device, enumerate the private device as a managed device of the device, and map a portion of a virtual address space of an operating system executing on the processor subsystem to the private device, such that the private device is abstracted to the operating system as a virtual memory address of the operating system.

Abstract: Embodiments of the present disclosure use vendor defined messages (VDMs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using VDMs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may encode cache writebacks as VDMs to be sent to a root complex. The root complex may store the VDMs in a dedicated VDM buffer and send the VDMs on a dedicated VDM channel.

Abstract: Automated facial recognition is performed by operation of a convolutional neural network including groups of layers in which the first, second, and third groups include a convolution layer, a max-pooling layer, and a parametric rectified linear unit activation function layer. A fourth group of layers includes a convolution layer and a parametric rectified linear unit activation function layer.

Abstract: Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system is disclosed. In this regard, a compressed memory controller provides a CI hint directory comprising a plurality of CI hint directory entries, each providing a plurality of CI hints. The compressed memory controller is configured to receive a memory read request comprising a physical address of a memory line, and initiate a memory read transaction comprising a requested read length value. The compressed memory controller is further configured to, in parallel with initiating the memory read transaction, determine whether the physical address corresponds to a CI hint directory entry in the CI hint directory. If so, the compressed memory controller reads a CI hint from the CI hint directory entry of the CI hint directory, and modifies the requested read length value of the memory read transaction based on the CI hint.

Abstract: A computer system and a method are provided for accessing a peripheral component interconnect express (PCIe) endpoint device. The computer system includes: a processor, a PCIe bus, and an access proxy. The access proxy connects to the processor and the PCIe endpoint device; the processor acquires an operation instruction, where the operation instruction instructs the processor to access the PCIe endpoint device through the access proxy, and send an access request to the access proxy according to the operation instruction; and the access proxy sends a response message of the access request to the processor after receiving the access request sent by the processor. Because the processor does not directly access the PCIe endpoint device to be accessed but completes access through the access proxy, thereby avoiding an MCE reset for the processor.

Abstract: Various example embodiments herein disclose methods of enabling access to a storage device remotely over the network. According to at least one example embodiment, a method comprising initializing a Non-Volatile Memory Express (NVMe) controller, by a network device coupled to a server, configuring, by the network device, a NVMe queue pair for handling a remote device discovery process, receiving, at the network device, a request from the remote device to access the storage device controlled by the NVMe controller maintained at the server, initiating, by the network device, the discovery process for locating the remote device; and establishing, by the network device, a connection with the remote device by mapping the NVMe queue pair with a Remote Direct Memory Access (RDMA) queue pair, once the remoted device is discovered.

Abstract: Systems and methods for handling Shingled Magnetic Recording (SMR) drives in a tiered storage system. In some embodiments, an Information Handling System (IHS) may include a processor; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the IHS to: identify, among data stored in a first storage medium, a data subset that has a selected access pattern, wherein the selected access pattern is indicative of how often data is updated; and move the data subset from the first storage medium to one or more SMR drives.

Abstract: A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the first memory through a bus (14); a second processor (11) that inputs and outputs processed data from and to the second memory through the bus; and a management unit 32 that deallocates an address range corresponding to the second memory from the first process and allocates the address range to the second processor.

Abstract: An interface module has at least a configuration connection, a reset connection, a transmission connection and a reception connection. The interface module also has at least a first interface processing unit and a second interface processing unit which differs from the first interface processing unit and the connections of which can be connected to the connections of the interface module via a multiplexer. Only one set of interface connections needs to be provided on the interface module.

Abstract: Various embodiments are generally directed to techniques for improving the efficiency of exchanging packets between pairs of VMs within a communications server. An apparatus may include a processor component; a network interface to couple the processor component to a network; a virtual switch to analyze contents of at least one packet of a set of packets to be exchanged between endpoint devices through the network and the communications server, and to route the set of packets through one or more virtual servers of multiple virtual servers based on the contents; and a transfer component of a first virtual server of the multiple virtual servers to determine whether to route the set of packets to the virtual switch or to transfer the set of packets to a second virtual server of the multiple virtual servers in a manner that bypasses the virtual switch based on a routing rule.

Abstract: An image processing module input/output port in a DMAC includes an input part which receives second address information and an addressing request signal from an image processing module and an output part which outputs a reply signal indicating valid reception of the second address information to the image processing module. The image processing module input/output port can perform signal input/output control processing of returning, in response to the addressing request signal, the reply signal indicating confirmation of valid reception of the second address information to the image processing module when valid reception of the second address information is confirmed. A memory access controller performs memory access processing of accessing a storage area to be accessed in a memory based on the first address information (=the second address information) received via the image processing module input/output port.

Abstract: Managing input/output (‘I/O’) queues in a data storage system, including: receiving, by a host that is coupled to a plurality of storage devices via a storage network, a plurality of I/O operations to be serviced by a target storage device; determining, for each of a plurality of paths between the host and the target storage device, a data transfer maximum associated with the path; determining, for one or more of the plurality of paths, a cumulative amount of data to be transferred by I/O operations pending on the path; and selecting a target path for transmitting one or more of the plurality of I/O operations to the target storage device in dependence upon the cumulative amount of data to be transferred by I/O operations pending on the path and the data transfer maximum associated with the path.

Abstract: A Peripheral Component Interconnect Express (PCIe) network system with fail-over capability and an operation method thereof are provided. The PCIe network system includes a management host, a PCIe switch, a first non-transparent bridge, and a second non-transparent bridge. The upstream port of the PCIe switch is electrically coupled to the management host. The first non-transparent bridge is disposed in the PCIe switch for electrically coupling to the first PCIe port of a calculation host. The first non-transparent bridge can couple the first PCIe port of the calculation host to the management host. The second non-transparent bridge is disposed in the PCIe switch for electrically coupling to the second PCIe port of the calculation host. The second non-transparent bridge can couple the second PCIe port of the calculation host to the management host.

Abstract: Various embodiments of systems and methods to interleave high priority key-value transactions together with lower priority transactions, in which both types of transactions are communicated over a shared input-output medium. In various embodiments, a central-processing-unit (CPU) initiates high priority key-value transactions by communicating via the shared input-output medium to a key-value-store. In various embodiments, a medium controller blocks or delays lower priority transactions such that the high priority transactions may proceed without interruption. In various embodiments, both of the types of transactions are packet-based, and the system interrupts a lower priority transaction at a particular packet, then completes the high priority transaction, then completes the lower priority transaction.

Abstract: An I/O DMA address may be translated for a flexible number of entries in a translation validation table (TVT) for a partitionable endpoint number, when a particular entry in the TVT is accessed based on the partitionable endpoint number. A presence of an extended mode bit can be detected in a particular TVT entry. Based on the presence of the extended mode bit, an entry in the extended TVT can be accessed and used to translate the I/O DMA address to a physical address.

Abstract: An I/O DMA address may be translated for a flexible number of entries in a translation validation table (TVT) for a partitionable endpoint number, when a particular entry in the TVT is accessed based on the partitionable endpoint number. A presence of an extended mode bit can be detected in a particular TVT entry. Based on the presence of the extended mode bit, an entry in the extended TVT can be accessed and used to translate the I/O DMA address to a physical address.

Abstract: An efficient search key processing method includes writing a first and a second search key data set to a memory, where the search key data sets are written to memory on a word by word basis. Each of the first and second search key data sets includes a header indicating a common lookup operation to be performed and a string of search keys. The header is immediately followed in memory by a search key. The search keys are located contiguously in the memory. At least one word contains search keys from the first and second search key data sets. The memory is read word by word. A first plurality of lookup command messages are sent based on the search keys included in the first search key data set. A second plurality of lookup command messages are sent based on the search keys included in the second search key data set.

Abstract: A Island-Based Network Flow Processor (IBNFP) includes a memory and a processor located on a first island, a Direct Memory Access (DMA) controller located on a second island, and an Interlaken Look-Aside (ILA) interface circuit and an interface circuit located on a third island. A search key data set including multiple search keys is stored in the memory. A descriptor is generated by the processor and is sent to the DMA controller, which generates a search key data request, receives the search key data set, and selects a single search key. The ILA interface circuit receives the search key, generates and ILA packet including the search key that is sent to an external transactional memory device that generates a result data value. The DMA controller receives the result data value via the ILA interface circuit, writes the result data value to the memory, and sends a DMA completion notification.

Abstract: A multi-processor includes a shared memory that stores a search key data set including multiple search keys, a processor, a Direct Memory Access (DMA) controller, and an Interlaken Look-Aside (ILA) interface circuit. The processor generates a descriptor that is sent to the DMA controller causing the DMA controller to read the search key data set. The DMA controller selects a single search key from the set and generates a lookup command message that is communicated to the ILA interface circuit. The ILA interface circuit generates an ILA packet that includes the single search key and sends the ILA packet to an external transactional memory device that generates a result data value. The result data value is communicated back to the DMA controller via the ILA interface circuit. The DMA controller stores the result data value in the shared memory and notifies the processor that the DMA process has completed.

Abstract: A computer system and a method are provided for accessing a peripheral component interconnect express (PCIe) endpoint device. The computer system includes a processor, a PCIe bus, and an access proxy. The access proxy connects to the processor and the PCIe endpoint device; the processor acquires an operation instruction, where the operation instruction instructs the processor to access the PCIe endpoint device through the access proxy, and send an access request to the access proxy according to the operation instruction; and the access proxy sends a response message of the access request to the processor after receiving the access request sent by the processor. Because the processor does not directly access the PCIe endpoint device to be accessed but completes access through the access proxy, thereby avoiding a machine check exception (MCE) reset for the processor.

Abstract: Apparatus and methods implemented therein are disclosed for communicating with flash memories. The apparatus comprises a flash interface module and a processor in communication with the flash interface module. The flash interface module is configured for communication with a first and second flash bank. The processor is configured to generate a plurality of command sequences in response to receiving a plurality of flash commands from a host system. Each of the plurality of command sequences corresponds to a respective one of the plurality of flash commands. Some of the plurality of command sequences comprises a first portion and a second portion and each of the first portion and second portion are atomic.

Abstract: A block memory device and method of transferring data to a block memory device are described. Various embodiments provide methods for transferring data to a block memory device by adaptive chunking. The data transfer method comprises receiving data in a data chunk. The data transfer method then determines that the data chunk is ready to be transferred to a block memory and transfers the data chunk to the block memory. The transfer occurs over duration, repeating the above steps until the transfer is complete. The data transfer method determines that the data chunk is ready to be transferred to the block memory based on at least in part on a duration of a previous transfer.

Abstract: A passive optical network (PON) packet processor for processing PON traffic includes a core processor for executing threads related to the processing of PON traffic and a plurality of hardware (HW) accelerators coupled to the core processor for accelerating the processing of said PON traffic. A memory unit is coupled to the core processor for maintaining program and traffic data. In an embodiment of the present invention, the PON packet processor includes a scheduler that optimizes the execution of PON related tasks.

Abstract: One embodiment relates to an integrated circuit with a modular direct memory access system. A read data mover receives data obtained from a source address, and a write data mover for sends the data to a destination address. A descriptor controller provides the source address to the read data mover and the destination address to the write data mover. Another embodiment relates to a method of providing direct memory access. Another embodiment relates to a system which provides direct memory access. Other embodiments and features are also disclosed.

Abstract: An information processing apparatus having first and second buses, includes: a read/write command unit transmitting a read command or a write command to the first bus; a read command unit receiving a read command from the second bus; a write command unit receiving a write command from the second bus; and a command unit transmit the read command and the write command to the read/write command unit based on the read and write commands received by the read command unit and the write command unit. Further, the command unit stops transmitting the read command, and, while stopping transmission of the read command, change a transmission order of the read and the write commands so that the read/write command unit transmits the write command with higher priority than the read command.

Abstract: An in-vehicle sensor (1) connected to a communication bus CAN includes a bus connection connector (40) including external communication terminals T3, T4, and external setting terminals T5, T6 each of which is brought into one of a plurality of connection states; judgment means S1-S7 for judging the connection states of the external terminals for setting T5, T6 when electric power is supplied in a state in which the bus connection connector (40) is connected to the communication bus CAN; identifier generation means S8 for generating an identifier ID of the in-vehicle sensor (1) based on the judged connection states; a nonvolatile storage section (11) for storing the identifier ID; communication means (10) for performing communications through the communication bus CAN using the stored identifier ID; and storing means S9 for storing a first generated initial identifier IDS in the storage section (11) as the identifier ID.

Abstract: A system, method, and computer readable medium for sharing bandwidth among executing application programs across a packetized bus for packets from multiple DMA channels includes receiving at a network traffic management device first and second network packets from respective first and second DMA channels. The received packets are segmented into respective one or more constituent CPU bus packets. The segmented constituent CPU bus packets are interleaved for transmission across a packetized CPU bus.

Abstract: Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration.

Abstract: A DMA controller (40) comprises a reading start address register (402) storing a reading start address from which reading starts; a reading data size register (403) storing the size of data to be read in a single reading operation; an offset value register (404) storing an offset value for updating the reading start address after the reading operation ends; a repetition upper limit value register (405) storing the upper limit value of the number of times of repetition of the reading operation; and a repetition counter register (406) storing the number of times of repetition of the reading operation. The controller (401) of the DMA controller (40) outputs an interrupt signal indicating that the processing of the DMA controller (40) ends when the value stored in the repetition counter register (406) reaches the value stored in the repetition upper limit value register (405).

Abstract: One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.

Abstract: A bus system that has at least two lines. A bus subscriber has at least one connection element that has at least two contacts that can each be connected to one of the lines. An address allocation device can be used to ascertain an address for the bus subscriber in the bus system on the basis of a respective connection state of the contacts with respect to the lines. Also, a method allocates addresses in the bus system.