Abstract: First and second data interfaces provide data transfer to and from a plurality of memory banks. The first data interface uses a first bus size and a first clock frequency. The second data interface uses a second bus size and a second clock frequency. The second bus size is an integer multiple of the first bus size. The first clock frequency is an integer multiple of the second clock frequency. A channelizer module segments data from the second data interface into data segments of the first bus size and transmits them to addressed ones of the plurality of memory banks using the first clock frequency. The channelizer module also receives data in accordance with the first bus size and first clock frequency from the plurality of memory banks, combines this data into the second bus size, and transmits the data to the second data interface using the second clock frequency.

Abstract: Techniques are disclosed for performing an auxiliary operation via a compute engine associated with a host computing device. The method includes determining that the auxiliary operation is directed to the compute engine, and determining that the auxiliary operation is associated with a first context comprising a first set of state parameters. The method further includes determining a first subset of state parameters related to the auxiliary operation based on the first set of state parameters. The method further includes transmitting the first subset of state parameters to the compute engine, and transmitting the auxiliary operation to the compute engine. One advantage of the disclosed technique is that surface area and power consumption are reduced within the processor by utilizing copy engines that have no context switching capability.

Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

Abstract: A storage architecture of a storage system environment has a storage connector interface configured to exchange data directly between flash storage devices on a server and a storage array of the environment so as to bypass main memory and a system bus of the server. According to one or more embodiments, the storage connnector interface includes control logic configured to implement the data exchange in accordance with one of a plurality of operational modes that deploy and synchronize the data on the flash storage devices and the storage array. Advantageously, the storage connector interface obviates latencies and bandwidth consumption associated with prior data exchanges over the main memory and bus, thereby enhancing storage architecture performance.

Abstract: Methods, systems and computer readable storage medium embodiments for communicating over a data bus include, determining a number of changes in bit value in respective bit positions between a previous bit string and a current bit string, transmitting either the current bit string in an inverted form over the data bus if the determined number of changes in bit value exceeds a threshold or the current bit string in non-inverted form if the determined number of changes in bit value does not exceed a threshold, and transmitting an additional at least one bit along with the current bit string having a logic value that indicates whether the current bit string is in an inverted form or non-inverted form. Methods, systems, and computer readable storage medium embodiments for receiving bit strings over a bus are also disclosed.

Abstract: Embodiments herein relate to sending a request to a storage device based on a moving average. A threshold is determined based on a storage device type and a bandwidth of a cache bus connecting a cache to a controller. The moving average of throughput is measured between the storage device and a host. The request of the host to access the storage device is sent directly to the storage device, if the moving average is equal to the threshold.

Abstract: An eMMC includes flash memory including an extended card specific data (CSD) register (“EXT_CSD register”), and an eMMC controller that controls operation of the flash memory. The eMMC controller is receives a clock from a host via a clock line, receives a SEND_EXT_CSD command from the host via a command line, and provides the host with eMMC information stored in the EXT_CSD register via a data bus in response to the SEND_EXT_CSD command, the eMMC information including maximum operating frequency information for the eMMC.

Abstract: Method and system for sending data from a memory of a computing system interfacing with a device is provided. An input/output control block (IOCB) from the computing system for transferring the data from the memory of the computing system is received by the device. The device then allocates a plurality of DMA channels to the IOCB for transferring the data from the memory of the computing system when a number of pending input/output (I/O) requests when the IOCB is received is less than a number of available direct memory access (DMA) channels to receive the data from the memory of the computing system.

Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.

Abstract: An apparatus of a data storage device is provided. The data storage device is connected to a host system via a peripheral component interconnect express (PCIe) interface. The host system includes a first memory having a plurality of first memory space addresses. The data storage device comprises a second memory, a non-transparent bridge (NTB) and a processor. The NTB is coupled to the host system, and having a first portion and a second portion. The processor coupled between the NTB and the second memory, wherein the first portion of the NTB and the plurality of first memory space addresses have a first mapping relationship therebetween, and the processor writes a first datum in the first memory into the second memory via the first mapping relationship according to a command from the host system.

Abstract: System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes: a circuit, and first and second memory banks, coupled to the circuit. The circuit may be configured to: store a first subset of the waveforms in the first memory bank, accumulate each waveform in a chunk-wise manner, where each chunk has a specified size, thereby generating a first bank sum including a first partial accumulation of the set of waveforms, store a second subset of waveforms in the second memory bank concurrently with the accumulation, and accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum including a second partial accumulation of the set of waveforms, where the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms.

Abstract: Embodiments of electronic circuits, computer systems, and associated methods include a module that accesses memory using virtual addressing, the memory including local memory that is local to the module and nonlocal memory that is accessible via a system bus coupled to the module, the module including logic coupled to the local memory via a local bus. The logic is configured to receive a memory access specified to a virtual address, determine whether the virtual address is within the local memory, and direct the memory access either to the local memory via the local bus or to the nonlocal memory via the system bus based on the determination.

Abstract: Embodiments of the present invention provide a data transmission apparatus, system, and method. The apparatus includes: a data transit module, configured to read configuration information of a first sending buffer of a first processor core, and when the configuration information indicates that the first sending buffer stores data to be transmitted to a receiving buffer of a second processor core, control a DMA module to transmit the data from the first sending buffer to the receiving buffer, and set interrupt information; and an interrupt management module, configured to read the interrupt information, and when the interrupt information indicates that an interrupt needs to be triggered to the second processor core, control a multi-core interrupt controller to trigger the interrupt to the second processor core, to enable the second processor core to process the data in the receiving buffer.

Abstract: An apparatus comprises a memory device to store a pre-generated Universal Serial Bus (USB) command before a USB peripheral device is coupled to a USB. The apparatus also includes a processing device to retrieve the pre-generated USB command from the memory device and transmit the pre-generated USB command to the USB peripheral device over the USB. A method comprises identifying a Universal Serial Bus (USB) peripheral device is coupled to a USB. The USB peripheral device is coupled to the universal serial bus after a pre-generated USB command is stored in a memory device. The method further includes transmitting the pre-generated USB command to the USB peripheral device over the USB in response to identifying the USB peripheral device is coupled to the USB.

Abstract: Mechanisms for performing all-to-all comparisons on architectures having limited storage space are provided. The mechanisms determine a number of data elements to be included in each set of data elements to be sent to each processing element of a data processing system, and perform a comparison operation on at least one set of data elements. The comparison operation comprises sending a first request to main memory for transfer of a first set of data elements into a local memory associated with the processing element and sending a second request to main memory for transfer of a second set of data elements into the local memory. A pair wise comparison computation of the all-to-all comparison of data elements operation is performed at approximately a same time as the second set of data elements is being transferred from main memory to the local memory.

Abstract: A device includes a first processor and a second processor. The first processor is configured to operate in accordance with a first power mode. The first processor includes a first transistor. The first processor is configured to, while operating in accordance with the first power mode, switch the first transistor at a first duty cycle. The second processor is configured to operate in accordance with a second power mode. The second processor includes a second transistor. The second processor is configured to, while operating in accordance with the second power mode, switch the second transistor at a second duty cycle. The second duty cycle is greater than the first duty cycle. The second processor consumes less power while operating in accordance with the second power mode than the first processor consumes while operating in accordance with the first power mode.

Abstract: The present disclosure provides a computer system that includes a processor coupled to a host memory through a memory controller. The computer system also includes an upper device communicatively coupled to the memory controller, the upper device configured to process local input/output received from or sent to a lower device. The computer system also includes a memory comprising a data flow identifier used to associate a data flow resource of the upper device with an external data flow resource corresponding to the lower device. A data packet received by the upper device from the lower device includes the data flow identifier.

Abstract: A controller as an embodiment of the present disclosure controls a timing of transmitting an access request that has been received from an initiator (or its transmission interval). The controller includes: transmitting and receiving circuitry configured to receive an access request related to burst accesses from a first initiator that is connected via a first bus to, and adjacent to, the transmitting and receiving circuitry and configured to transmit the access request to a second bus implemented as a network; and a transmission interval controller configured to control the timing of transmitting the access request that has been received from the first initiator according to density of the burst accesses during a period in which the burst accesses continue and an access load on the second bus.

Abstract: A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer.

Abstract: A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

Abstract: A system improves bandwidth used by a data stream. The system receives data from the data stream and partitions the data into bursts. At least one of the bursts includes one or more idles. The system selectively removes the idles from the at least one burst and transmits the bursts, including the at least one burst.

Abstract: An Accelerated Storage Controller (ASC) in an electronic device allows both conventional (slower) application processor to memory interfaces to be employed transparently to existing software, while also allowing software configuration to realize an accelerated storage architecture on demand. Some use cases for the electronic device do not require accelerated storage, and a bypass mode does not require any modification to existing software. Other use cases (such as fast download of multiple gigabytes of media) benefit from an accelerated storage architecture offloading transfer from the electronic device application processor, but could also work with the traditional processor to memory interface, at the cost of slower downloads. Embodiments of the present invention provide for both these possibilities in a software-configurable architecture. Furthermore, a number of other connectivity options are provided under software control to optimize performance and connectivity for different use case scenarios.

Abstract: A processing node of a server rack includes a processor to generate processing node management requests and to process responses to the node management requests, and a communication module to receive the processing node management requests, to transmit over a communication link to a management controller of the server rack external to the processing node a processing node management request, to receive over the communication link from the management controller processing node management information, and to transmit the processing node management information to the processor.

Abstract: A hardware apparatus for a system comprises an interface and a direct memory access device. The interface is configured to connect the hardware apparatus to a system bus, which the hardware apparatus can use to communicate with a central control unit in the system and/or with another hardware apparatus in the system. The direct memory access device is configured to directly access a main memory of the central control unit, and to set an identifier for data flow control in the main memory of the central control unit when the direct memory access device has terminated direct access to a main memory of the system.

Abstract: A microcontroller includes a system bus matrix to connect various modules. The microcontroller also includes direct connections between modules. For example, the microcontroller may include a direct connection between a data processing module and a memory controller module to improve the transfer rate for data that is processed by the data processing module.

Abstract: A system is disclosed that can include at least one processor module connectable to a memory bus. The processor module can include at least one memory, at least one offload processor mounted on the processor module, and configured to execute operations on data received over the memory bus, and to output context data to the memory and read context data from the memory, and a hardware scheduling logic mounted on the module and configured to control operations of the at least one processor.

Abstract: A structured data processing system is disclosed that can include a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules providing an in-memory database; and a central processing unit (CPU) in the first server connected to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules.

Abstract: Systems and methods are disclosed for selectively combining commands for a system having non-volatile memory (“NVM”). In some embodiments, a command dispatcher of a system can receive multiple commands to access a NVM for a period of time. After receiving the multiple commands, the command dispatcher can determine a set of commands that are naturally combinable. In some embodiments, the command dispatcher can select commands that are fairly distributed across different chip enables (“CEs”) and/or buses. After selecting the set of commands, the command dispatcher can combine the set of commands into a multi-access command. Finally, the command dispatcher can dispatch the multi-access command to the NVM.

Abstract: A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

Abstract: The present invention presents a system and method to provide a storage system wide approach to better manage IO requests and better manage the prefetch transfers of data to and from the drives.

Abstract: Methods, systems, and apparatus for implementing raw memory transactions. An SoC is configured with a plurality of nodes coupled together forming a ring interconnect. Processing cores and memory cache components are operatively coupled to and co-located at respective nodes. The memory cache components include a plurality of last level caches (LLC's) operating as a distributed LLC and a plurality of home agents and caching agents employed for supporting coherent memory transactions. Route-back tables are used to encode memory transactions requests with embedded routing data that is implemented by agents that facilitate data transfers between link interface nodes and memory controllers. Accordingly, memory request data corresponding to raw memory transactions may be routed back to requesting entities using headerless packets.

Abstract: A method for processing an incoming command destined for a target is provided, comprising: determining if the incoming command is a data command or a management command; forwarding the incoming command to a storage management component of the target when the incoming command is a management command; when the incoming command is a data command: determining if a disk command queue on the target is full; sending the incoming command to the disk command queue when the disk command queue is not full; when the disk command queue is full: starting a timer, the timer having a predetermined length; sending the incoming command to the disk command queue when the disk command queue becomes not full prior to the expiration of the timer; and sending a rejection of the incoming command to the host only if, upon expiration of the timer, if the disk command queue is still full.

Abstract: A semiconductor integrated circuit includes a bus, a memory connected to the bus, an arithmetic processing unit connected to the bus, a first DMA controller connected to the bus, and at least one functional block connected to the bus. The functional block includes a functional macro which is configured to perform a process that realizes a given function, a second DMA controller which is configured to control data transfer between the memory and the functional macro, and an access condition setting unit which is configured to set an access condition regarding the DMA transfer between the memory and the functional macro.

Abstract: Systems and methods schedule periodic and non-periodic transactions in a multi-speed bus environment that includes in a downstream hub a data forwarding component, such as a USB transaction translator, which accommodates communication speed shifts at the hub. The method may comprise receiving a split packet request defining a transaction with a device, tagging the request with an identifier allocated to the data forwarding component, storing the request in a transaction list associated with the identifier, initiating transfer of payload data, and updating a counter associated with the identifier to reflect an amount of payload data for which transfer was initiated. The identifier may have associated therewith a counter for tracking a number of bytes-in-progress to the data forwarding component and one or more transaction lists configured to store a plurality of split packet requests awaiting execution and state information regarding an execution status of the requests.

Abstract: A collaborative bus arbitration multiplex architecture includes of a main memory, a bus, a plurality of BMPDs, and a BAM. Arbitration can be done according to the following steps of awaiting whether any of the BMPDs renders any request for access; B) identifying whether the access authority of the bus is being fetched by any other BMPDs; C) identifying whether the main memory to which the request for access corresponds have any record that the corresponding BMPD needs special treatment; D) identifying whether all of the BMPDs have rendered the requests for access; E) according to a generic arbitration principle, identifying whether the corresponding BMPDs indicated in the steps C) and D) win the access authority; F) yielding the access authority of the bus to the BMPDs winning the access authority as indicated in the step E); and G) accessing the main memory.

Abstract: There is provided a semiconductor device having a reduced number of external terminals allocated for address input to receive access from outside, while realizing a high-speed response to an access from outside. The semiconductor device employs, in order to allow other external devices to directly access resources it possesses in its own address space, in an external interface circuit, external terminals which input a part of the address signal required for access from outside, a supplementary register which supplements the upper portion of address information that has been input from the external terminals, a mode register accessible from outside, and an address control circuit which generates an address signal to access the address space in a form based on information input from the external terminals, required supplementary information, and mode information of the mode register.

Abstract: A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12P, 12C) that are otherwise configured to communicate over an address-based network (18). Sync signals (46, 56) are generated for each of producer and consumer circuits (12P, 12C) from the address information encoded into requests that communicate the data streams output by the producer circuit (12P) and expected by the consumer circuit (12C). The sync signals (46, 56) for the producer and consumer circuits (12C) are then used to selectively modify the data stream output by the producer circuit (12P) to a format expected by the consumer circuit (12C). Typically, such modification takes the form of inserting data into the data stream when the consumer circuit (12C) expects more data than output by the producer circuit (12P), and discarding data communicated by the producer circuit (12P) when the consumer expects less data than that output by the producer circuit (12P).

Abstract: An apparatus generally including an internal memory and a direct memory access controller is disclosed. The direct memory access controller may be configured to (i) read first information from an external memory across an external bus, (ii) generate second information by processing the first information, (iii) write the first information across an internal bus to a first location in the internal memory during a direct memory access transfer and (iv) write the second information across the internal bus to a second location in the internal memory during the direct memory access transfer. The second location may be different from the first location.

Abstract: An apparatus includes a socket, a computer-readable medium, and a controller. The socket is capable of interfacing with different types of storage medium. The computer-readable medium is operable for storing a computer-executable universal driver associated with a first operation mode and compatible with each of the types of storage medium, and for storing a computer-executable dedicated driver associated with a second operation mode and compatible with only a subset of the types of storage medium. The controller is operable for selecting a selected driver from the universal driver and the dedicated driver if a storage medium is inserted into the socket and for operating in a corresponding operation mode to exchange data information with the storage medium according to the selected driver. The selected driver includes the dedicated driver if the storage medium is a member of the subset and otherwise the selected driver includes the universal driver.

Abstract: A data processing system includes a hub processing portion, and a first plurality of processing resources communicatively connected to define a first ring, wherein each processing resource of the first plurality of processing resources is communicatively connected to the hub processing portion.

Abstract: A data processing system includes a processor core, a system memory coupled to the processor core, an input/output adapter (IOA), and an input/output (I/O) host bridge coupled to the processor core and to the IOA. The I/O host bridge includes a register coupled to receive I/O messages from the processor core, a buffer coupled to receive I/O messages from the IOA, and logic coupled to the register and to the buffer that services I/O messages received from the register and from the buffer.

Abstract: Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller. In another embodiment, the device may include a bus translator and a self-selecting bus decoder. The bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses. A microcontroller may be coupled to a selected one of the plurality of different types of buses of the bus translator.

Abstract: A data processing system includes a processor core, a system memory coupled to the processor core, an input/output adapter (IOA), and an input/output (I/O) host bridge coupled to the processor core and to the IOA. The I/O host bridge includes a register coupled to receive I/O messages from the processor core, a buffer coupled to receive I/O messages from the IOA, and logic coupled to the register and to the buffer that services I/O messages received from the register and from the buffer.

Abstract: Administering connection identifiers for collective operations in a parallel computer, including prior to calling a collective operation, determining, by a first compute node of a communicator to receive an instruction to execute the collective operation, whether a value stored in a global connection identifier utilization buffer exceeds a predetermined threshold; if the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold: calling the collective operation with a next available ConnID including retrieving, from an element of a ConnID buffer, the next available ConnID and locking the element of the ConnID buffer from access by other compute nodes; and if the value stored in the global ConnID utilization buffer exceeds the predetermined threshold: repeatedly determining whether the value stored in the global ConnID utilization buffer exceeds the predetermined threshold until the value stored in the global ConnID utilization buffer does not exceed the predetermined thr

Abstract: Methods and apparatus are provided for implementing transaction layer processing (TLP) hint (TPH) protocols in the context of the peripheral component interconnect express (PCIe) base specification. The method allows an endpoint function associated with a PCI Express device to configure a steering tag header in the open systems interconnect (OSI) transaction layer to identify a particular processing resource that the requester desires to target, such as a specific processor or cache location within the execution core. A bit mask may be implemented by the hardware or operating system, for example, by embedding the bit mask in the steering tag header. The bit mask provides administrative oversight of the steering tag header configuration, to thereby mitigate unintended denial of service attacks or cache misses occasioned by aggressive steering tag configuration strategies employed by endpoint functions.

Abstract: An apparatus for processing a register window overflow and underflow includes register windows each configured to include local registers and incoming registers, dedicated internal memories configured to store contents of the local registers and the incoming registers for each word, dedicated data buses configured to connect the local registers and the incoming registers and the respective dedicated internal memories, a memory word counter configured to perform counting in order to determine whether or not there is a storage space of a word unit in the dedicated internal memories, and a logic block configured to control an operation of the dedicated data buses when one of a window overflow and a window underflow is generated based on the count value of the memory word counter.

Abstract: DMA transfer of audio and video data. The audio and video data may be received over a serial bus. A DMA engine may provide audio and video data packets to data storage logic based on the audio and video data. The DMA engine may provide each of the audio data packets with a first, same destination address of a first memory and may provide each of the video data packets with a second, same destination address of the first memory. The data storage logic may maintain first and second pointers that indicate a next current memory location for audio data in a first buffer and video data in a second buffer in the first memory, respectively. The data storage logic may receive and store the audio and video data packets at respective locations in the first and second buffers based on current values of the first and second pointers.

Abstract: Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core.

Abstract: A computer system consists of a plurality of nodes, each with an associated local host, coupled together with a plurality of point-to-point links. An isochronous data channel is established within the computer system between a first subset of the plurality of nodes. The isochronous data channel includes a linked list of buffers which are used as temporary storage locations for data transmitted on the isochronous data channel. Each node which is part of the isochronous data channel is configured as a sender or a receiver and data transmissions are commenced. The presence of isochronous data in the channel generates an interrupt which signals a central processing unit (CPU) that data is available. The data is transferred to an associated location within the linked list of buffers and the CPU then moves on to other tasks. In other embodiments, data is transferred using DMA techniques rather than interrupt driven events. Buffers can also be used to transmit isochronous data.

Abstract: A system and method for interfacing at least one ISA and/or PCI compliant device with a PCMCIA compliant socket on a host computer is disclosed. The system is particularly useful to allow ISA and/or PCI compliant devices, which could not otherwise be used with a portable computer having a PCMCIA socket, to be used with such computers. The system can provide complete compatibility between a PCMCIA socket and ISA /PCI compliant devices even though such industry standards include contradictory requirements. The system allows a user to easily connect and disconnect numerous ISA and/or PCI compliant devices via a single PCMCIA socket commonly found on portable computers.