Abstract: Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection.

Abstract: The present disclosure relates to an example of a method for a first router to adaptively determine status within a network. The network may include the first router, a second router and a third router. The method for the first router may comprise determining status information regarding the second router located in the network, and transmitting the status information to the third router located in the network. The second router and the third router may be indirectly coupled to one another.

Abstract: A device and method are disclosed for performing a limit address check validation in a switching device. The device includes a data selector circuit that is enabled to select the content of an address register in an array of address registers, and a comparator electrically coupled to the data selector circuit and enabled to take a first input from the data selector circuit and target address as a second input from a communication packet. The method includes receiving the target address, seeking and locating a matching address in an array of base address registers, directing the packet to the port associated with the matching address, determining the target address to be a valid address by comparing the target address with a limit address associated with the matching base address, and nullifying the match if the target address is greater than the limit address.

Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requester IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.

Abstract: A partition priority controlling apparatus includes a partition ID identifying unit, a partition ID match detecting unit for detecting whether or not a partition to which one of a plurality of system board modules belongs matches partitions to which the other system board modules respectively belong for at least one combination of the system board modules, and an inter-crossbar-unit conflict partition detecting unit for detecting a combination of partitions, which make a conflict between two of a plurality of crossbar units, for at least one combination of the two crossbar units on the basis of the determination result of the partition ID identifying unit, and the detection result of the partition ID match detecting unit.

Abstract: A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.

Abstract: An uninterruptible power supply (UPS) system that may incorporate a battery subsystem including at least one battery for generating electrical power, and a UPS subsystem including at least one power module. At least one first bus system may couple the battery subsystem to the UPS subsystem to supply electrical power to the UPS subsystem. An input and output (I/O) subsystem is in communication with an output of the UPS subsystem for generating an output signal. At least one second bus system may be used for coupling the output of the UPS subsystem to the I/O subsystem. At least one of the first and second bus systems may include a pair of parallel coupled, independent busses, and may further have a tie bar for enabling the pair of busses to be reconfigured as a single bus.

Abstract: A front side bus swizzle mechanism modifies the front side (address and data) bus on a chip so that, when the chip is positioned on one side of a printed circuit board, connection to a second chip located on the opposite side of the printed circuit board is simplified. The simplified connection may result in less complexity and minimize the consumption of additional printed circuit board real estate.

Abstract: An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.

Abstract: The invention aims at improving the scalability of a storage system using a switch with a small number of ports. A storage system includes a plurality of host connection control units 10 connected to host computers; a plurality of drive control units 12 connected to disk drives 13; and a plurality of 4 by 4 switching units 11 located between each of the host connection control units 10 and each of the drive control units 12, and switching a plurality of paths connecting each host connection control unit 10 and each drive control unit 12, wherein the plurality of 4 by 4 switching units 11 is arranged in multiple stages in the direction of information transmission and the 4 by 4 switching units 11 in each stage are connected so that only two paths are defined from a given host connection control unit 10 from among the host connection control units 10, to every drive control unit 12, and the two paths have no parts in common.

Abstract: In an embodiment, a multi-processor computer system includes multiple cells, where a cell may include one or more processors and memory resources. The system may further include a global crossbar network and multiple cell-to-global-crossbar connectors, to connect the multiple cells with the global crossbar network. In an embodiment, the system further includes at least one cell-to-cell connector, to directly connect at least one pair of the multiple cells. In another embodiment, the system further includes one or more local crossbar networks, multiple cell-to-local-crossbar connectors, and local input/output backplanes connected to the one or more local crossbar networks.

Abstract: A dual bus matrix architecture comprising: a first interconnect matrix connected to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports; a second interconnect matrix connected to a plurality of limited bandwidth peripherals and having a plurality of master ports and a plurality of slave ports; and a shared multiport controller connected to one (or more) of the slave ports of the first interconnect matrix and to one (or more) of the master ports of the second interconnect matrix, wherein the shared multiport controller controls accesses to the high performance peripherals and the limited bandwidth peripherals by directing accesses to the high performance peripherals through the first interconnect matrix and accesses to the limited bandwidth peripherals through the second interconnect matrix.

Abstract: The present invention describes a flexible routing scheme between masters and slaves in complex digital systems. The routing scheme is optimized for maximum versatility and configurability using switched resources in the form of configurable crossbar switches.

Abstract: A plurality of PCIe switch complexes are interposed between a plurality of I/O devices and a plurality of microprocessor complexes. Each PCIe switching complex comprises a plurality of PCIe switches wherein each switch possesses at least one non-transparent port. The non-transparent port is used to cross-couple each PCIe switch creating an active matrix of paths between the HBAs associated with each I/O device and each microprocessor. The paths between each HBA (I/O device) and each microprocessor are mapped using a recursive algorithm providing each I/O device with direct memory access to each microprocessor.

Abstract: Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Abstract: In a communication system, one of a plurality of communication apparatuses that acts as a host controls data transmission and the other communication apparatuses that act as devices perform data transmission under control of the host over a predetermined communication interface. The communication apparatuses have both host and device roles, and are configured to exchange the host and device roles by using a predetermined communication protocol are connected to the predetermined communication interface. A first apparatus acts as a host and a second apparatus as a device. The second apparatus transmits information concerning the second apparatus to the first apparatus. The first apparatus compares the transmitted information with information concerning the first apparatus to determine whether or not to switch the host and device roles according to a predetermined criterion. In response to an affirmative determination, the host and device roles are switched by using the predetermined communication protocol.

Abstract: Embodiments of the present invention provide a media drive that is intended for reduction in power consumption required for serial communications to/from a host, and a power saving method thereof. In one embodiment, a HDD includes: a cache; a host interface for transferring, to a host, transfer data read out from the cache; a host interface manager that controls the execution of commands so as to generate a transfer unnecessary period during which a command and transfer data need not be exchanged with the host; and a MPU that brings a serial communication part of the host interface into a power save mode during the transfer unnecessary period. The host interface manager determines the optimum data transfer timing of transferring data from the cache to the host on the basis of a transfer rate at which data is transferred to the host, and a read rate at which data is read out from a disk into the cache.

Abstract: A resource interconnect architecture and associated descriptor protocol provides more efficient communication between different resources in a data processing system. One embodiment uses a backdoor interconnect that allows some resources to communicate without using a central resource interconnect. Another embodiment uses nested descriptors that allow operations by different resources to be chained together without having to communicate back to an originating descriptor resource. In another embodiment, the descriptors are generated in hardware or in software. Other embodiments assign priority or privilege values to the descriptors that optimize processing and error handling performance.

Abstract: A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks.

Abstract: A programmable logic device with an embedded operating system is disclosed. The programmable logic device includes a bus, memory, a number of bidirectional communication ports, a switching mechanism. The operating system embedded in the programmable logic device responds to input received through the ports by either sending data to a device connected to one such port, or by instructing the switching mechanism to establish a direct connection between two such ports. This device may be included as part of a larger computer system.

Abstract: A router is provided that includes a plurality of lanes to receive inbound data from a plurality of different input ports. The router may further include a shared crossbar channel coupled to each of the lanes and to a plurality of output ports, the crossbar channel to receive inbound data from the plurality of lanes and to provide outbound data to the plurality of output ports. Each lane may include a local lane arbiter, a global lane arbiter and a port arbiter associated with each port.

Abstract: A UART interface communication circuit includes a plurality of communication devices, and each includes a UART interface, a selecting apparatus, a CPU, and a multiplexer (MUX). The communication devices connect with each other via the UART interfaces thereof. The selecting apparatus is connected to the CPU for defining one of the communication devices as a master communication device and the rest as slave communication devices. The MUX is connected between the UART interface and the CPU. When the master communication device transmits data carrying an ID to the slave communication devices, a slave communication device corresponding to the ID receives and processes the data, and transmits return data to the master communication device, and then the MUX receives the return data from the slave communication device and passes it to the CPU of the master communication device for processing.

Abstract: A processor bus has several data processing units, each connected to a line system which acts as a bus having bus segments connected in a separable manner through connection units. Functional units arranged on the bus carry out the information thereof. The functional units may carry out exchanges independently of each other. Conversely, functional units in different groups may carry out information exchanges simultaneously. The connection units define combinatory connections of the signal lines, with physical connections between the connection units provided by the bus segments. The connection units can carry out information exchanges with as many connected functional units as desired. The information path from a functional unit to selected functional units can be multiplexed or switched by toggling simultaneous connections to several functional units or by bridging non-participating functional units.

Abstract: Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment.

Abstract: An apparatus and method for scheduling within a switch is described. A set of input signals is received from input ports. The set of input signals is associated with a set of packets at the input ports. A request for each packet from the set of packets is generated based on the set of input signals. Each request has an input-port indicator, an output-port indicator and a service-level indicator. The packets are scheduled based on the service-level indicator.

Abstract: A method for connecting an externally accessible shared serial port to one of a plurality of target serial ports is provided. The target serial ports are associated with a plurality of different application cards within a shelf assembly. The method includes receiving, from an external device connected to an externally accessible shared serial port, a request for a connection between the externally accessible shared serial port and one of a plurality of target serial ports within a shelf assembly associated with a plurality of different application cards, and determining whether shelf resources are available to connect the externally accessible shared serial port to the requested target serial port. In response to determining that shelf resources are available, the externally accessible shared serial port is connected to the requested target serial port.

Abstract: Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A multi-node system for making the data transfer between nodes via each internodal crossbar switch comprises a plurality of internodal crossbar switches having a switch for transmitting the transfer data from a plurality of nodes to the node of transfer destination. If a fault occurs in the switch, the system is configured to make the data transfer between the nodes via any other internodal crossbar switch than the internodal crossbar switch having the switch where the fault occurs.

Abstract: According to one embodiment, an embedded system includes at least one processor, memory and peripheral subsystem. Each subsystem has a terminating node configured to issue and receive messages for the subsystem. A bus fabric interconnects the subsystems and includes a plurality of non-terminating nodes located at different points in the bus fabric and interconnected with the terminating nodes to form a peer-to-peer communication matrix between the subsystems. The non-terminating nodes route the messages over the peer-to-peer matrix so that instructions included in the messages are delivered to the terminating nodes identified in the messages for execution. Each node is assigned one or more unique object identifiers for identifying the nodes and the instructions included in the messages identify different control and data flow functions supported by different ones of the subsystems.

Abstract: A communication system has a monitor, memory and one or more resources. The memory is connected to the monitor by a bus and stores tasks and data. Each of the resources is connected to the monitor by the bus and performs a function or executes a program. The bus is implemented by a plurality of adjacent sections, each section being implemented as an ASIC connected to a resource. Each ASIC is arranged to assign sub busses of the bus with variable width.

Abstract: A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network (“MIN”) of switches configurable to form data paths from any input terminal to any output terminal.

Abstract: A method is provided for supporting device sharing between hosts via a bus fabric. A master host owns a device tree and provides IO services to at least one client host. The client host comprises generic device drivers and subscribes to IO services provided by the master host.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of CPU registers. The method may include use of a predetermined level of aggressiveness for the scheduling of the register diagnostic testing. The scheduled diagnostic testing may include writing known data to a register, reading data from the register, and comparing the known data with the data that was read. If the comparison indicates a difference, then a jump may occur to a fault handler routine.

Abstract: Computer-implemented system and method for presenting routing information in a measurement system. A meta-routing tool receives user input specifying a device, then retrieves a topography description for the device indicating connectivity between a plurality of components in the device, e.g., from memory or from a server coupled to the computer via a network. The tool then determines routability information for the device based on the topography description, e.g., by walking the topography, and displays the routability information, which is then useable to determine routing for the measurement system. The routability information includes possible routes through the device, and may also indicate potential side effects for one or more of the routes, e.g., sub-systems used by the routes. The tool may receive user input indicating one of the possible routes, and display a component-wise path used by the indicated route, as well as any sub-systems used by the indicated route.

Abstract: A crossbar switch is optimized for area, performance, and power by grouping the data lines that comprise the input ports and output ports of the switch into a plurality of separate cross-point blocks. Each cross-point block contains a complete set of input and output ports but the number of data lines comprising the input and output ports of each separate cross-point block is reduced to fraction of the number of data lines contained in each port of the crossbar switch. This fraction is equal to one divided by the number of separate cross-point blocks. Area, performance, and power of the crossbar switch are improved provided the area of the crossbar switch without grouping of data lines into separate cross-point blocks is determined by the pitch of the data lines rather than the area of the cross-point circuits. The number of blocks can be selected to optimize area, performance and power.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X?1)/2], wherein X equals the number of processor clusters.

Abstract: A method of storing data from a plurality of processors comprising the steps of (a) transferring data along a first bus (b) connectable between a first processor and a synchronising means and operable with a first protocol; (c) synchronising the synchronising means with a second processor; and (d) transferring the data along a second bus to a memory of the second processor wherein the second bus is connectable between the synchronising means and the memory of a second processor and operable with a second protocol.

Abstract: A technique to broadcast a message across a point-to-point network. More particularly, embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect.

Abstract: A multi-port memory, comprising: m (m?2) input/output ports independent of one another; n (n?2) memory banks independent of one another; and a route switching circuit capable of optionally setting signal routes of a command, an address, and input/output data between the m input/output ports and the n memory banks, wherein the route switching circuit allocates p (1?p?m) input/output ports optionally selected from the m input/output ports to a memory bank optionally selected from the n memory banks.

Abstract: A mother-board includes a chipset, a switch, and first and second PCI Express X16 graphics interfaces. The switch has first and second switch circuits. The switch selectively turns on one of the first and second switch circuits according to a control signal. The first PCI Express X16 graphics interface has former eight lanes electrically connected to the chipset, and latter eight lanes selectively electrically connected to the chipset through the first switch circuit. The second PCI Express X16 graphics interface has former eight lanes selectively electrically connected to the chipset through the second switch circuit. When the first switch circuit is turned on, 16 lanes of the first PCI Express X16 graphics interface are electrically connected to the chipset. When the second switch circuit is turned on, the former eight lanes of the second PCI Express X16 graphics interface are electrically connected to the chipset.

Abstract: Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement allows simultaneous maximization of microprocessor complex load sharing, and minimization of inter-processor signaling/metadata migration. Separating processing control from data placement allows the location of data buffering to be chosen so as to maximize bus bandwidth utilization and achieve non-blocking switch behavior. This separation reduces the need for inter-processor communication and associated interrupts thus improving computation efficiency and performance.

Abstract: There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Abstract: A shared memory device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access, wherein an input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros.

Abstract: A dynamic arbitration controller includes components for reading current state information as well as records of known arbitration states which may cause a deadlock condition, comparing the current state to the records of known arbitration states and resolving deadlock conditions during arbitration. The dynamic arbitration controller may include circuits for storing and retrieving information related to the arbitration. The dynamic arbitration controller may be implemented as a circuit design or as a computer program product stored on machine readable media.

Abstract: A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arbitration of connection requests to be setup or removed among multiple end devices and expander devices so as to increase system performance and reduce hardware cost in a standard compliant manner.

Abstract: A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.