Abstract: A multi-layer bus system includes an interconnect matrix, bus slaves, bus masters and a bus control circuit. The interconnect matrix has master connection ports and slave connection ports, and connects one of the master connection ports to one of the slave connection ports in response a control signal. The slaves are connected to the slave connection ports, respectively. The bus masters includes a priority bus master connected to one of the master connection ports and a non-priority bus master. The priority bus master generates a bus demand signal when it needs a real-time operation. The bus control circuit is connected between the non-priority bus master and the other master connection ports. The bus control circuit disconnects the non-priority bus master to the other master connection ports in response to the bus demand signal.

Abstract: Embodiments of the present invention provide a system that transfers data between the components in the computer system through a switch. In these embodiments, the switch includes multiple switch chips which are coupled together and are configured to collectively function as a switch. During operation, each switch chip, receives cells from the subset of the set of inputs and selectively transfers each of the cells to at least one output of the subset of the set of outputs coupled to the switch chip or of the subset of the set of outputs coupled to the other switch chips.

Abstract: A method is described that involves directing a configuration request through a switch core to a configuration agent. The method also involves processing the configuration request at the configuration agent. The method also involves sending a configuration command derived from the configuration request from the configuration agent to the switch core. The method also involves executing the configuration command at an agent to which the configuration command pertains.

Abstract: When the capacity availability of buffer memory provided to an output port of a frame to be transferred is exceeding a predetermined value, a crossbar switch is used for path change of the frame. When the capacity availability of the buffer memory of the output port is the predetermined value or lower, the frame is written into shared memory. Then, the frame is read from the shared memory for transfer to the output port. By selectively performing frame transfer using the crossbar switch and frame transfer via the shared memory, the effects can be reduced even if the port buffer overflows, and the writing throughput can be favorably improved.

Abstract: Many Peripheral Component Interconnect Express (PCIE) lanes are available between a root complex host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. Some lanes are directly connected from the root complex host to each slot. Each slot is driven by a different port and a different direct physical layer on the host. Other lanes are configurable and can be driven by any port and use a configurable physical layer on the host. These configurable lanes pass through an external switch or crossbar that connects the lanes from the host to one or more of the slots. The direct-connect lanes can be the first lanes to a slot while the configurable lanes are the higher-numbered lanes.

Abstract: An integrated circuit implementing a storage-shelf router used alone, or in combination with other storage-shelf routers, and in combination with path controller cards, to interconnect the disks within a storage shelf or disk array to a high-bandwidth communications medium, such as an FC arbitrated loop, through which data is exchanged between the individual disk drives of the storage shelf and a disk-array controller. A set of interconnected storage-shelf routers within a storage shelf can be accessed through a single port of an FC arbitrated loop or other high-bandwidth communications medium. Because, in one implementation, eight storage-shelf routers can be interconnected within a storage shelf to provide highly available interconnection of sixty-four disk drives within the storage shelf to an FC arbitrated loop via a single FC-arbitrated-loop port, a single FC arbitrated loop including a disk-array controller, may interconnect 8,000 individual disk drives to the disk-array controller within a disk array.

Abstract: Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A device including a nanowire crossbar array including a programmable material layer, at least one of input or output circuitry, and at least one array of input or output tips to provide an electrical connection between the nanowire crossbar array and the input or output circuitry.

Abstract: A method and system comprising at least two processing units that are connected with at least two memory units, wherein first data buses are connected with the memory units, wherein second data buses are connected with processing units, wherein cross bar switches are disposed between first and second data buses, and wherein a control unit controls the cross bar switches for connecting selected processing units with selected memory units.

Abstract: A signal switch for sharing a video monitor, a plurality of console devices compliant with an industry standard and one or more than one peripheral device in any of a plurality of computer systems, is provided comprising a CPU with a first memory for storing a management program for managing the signal switch; a hub switch module connected to the CPU and configured to communicate with any of the plurality of computer systems, and the one or more than one peripheral device; a device control module for emulating according to the industry standard the plurality of console devices, connected to the CPU and the hub switch module; a host control module connected to the CPU and configured to communicate with the plurality of console devices; and a video control module connected to the CPU and configured to communicate with a video monitor device.

Abstract: A method and a Fibre Channel switch element are provided that allows communication between a host system and a target device attached to a proprietary switch fabric in a network. The Fibre Channel switch element includes a first port that communicates with the target device through the proprietary switch fabric by logging on behalf of the host system so that the proprietary switch behaves as if it was directly communicating with the host system; and a second port that communicates with the host system and collects host bus adapter (“HBA”) identification information, wherein the HBA identification information is used to map the first port to the second port so that when the host system communicates with the target device the Fibre Channel switch element is transparent to the proprietary switch fabric.

Abstract: A configuration is such as to change a mode setup of other crossbars influenced by an error occurring in one of plural crossbars from a first mode to a second mode for operating each of them independently (i.e., in a singularization mode) in the case of placing plural crossbars (i.e., crossbar units) for connecting incorporated units (i.e., processing units) and operating the plural crossbars in the first mode (i.e., a dualized mode) for dualizing them, thereby continuing an operation of a system by using a normally operable part when an error occurs in a part of the system.

Abstract: A television with integrated signal switch (100) for sharing a television screen (14), a plurality of console devices compliant with an industry standard (16, 18) and at least one peripheral devices (20) with any computer system in a plurality of computer systems (12), is provided comprising a CPU (30); a hub switch module (32) connected to the CPU (30) and configured to communicate with any of the plurality of computer systems (12), and the at least one peripheral devices (20); a device control module (38) for emulating, according to the industry standard, the plurality of console devices, connected to the CPU (30) and the hub switch module (32); a host control module (44) connected to the CPU (30) and configured to communicate with the plurality of console devices (16, 18); and a video control module (50) connected to the CPU (30) and configured to communicate with the television screen (14).

Abstract: A programme-controlled unit comprises a crossbar with a multiplicity of ports, a multiplicity of devices which are connected to the ports of the crossbar and can exchange data via the crossbar, and debug resources for detecting the events and states occurring in the programme-controlled unit. The programme-controlled unit described can be characterized by the fact that the ports of the crossbar comprise a diagnostic port, that the addresses, data and/or control signals which are transmitted between two other ports of the crossbar are additionally also supplied to the diagnostic port, and that the debug resources are connected to the diagnostic port of the crossbar.

Abstract: Embodiments of the present invention take advantage of the extra slot and connectors in the P0/J0 position that are reserved for future use in the VXS standard to create a VXS-compliant backplane that has increased performance. The backplane is considered VXS-compliant in that it is compatible with VXS-compliant payload boards and switch boards. The backplane utilizes in the extra slot another VXS-compliant switch slot for a third VXS-compliant switch. The wiring of the switch slots are slightly modified to provide two differential pair serial connected between each of the three switch slots. Furthermore, wiring is added to the J0 connectors in at least one payload slot so that the payload slot is directly connected to each of the three switch slots. A payload board is also disclosed that is adapted to directly communicate with through the additional wiring with each of the three switches.

Abstract: A signal processing system is taught to be formed by combining a crossbar array with programming circuitry and signal input circuitry so as to provide a linear transformation from a set of input signals to a set of output signals. Applications of such a system to waveform generation, signal filtering, communications, and pattern recognition are explained. In one embodiment the crossbar array of the signal processing system may be a molecular nanowire crossbar array in which the crossbar interconnects are addressed via dual arrays of scanning probe tips so as to provide an interface between the molecular crossbar electronics and conventional solid state electronics used in the programming and signal processing circuitry.

Abstract: An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection with the back plane. The back plane distributes power to the modules and provides a communication link from the controller to each module. Each communication link includes a data out line, a data in line and a clock line, where each clock line is derived from one clock source.

Abstract: Each of a cluster of computing balls (1) contains within its housing (3) a photosensitive device (51) for receiving light from a light source (5) and converting it into energy to power a processing chip (2). There is thus wireless transmission of power to the computing balls (1), which also carry out wireless communication of data with one another. The computing balls (1) may be poured at random into a container (6), and intercommunicate to form a computing device.

Abstract: The multilayer system of this invention is characterized by the process when a first master such as a CPU to which a clock signal is constantly supplied from a clock generator activates a second master. First, the first master outputs an activation signal for activating the second master to the second master through a slave corresponding to the second master. The second master is activated by the activation signal and outputs to the clock generator a clock request signal for requesting supply of a clock signal to the second master. The clock generator supplies a clock signal to the second master in response to the clock request signal.

Abstract: A content addressable merged queue (camQ) architecture for high-speed switch fabrics reduces the memory requirement for crossbar switch input and output queues using memory cells and age tag comparators. CamQ emulates VOQ FIFO for each supporting priority, eliminating HOL blocking. Multiple QoS levels are supported cost effectively at higher traffic bandwidth limits. Content addressable memory (CAM) cells store payload destinations, which can be addressed by cell priorities. Once a priority for QoS is decided, all the cells with the selected priority in the payload can make connection requests to destination ports directly through the CAM structure. An age tag is assigned to incoming cells and fast age tag comparators provide FCFS features by selecting the oldest cell. Small memory sizes prevent the bottlenecking in ingress and egress queues. A CIOQ crossbar has a fast switching speed, emulating a FIFO output queue switch. Age and priority are interleaved to schedule switching.

Abstract: A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.

Abstract: A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip, to communicate with the CPU. In one embodiment, the programmable interface core includes a crosspoint switch for coupling a plurality of devices and the CPU. Re-programmability of the PLD provides significant flexibility in providing features that can be parameterized based on the user's needs and/or associated design. Specifically, these parameterized features can be implemented in programmable resources on the PLD, thereby allowing these features to be modified at any time. Moreover, only those resources actually needed for the programmable interface core need be implemented, thereby allowing the user to optimize use of the remainder of the PLD.

Abstract: In a storage system in which: LSW 110 is a local switch, GSW 115 is a global switch, and 21 is a global shared memory unit; when a host computer 3 makes a data read request to a disk control cluster 1-1, a channel interface unit 11 accesses to a local shared memory unit 22 via the LSW 110, and if the data exists in the disk control cluster 1-1, the channel interface unit 11 read the data from the local shared memory unit 22 or the disk drive 2 so as to transfer to the host computer 3. If the data is not in the disk control cluster 1-1, the channel interface unit 11 accesses to the global shared memory unit 21, check a disk control cluster with the requested data stored therein, obtains the requested data from the disk control cluster where the requested data is stored, and transfer the data to the host computer 3.

Abstract: An integrated circuit chip includes multiple functional components and a central interconnect (CI) module. Each functional component communicates with the CI module via a respective internal bus sharing a common architecture which does not dictate any particular data alignment. The chip architecture defines an alignment mechanism within the CI module, which performs any required alignment of transmitted data. Alignment mechanism design parameters can be varied to accommodate different alignment domains of different functional components. Preferably, the common bus architecture supports multiple internal bus widths, the CI module performing any required bus width conversion. Preferably, for certain transactions not containing a data address, correct alignment is obtained by placing restrictions on transaction size and boundaries, and duplicating certain data on different alignment boundaries.

Abstract: A method and apparatus includes identifying a first portion of a first message in a first slice of a switch, the first message associated with a first priority, the first portion of the first message including a first routing portion specifying a network resource; identifying a second portion of the first message in a second slice of the switch, the second portion of the first message including the first routing portion; identifying a first portion of a second message in the first slice, the second message associated with a second priority, the first portion of the second message including a second routing portion specifying the network resource; identifying a second portion of the second message in the second slice, the second portion of the second message including the second routing portion; selecting, independently in each slice, the same one of the first and second messages based on the first and second priorities; sending the first portion of the selected message from the first slice to the network reso

Abstract: A system for selectively forming high-speed serial connections between various components of a network device that includes a multiplexing switch coupled a GE slot and to the high speed serial interfaces of a PHY and at least two network devices. The switch can be programmed to connect the serial interfaces of the two network modules to provide a high-speed, low-latency serial link between the two network modules. Alternatively, the serial interface of a network module can be connected to the GE slot to provide a high-speed, low-latency serial link between the network module and the GE slot.

Abstract: Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.

Abstract: A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network (“MIN”) of switches configurable to form data paths from any input terminal to any output terminal.

Abstract: A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.

Abstract: In an advanced microcontroller bus architecture (AMBA) system with reduced power consumption, a signal transition is allowed to occur only in loads required for transferring bus signals by isolating loads on a bus signal transfer path requiring the signal transition from the other loads, so that the power consumption can be reduced in a bus architecture such as an advanced high-performance system bus (AHB).

Abstract: A system and method allows input/output to and from a computer system via the memory bus of a computer system. Input is accepted directly into shared memory or other memory and assigned to a processor or other entity. A processor or other entity may retrieve the input assigned to it and process the input. Output is written by the system processors to private memory, then retrieved from private memory by the system and method and output, for example to a network. Inputs and outputs are written to and from memory without using the I/O buses of the computer system and without generating interrupts to the system processors.

Abstract: Disclosed are ways of providing a highly flexible high availability storage system. Disk drive carriers for insertion into enclosures in a storage system include several disk drives. The enclosures accept carriers that include drives of different sizes, and drives compatible with different storage technologies, for instance Fibre Channel, SATA, or SAS. Drives oriented in their carriers in a manner that allows them to be connected to a common medium via identical flex circuits that are configured based on the orientation of the drives. Redundant controllers include redundant serial buses for transferring management information to the carriers. The carriers include a controller for monitoring the multiple serial buses and producing storage technology specific management commands for the disk drives.

Abstract: An input processing circuit is interposed between input terminals and input ports of an MPU. An output processing circuit is interposed between output ports of the MPU and output terminals. The input processing circuit includes switch sections and processing sections. The output processing circuit includes switch sections and processing sections. A switch control section switches the switch sections based on switch information stored in a switch information storage section to switch a connection relationship between the input terminals and the input ports, processing for an input signal, a connection relationship between the output ports and the output terminals, and processing for an output signal.

Abstract: In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.

Abstract: A system and method for facilitating communications between a plurality of devices that communicate using different cache-line sizes are disclosed. Briefly described, in architecture, one exemplary embodiment of a compatible cache-line communication system employs a plurality of first ports, each first port configured to receive communications from a first type of device that uses a first cache-line size; and a plurality of second ports, each second port configured to receive communications from a second type of device that uses a second cache-line size, such that communications between the first type of devices are enabled over a plurality of first routes, such that communications between the second type of devices are enabled over a plurality of second routes, and such that communications between the first type of devices and the second type of devices are disabled.

Abstract: An architecture for computing includes nanometer scale crossbar switches configured to perform a logical function in response to a sequence of pulses that encode logic values in the nanometer scale crossbar switches as impedances.

Abstract: A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers.

Abstract: In a method for exchanging data between several stations belonging to various data bus systems. The data bus systems are spatially and physically separate from each other. The stations exchange data via control devices which are respectively associated with a data bus system and which are interconnected by means of a faster data bus, which said bus is not busy.

Abstract: The present technique is associated with a device-controller configuration system for a computer system having a plurality of controllers. The technique utilizes an automatic switching assembly so that each device is routed to one of the controllers based on a data transfer specification of the device and data transfer capacities of the controllers. Accordingly, the technique evaluates at least one of a plurality of hypothetical configurations to determine a viable and/or optimal configuration.

Abstract: An apparatus having a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains (OSDs) through a load-store fabric, each routing transactions between the plurality of OSDs and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint requests/completes the transactions for each of the plurality of OSDs. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the transactions between the first plurality of I/O ports and the second I/O port. The core logic designates a corresponding one of the plurality of OSDs according to a variant of a protocol, where the protocol provides for routing of the transactions only for a single OSD.

Abstract: A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch (12) uses shared slave port control circuitry (48), configuration registers (46) and slave port arbiter logic (34, 36, 38, 40, 42 and 44) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.

Abstract: A data processing apparatus comprises a master device 150, 160, 170, 180, a slave device 110, 120, 130 and a communication bus 140 via which transaction requests are passed from master to slave. A transaction annotator of the master device generates transaction identifiers having a master identifier portion and a priority request portion. The slave device determines an order of servicing of transaction requests in dependence upon transaction ordering requests at least partially derived from the master identifier portions and in dependence upon priority values specified in the priority request portions.

Abstract: A method for adjusting the PCI Express lane ordering is disclosed, comprising the following steps. The first packet associated with a first PCI Express lane ordering is sent to the peripheral device. The peripheral device replies the second packet associated with the second PCI Express lane ordering. Whether the PCI Express lane ordering is correct is determined in response to said second packet. The first PCI Express lane ordering is adjusted while the first PCI Express lane ordering does not match the second PCI Express lane ordering. Preferably, the adjusted PCI Express lane order matches the normal order or the reverse order. Then, reset and reinitialize the peripheral device. The resetting step can be accomplished by sending reset packets, or changing the common mode voltage level in order to reset the bridge chipset of the PC.

Abstract: Many Peripheral Component Interconnect Express (PCIE) lanes are available between a host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. The host has 2N primary lanes plus one extra lane. The extra lane is allocated to a slot when another slot uses all 2N primary lanes. The extra lane ensures that a low-priority peripheral has at least one lane when a high-priority peripheral requires all primary lanes. A partial cross-bar switching matrix between the host and peripheral slots switches lanes at the physical layer using transistor bus switches. A switch controller can be programmed by configuration software to enable transistor bus switches to allocate and connect host lanes to slot lanes. Peripherals can have 1, 2, 4, 8, 12, or 16 lanes allocated and may be inserted into any of the slots.

Abstract: A method enabling I/O devices to be shared among multiple operating system domains, including first communicating with each of the operating system domains according to a protocol that provides exclusively for a single system domain ithin the load-store fabric; and second communicating with the shared I/O endpoint according to a variant of the protocol to enable the shared I/O endpoint to associate a prescribed operation with a corresponding one of the independent operating system domains. The second communicating includes encapsulating an OS domain header within a transaction layer packet that otherwise comports with the protocol, wherein the value of the OS domain header designates the corresponding one of the operating system domains; and via core logic within a swithching apparatus, mapping the independent operating system domains to the shared I/O endpoint.

Abstract: A crossbar switching fabric comprising a plurality of crossbar input ports and a plurality of crossbar output ports. The traffic from at least one source is directed to more than one of the plurality of crossbar input ports. The traffic from more than one crossbar output port is directed to at least one destination.

Abstract: A transmission unit that improves communication quality by making effective use of a line to a blocked port in compliance with a spanning tree protocol. Bridges have bridge ports and communicate at the layer 2 level. Physical ports are used for sending and receiving frames via lines. A bridge port state monitoring section monitors the state of ports. A port correspondence table managing section stores and manages a port correspondence table including the state of the bridge ports and the correspondence between the bridge ports and the physical ports in the unit and the correspondence between bridge ports and physical ports in an opposite unit. A switching section switches bridge ports and physical ports on the basis of the port correspondence table so that a line disconnected logically can be used for providing other communication services. A port state management control section sends and receives port state information.

Abstract: A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.

Abstract: The invention provides an interconnection architecture for semiconductor devices. Cross bar switches are traditionally placed in the center of the IC. However, this location may also be the preferred location for the centralized logic in the IC. This invention, known as a cross bar ring or CBR, provides cross bar switch functionality in a manner that can be easily distributed around the chip. Typically, it can fit in the routing channels between other functional blocks, thereby allowing other centralized functions to be placed in the center of the IC. The CBR is defined so that it can be partitioned into separate modules, which greatly aids in the placement and routing of wires. Furthermore, the architecture is defined such that the CBR can use storage elements, allowing it to be pipelined so that the wire distances can be increased while still maintaining a high internal clock speed.