Abstract: A Direct Memory Access (DMA) controller issues a read request to read data stored in a cache memory and sends a cache controller the read request via a bridge chip. When a response time monitored by a response time monitor exceeds a predetermined time, a status information notification unit obtains a measured value of a throughput from a throughput measuring unit and sends the cache controller a notification of both delay in the response time and the status information of a bus. A suppression instruction counting unit counts the number of suppression instructions, issued from the cache controller, to suppress a read request and sends a suppression control unit a notification of the number of suppression instructions. Then, the suppression control unit indicates a waiting time corresponding to the number of suppression instructions to the DMA controller to perform control to suppress issuance of a read request.

Abstract: A control system for data storage includes an electronic device, and a swap device. The electronic device includes a swap device detection module, first and second swap modules, and a storage device detection module. If the swap device is inserted in the electronic device, the swap device detection module outputs a first interrupt signal, the first swap module transfers data to be written to a first storage device to the swap device instead. If the first storage device is removed and a second storage device is inserted in the electronic device, the storage device detection module sends a second interrupt signal, the second swap module transfers data written and to be written to the swap device to the second storage device instead.

Abstract: A request control apparatus and a request control method are configured such that when an A type request that is an overtaking acceptable request allowed to overtake and to be overtaken among the other requests is turned to a retry matter on a pipeline, a request-order control unit performs an information renewal such that the A type request is rearranged to a place immediately preceding a B type request that is an overtaking inhibited request inhibited to overtake or to be overtaken among the other requests, and a request fetching unit fetches requests from ports by using the information renewed by the request-order control unit. Moreover, the request-order control unit is configured to perform request order control per request source.

Abstract: A disclosed image forming apparatus includes an image processing device including plural image processing units; a control device configured to control the plural image processing units; and a connection unit configured to connect the image processing device to the control device. Each of the plural image processing units is connected to the control device by one of plural channels; the image processing device is connected to the control device by a first bus including the channels; and the connection unit is provided on the first bus so that the image processing device is connected to the control device by a single connection unit.

Abstract: A device interface circuit unit transfers a command and data in packet format between the unit and the host. A transport layer is provided with a receive FIFO, a command detection circuit and a send FIFO, and an application layer is provided with a receive task file register and a send task control file register. An available time is generated for each break point of a packet during data transfer in order to receive another command packet from the host. When the command packet is received from the host in the available time during data transfer, the data transfer is suspended and the received command is decoded to execute a process for continuing or canceling the data transfer, after which the data transfer is resumed.

Abstract: A multi-core/multi-package bus termination apparatus includes a configuration array and a plurality of drivers. The configuration array generates location/protocol signals that each direct one of the plurality of drivers on the bus to employ location-based bus termination or protocol-based bus termination. The plurality of drivers is coupled to the plurality of location/protocol signals, a plurality of location signals, a bus ownership signal, and a multi-package signal. Each of the plurality of drivers controls how one of a plurality of nodes is driven responsive to a first state of one of the plurality of location/protocol signals.

Abstract: A method for transmitting and receiving digitally modulated wireless signals using an analog FM transceiver is provided. The analog FM transceiver has a transmit speech audio frequency band, a receive speech audio frequency band substantially equal to the transmit speech audio frequency band, a subaudible frequency band, a direct microphone audio input, and a direct speaker audio output. The method includes generating, in a baseband digital spectrum translator external to the analog FM transceiver, a baseband transmit signal occupying frequencies substantially within the transmit speech audio frequency band of the analog FM transceiver. The method also includes applying the generated baseband transmit signal to the direct microphone audio input to thereby transmit a digitally encoded RF TX signal having a constant envelope and using the analog FM transceiver to receive a digitally encoded RF RX signal with a constant envelope and to generate a baseband receive signal using the digitally encoded RF RX signal.

Abstract: Methods, apparatus, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA engine on an origin compute node in an injection FIFO buffer, a data descriptor for an application message to be transferred to a target compute node on behalf of an application on the origin compute node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying an address of a completion notification field in application storage for the application; transferring, by the origin DMA engine to the target compute node, the message in dependence upon the data descriptor; and notifying, by the origin DMA engine, the application that the transfer of the message is complete, including performing a local direct put operation to store predesignated notification data at the address of the completion notification field.

Abstract: Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.

Abstract: The present invention relates to a method for disconnecting a transceiver from a bus in multipoint/multidrop architecture. A central processing unit (CPU) and a universal asynchronous receiver transmitter (UART) in a system are connected to a controller used for storing and transmitting data, and the controller is further connected with a bus through a transceiver that monitors/records data and a relay that connects or disconnects the transceiver from the bus. The controller comprises a signal comparator used to compare similarities and differences of data and a failure detection controller used to achieve connection or disconnection of the bus with the transceiver. In case of the transceiver's failure, the controller disconnects the transceiver from the bus to ensure that the bus does not fail to work due to breakdown of the transceiver.

Abstract: One embodiment of the present invention sets forth a technique for reducing the latency associated with media protection notification for serial interface mass storage devices, such as serial AT attachment (SATA) hard disk drives. A new link layer primitive, referred to as hold-emergency (HOLDE), incorporates the flow-control behavior of the existing HOLD command, with the additional new action of notifying the hard disk drive to take emergency steps to prepare for impact. The HOLDE link layer primitive operates in conjunction with the existing hold-acknowledge (HOLDA) primitive and is semantically similar to the existing HOLD primitive. The HOLDE mechanism is preferably implemented directly in hardware in the SATA link layer state machines within the host and the hard disk drive.

Abstract: A computer system with concurrent direct memory access is provided including a computer node having a processor interface bus and a cut-through network interface controller installed on the processor interface bus. A data transfer is initiated through the cut-through network interface controller by starting a direct memory access to move data from a memory to a transmit buffer in the cut-through network interface controller and a network interface controller physical interface transmitting the data, to the computer node attached to a reliable network, before all of the data is in the transmit buffer.

Abstract: An interface controller connected to a read request device which performs a read request to a storage device stored with data, includes a receiving buffer which stores a read response of said storage device with respect to the read request sent from said read request device; and a control unit which performs read request authorization to said read request device on the basis of a capacity of said receiving buffer, a read request size and a read response size.

Abstract: An invention is disclosed for a computer software timeout algorithm that reduces the amount of list manipulation needed to satisfy system or network requirements for scheduling and cancelling timeout requests to determine whether the expiration time has been reached for execution of an input/output (I/O) request, thereby requiring action to cancel the I/O operation if it has not yet been completed.

Abstract: A media utilization administering device reads a medium ID saved in a memory card, obtains last update time information indicating the respective times during a data transfer at specified time intervals, and stores state information including the medium ID and the last update time information in a utilization administration memory. The media utilization administering device also stores the last update time information as the state information in the memory card. A transfer resumption judging device compares the medium IDs and the last update time information included in the state information and saved in both the memory card attached and the utilization administration memory when the data transfer was started. If the state information held by both agree as a result of the comparison, a transfer resumption controlling device causes a data transfer processing device to resume the data transfer from a position on the data indicated by the last update time information.

Abstract: Device, system, and method of utilizing PCI Express packets having modified headers. For example, an apparatus includes a credit-based flow control interconnect device to generate a credit-based flow control interconnect Transaction Layer Packet in which one or more bits of an ID field carry non-ID data.

Abstract: A method for authentication of an external storage device (16) operatively connected to a port of a host computer (10) where the host computer (10) conducts a handshake with the external storage device (16) seeking an authentication key from the external storage device. The host computer (10) electrically disconnects the external storage device (16) from the host computer (10) if the authentication key is incorrect or not provided within a predetermined period. The host computer (10) allows access to the host computer (10) by the external storage device (16) if the authentication key is correct and provided within the predetermined period. Corresponding apparatus and systems are also disclosed.

Abstract: Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: A data processing system is provided which includes a plurality of components to perform prescribed processing based on an operation mode, a chain controller to perform control including setting of the operation mode on at least one of the plurality of components, a storage unit to store chain configuration definition information associating at least one of the plurality of components with the chain controller for each prescribed data processing, and a configuration management unit to receive a processing request for the prescribed data processing and form a chain corresponding to the requested data processing based on the chain configuration definition information.

Abstract: A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a test mode command. The ODT circuit is coupled to the plurality of input/output pads and generates a plurality of termination impedances in response to the impedance control signals. The boundary scan circuit stores the termination impedances to output the stored termination impedances. Thus, the semiconductor device may test an ODT circuit accurately by using a smaller number of pins and may reduce a required time for testing the semiconductor device.

Abstract: An integrated circuit includes processing modules and an interconnect device for coupling the processing modules and for enabling a device-level communication based on transactions between the processing modules. A first processing module issues a transaction towards a second processing module. The integrated circuit further includes a transaction abortion unit for aborting the transaction issued from the first module by receiving an abort request issued by the first module, by initiating a discard of the transaction to be aborted, and by issuing a response indicating the success/failure of the requested transaction abortion.

Abstract: A computer program product, an apparatus, and a method for processing communications between a target and an initiator an input/output processing system are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes: sending a message between the initiator and the target, the message requesting suspension of input/output operations between the initiator and the target for a period of time, the period of time being defined by the message; and responsive to the message, suspending input/output operation messages for the period of time.

Abstract: A computer program product, apparatus, and method for handling early termination of an I/O operation at a channel subsystem in an I/O processing system are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a request to terminate an I/O operation, and transmitting an abort command to a control unit in communication with the channel subsystem in response to receiving the request to terminate the I/O operation. The method also includes transmitting a purge path command to purge a path associated with the I/O operation, where the purge path command includes an error code identifying the request to terminate the I/O operation.

Abstract: The storage device of the invention has a ramp mechanism which shakes out the head onto the disk medium, and causes the head to evacuate from the medium to hold it. The command queuing processing unit stores input/output commands into the command queue in the order of issuance by the host, and then, executes the commands in arrangement in the increasing order of the medium access time. Completion of commands is responded to the host in the order of completion of execution. The end of command is responded to the host in the order of end of execution. The emergency evacuation processing unit interrupts, upon receipt of an emergency evacuation command from the host during operation of the command queuing processing unit, operation of the command queuing processing unit and protects the head by causing the head to evacuate from the medium to the ramp mechanism.

Abstract: A command executing apparatus includes an executing unit that executes a command indicating process contents of a robot; a suspending unit that suspends execution of the command, when an interrupt command; a resumption condition generating unit that generates a resumption condition for resuming a suspending command; an executed contents generating unit that generates executed contents indicating the process contents executed until the suspending command is suspended; a suspending state holding unit that holds the resumption command and the executed contents in association with the suspending command; a resumption propriety judging unit that judges whether the suspending command is able to be resumed, when the resumption command is obtained; and a resuming unit that indicates the executing unit that the execution of the suspending command is resumed from a point at which the suspending command is suspended, when the suspending command is judged to be able to be resumed.

Abstract: An invention is disclosed for a computer software timeout algorithm that reduces the amount of list manipulation needed to satisfy system or network requirements for scheduling and cancelling timeout requests to determine whether the expiration time has been reached for execution of an input/output (I/O) request, thereby requiring action to cancel the I/O operation if it has not yet been completed.

Abstract: For use in a storage area network (SAN), a virtualization layer including at least one virtual engine having a respective local cache and a secondary cache layer, wherein the secondary cache layer includes the local caches coupled together, the local caches individually including a first cache layer, and at least one of a data transfer command and data corresponding to the transfer command are multicast to the secondary cache layer through an interconnection bus, the interconnection bus coupling the at least one virtual engine and at least one physical storage device.

Abstract: Decoding an address in an address space including a plurality of local ranges and a plurality of peripheral ranges is described. Various approaches for decoding an input address include determining decoder address bits of the address space that distinguish local ranges from each other and that distinguish local ranges from peripheral ranges. The local and peripheral ranges are interleaved and have a plurality of sizes. The number of decoder address bits is less than the number of address bits in the address space and less than the number of local ranges plus the number of peripheral ranges. Using the decoder address bits of an input address, it is determined whether the input address is within a portion of the address space that includes one of the local ranges and does not include any of the peripheral ranges nor the local ranges other than the one of the local ranges.

Abstract: Dynamically creating a communication path between first and second storage devices, includes creating a connection to a source volume on the first storage device and indicating that the source volume is not ready to transmit data on the communication path, after successfully creating the connection to the source volume, creating a connection to a destination volume on the second storage device and initially indicating that portions of one of: the destination volume and the source volume do not contain valid copies of data, where the destination volume accepts data from the source volume, and after successfully creating the connections to the source and destination volumes, indicating that the source volume is ready to transmit data on the communication path. Dynamically creating a communication path between first and second storage devices, may also include creating at least one of: the source volume and the destination volume.

Abstract: Data transmission between transmitting/receiving nodes in a bus system may be controlled based on an error check of received data. When an error in the received data is detected, the transmitting node may cease data transmission, and other nodes, which may not have detected the error, may be notified of the detected error.

Abstract: A semiconductor device and a control method thereof that include a memory cell array having a plurality of nonvolatile memory cells and a control circuit. The control circuit starts a first operation of the memory cells in a part of the region of the memory cell array when a first command is input, then decides whether to temporarily suspend the first operation or to reset the first operation when a second command is input, and temporarily suspends the first operation if the control circuit decides to temporarily suspend the first operation, and terminates the first operation if the control circuit decides to reset the first operation.

Abstract: Audio and visual information processing components are co-located on a PCI Express graphics card by communicating audio and visual information received through the PCI Express interface of the graphics card to a PCI Express switch which switches audio information to audio processing components and video information to video processing components for processing of the information to an audiovisual appliance output. The audio processing components may include an AC97 interface and CODEC or an audio controller that processes PCI Express information. The audiovisual output signal may include a variety of combined or separate audiovisual appliance compatible outputs such as coaxial cable output, EVC output, HDMI output, HDTV output or 1394 output.

Abstract: According to one embodiment, a data transfer apparatus includes a first device, a transfer unit which controls data transfer between a second device to be connected to the first device and to be controlled thereby, and a control unit which discards data to be transmitted from the second device when the first device decides to stop reception of the data to be transmitted from the second device in a status in which data transfer from the second device to the first device is performed.

Abstract: Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.

Abstract: A system and method for hardware based reassembly of a fragmented packet is shown. The method includes receiving a bandwidth request to transfer a data packet from the data provider. Then, bandwidth is allocated to the data provider, where the allocated bandwidth is less than the requested bandwidth. Next, the present invention receives part of the data packet in the allocated bandwidth from the data provider, where the part of the data packet includes a fragment header, and the fragment header includes a sequence number for the part of the data packet. The part of the data packet is then stored in external memory. Finally, the data packet is reassembled by concatenating in the correct sequence the part of the data packet with other parts of the data packets to create the reassembled data packet.

Abstract: A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: Machine-readable media, methods, and apparatus are described to burst write a command and its arguments to control registers of a device and to burst read status and outputs of the command from control registers of the device. During the burst write, the arguments may be transferred to the device in a reverse order in which the last argument is transferred first and the first argument is transferred last. Further, the command may be transferred after the arguments.

Abstract: A fast with-in range comparator is implemented in digital logic. A packet arrives at a device for processing. Initial packet data that is available in a first read cycle, is used to compute data that is necessary for later cycles. The initial data and the subsequently data are then used to test a single value against a range of values. In a method of the present invention a range is separated into two ranges. An upper limit of the first range is tested to determine whether the value is below the upper limit. If this test fails, the value is tested to determine whether the value is between the upper limit of the first range and the upper limit of the full range. The ranges are tested by constructing a bit vector. Data representing the capability of a communicating port, is then used to index into the bit vector. The outcome of the index is a value that signifies whether the port can support the packet or not.

Abstract: An intelligent volumetric module for use in metering pressurized syrup to a drink dispenser machine comprises a solenoid driven metering system for controlling liquid flows from a pressurized syrup container and a controller for controlling operation of said solenoid driven metering system according to uniquely addressed instructions received from the drink dispenser's system controller. The controller comprises a self-addressing capability, wherein serial communication to all but one non-addressed volumetric module is disrupted while a first address is assigned to that one module. Communication is the enabled along a serial bus to a next non-addressed module, to which a second address is assigned. The process continues until each volumetric module is assigned a unique address and connected to the serial communication bus.

Abstract: Improved techniques for rendering a peripheral device removable (e.g., unpluggable) are disclosed. According to one aspect of the invention, the peripheral device is rendered removable from a host computer without preparatory user actions. In effect, the peripheral device can be automatically prepared for removal in the event that its user removes (unplugs) it from its host computer. According to another aspect of the invention, the peripheral device includes a data storage device that is mounted to a file system of the other computer when the other computer desires access to the data storage device. Otherwise, the data storage device is normally unmounted so that if the peripheral device were to be removed (e.g., unplugged) no harm or damage to data stored therein would occur. These aspects of the invention can be utilized alone or in combination with one another.

Abstract: A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition.

Abstract: A method and apparatus to provide network buffer descriptors grouped by memory page into page groups and access a list of the page groups to manage the allocation and de-allocation of the network buffers descriptors is presented.

Abstract: An intelligent volumetric module for use in metering pressurized syrup to a drink dispenser machine comprises a solenoid driven metering system for controlling liquid flows from a pressurized syrup container and a controller for controlling operation of said solenoid driven metering system according to uniquely addressed instructions received from the drink dispenser's system controller. The controller comprises a self-addressing capability, wherein serial communication to all but one non-addressed volumetric module is disrupted while a first address is assigned to that one module. Communication is the enabled along a serial bus to a next non-addressed module, to which a second address is assigned. The process continues until each volumetric module is assigned a unique address and connected to the serial communication bus.

Abstract: A Serial ATA communications system has a host, a device, and a Serial ATA communications cable that connects the host to the device. The Serial ATA communications cable includes (i) a pair of transmit lines configured to carry a differential mode transmit signal, (ii) a pair of receive lines configured to carry a differential mode receive signal, and (iii) a set of ground lines. The host includes a transmit circuit configured to connect to the pair of transmit lines of the Serial ATA communications cable, a receive circuit configured to connect to the pair of receive lines of the Serial ATA communications cable, and a sensor. The sensor is configured to provide an output signal indicating whether a Serial ATA device is connected to the Serial ATA communications cable in response to a test signal applied to the set of ground lines.

Abstract: A measuring device, a measuring device controller, a measuring system, a measurement process performing method and a recording medium thereof which can easily and adequately perform a measurement process are provided. The present invention is constructed to include a program receiving unit 110 for receiving a control program, which comprises contents prescribing a measurement process, from said network; a memorizing unit 120 for memorizing the control program; an initiating instruction receiving unit 130 for receiving a program initiating instruction of the control program from the network; and a measurement control unit 156 for letting a measuring unit 160 perform the measurement process based on the control program memorized by the memorizing unit 120 in case the initiating instruction receiving unit 130 receives the program initiating instruction.

Abstract: An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit. When it is enabled, data in the data transmitting circuit are exported to a receiving circuit. When it is disabled, data exportation stops. The data monitoring circuit receives signals of the data transmission circuit and export signals to the control selection circuit. The data monitoring circuit judges whether the data transmission is under a stable condition. If it is not, an unstable signal is exported to a first input end of the control selection circuit. A second input end of the control selection circuit receives an output enabling signal. When the data transmission is stable and the output enabling signal indicates a disable status, the control selection circuit disables the data transmitting circuit. Otherwise, the control selection circuit enables the data transmitting circuit.

Abstract: Various embodiments of systems and methods for implementing a streaming I/O protocol are disclosed. In some embodiments, a method may involve: receiving a packet initiating a streaming write operation, where the packet indicates that the size of the streaming write is larger than the size of the packet; initiating a write access having a size larger than the size of the packet to a storage device; receiving subsequent packets included in the streaming write operation; and writing data received in the subsequent packets to the storage device as part of the write access initiated in response to the earlier packet. In some embodiments, streaming read operations may also be supported.

Abstract: A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; determining if the first predetermined number of data items have been transferred; determining if the first device should release the bus based on whether or not there is a request from a second device after it is determined that the first predetermined number of data items have been transferred; and releasing the bus by the first deice when it is determined that the first device should release the bus.