Abstract: It is an object to restore states of isochronous resources and logic plugs to normal states when failures occur in release of the isochronous resources and disconnection of the logic plugs. Information of isochronous resources and logic plugs of which release have been failed is managed as a table, a disconnection processing for connections is repeated till the connections are disconnected according to the table, and when disconnection cannot be effected even after repetition of a disconnection processing, a bus reset is generated to restore the bus to a normal state.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.

Abstract: An interface control device controls the packet-type transfer of data between one or more computers and one or more input/output devices. According to one embodiment of the present invention, when the interface control device receives the lead packet in a series of packets from an input/output device, it creates new device control data to control the transfer of the series of packets, and also determines an identification number for the particular series of packet transfers. The interface control device then sends a notification packet, containing the identification number, to the sending input/output device in response to receiving the lead packet. When the interface control device receives a packet that is a second or subsequent packet in the series of packets, it determines whether the data stored in the packet are normal by referring to the device control data corresponding to the identification number stored in the subsequent packet.

Abstract: Logic (also called “re-ordering semaphore”) issues semaphore grants to access a shared resource in an order different from the order in which semaphore requests for accessing the shared resource are received. The re-ordering semaphore needs to receive a semaphore release between any two semaphore grants. There is no limit on the duration between a semaphore grant and a semaphore release, so that a task that receives a semaphore grant can use the shared resource for any length of time. In one embodiment, each request is associated with a number indicative of the order in which grants are to be issued, and the re-ordering semaphore uses this number in deciding which request is to be granted. The number can be a sequence number that is indicative of the order of arrival of packets that generated the requests.

Abstract: An exemplary system includes a bus (such as CAN bus) having at least two end points. A first and/or a second set of an undetermined number of devices may be connected to the bus. A controller is also connected to the bus, and is configured to establish a termination of the bus at one of the end points relative to the first and second sets of devices, dependent upon whether the controller receives a reply message in response to a communication test message sent to the first and second sets of devices at different times. If the controller discovers that devices are connected to the bus in both sets, the controller is relieved of establishing an end point on either end of the bus. Otherwise, if the controller discovers that devices are only connected to the bus in one of the two sets, the controller is therefore, configured to terminate an end of the bus.

Abstract: Provided are a method, system, and program for increasing processor utilization. A list of work is divided for processing among a plurality of processes, wherein a process is allocated a part of the list of work to process, and the processes execute in parallel. If a process completes the list of work allocated to the process then the process is made available on an available process queue. Before a process performs any work, the process reads the available process queue and determines if any process is available to share the work. If so, the work is split up between the examining process and the available process. In one implementation, the work involves scanning a cache and if necessary destage data.

Abstract: Methods and associated structure operable within a SCSI-based storage subsystem to adapt the storage controller for use with non-SCSI disk drives. A firmware layer of the present invention intercepts SCSI read/write requests and pass through command blocks (CDBs) generated by the storage management core of the controller and translates the requests and command structures into corresponding command structures for transmission to a non-SCSI disk drive. In like manner, the firmware layer of the present invention receives status information from non-SCSI disk drives and translates the status information into corresponding SCSI compatible status information. In one exemplary preferred embodiment, a storage subsystem designed for interaction with SCSI disk drives may be adapted in accordance with the present invention to utilize lower-cost, commodity disk drives such as IDE compatible disk drives.

Abstract: Methods and a system for combining commands for data transfers between a drive and memory. One exemplary method includes receiving multiple read or write commands in a queue. Then, a first command of the multiple read or write commands is processed. Next, the multiple read or write commands are combined. The combination includes identifying like commands each being associated with a file stored on a drive and ascertaining which of the files associated with the like commands are contiguous. Then, a combined command is created, where the combined command consolidates the identified like commands being associated with contiguous files. Next, the combined command is issued to the drive.

Abstract: A method and a device for controlling data transmission between IDE apparatuses allow an IDE controller of an IDE control device to send read control signal to an IDE apparatus via a set of IDE interfaces and a signal control transmission line and then to send write control signal to another IDE apparatus via another set of IDE interfaces and another signal control transmission line. Thus, the output data from the IDE apparatus through the data transmission line can be accelerated the transmission speed thereof between IDE apparatuses so as to save the time for transmitting data.

Abstract: A communication system, network interface and communication port is provided that includes a media local bus. The local bus is connected between a controller and one or more multimedia devices located within a node of the communication system. The controller periodically broadcasts addressing signals to the source devices to synchronize data transmission from those devices according to those addresses. Source devices will thereafter transmit a command which signifies the type of data being transmitted from that source device within the address channel. The channel is maintained and data is transmitted until the next address is sent from the controller. Each channel can be set up in a customized fashion to add flexibility in channel length and data types being transferred throughout the local bus without having to assign fixed and regimented time slots for those data types and for each device connected to the local bus.

Abstract: A system including a host processor (11) operating in combination with one or more co-processors (13) is disclosed. In this system, a file storage facility (17) stores executable files (40) that are called by a server (15) in the host processor (11) by way of an application programming interface (API) (16). In the disclosed system, the executable files (40) include both a program (obj 2) together with information (obj 2 attrs) indicative of a condition needed for execution of the program. Based on the condition information, the program (obj 2) is downloaded (67) to the co-processor (13), and executed by the co-processor (13) if the the condition is satisfied.

Abstract: The debug controller makes an efficient use of memory in tracing the direct memory access by the processor and the direct memory access controller for the purpose of debugging. The direct memory access for read and write is efficiently traced by first writing a next access memory address at a currently accessing memory address.

Abstract: Systems, methods, apparatus and software can utilize an extent guard to prevent modification (including relocation) of data in the storage resource while a third-party copy operation directed at the storage resource is occurring. A data transport mechanism such as a data restore application provides an extent list to the extent guard, which monitors read and/or write activity to storage resources described by the extent list. The data transport mechanism requests a data mover to perform a third-party copy operation whereby data is moved from a data source to the storage resource. If a modification attempt is made on the portion of the storage resource described by the extent list, the extent guard stalls the modification attempt until the third-party copy operation is aborted.

Abstract: Data is moved between zones of a central processing complex via a data mover located within the central processing complex. The data mover moves the data without sending the data over a channel interface and without employing processor instructions to perform the move. Instead, the data mover employs fetch and store state machines and line buffers to move the data.

Abstract: Dynamically creating a communication path between first and second storage devices, includes creating a connection to a source volume on the first storage device and indicating that the source volume is not ready to transmit data on the communication path, after successfully creating the connection to the source volume, creating a connection to a destination volume on the second storage device and initially indicating that portions of one of: the destination volume and the source volume do not contain valid copies of data, where the destination volume accepts data from the source volume, and after successfully creating the connections to the source and destination volumes, indicating that the source volume is ready to transmit data on the communication path. Dynamically creating a communication path between first and second storage devices, may also include creating at least one of: the source volume and the destination volume.

Abstract: An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit at the control end, so as to enable or disable the transmission. When it is enabled, data in the data transmitting circuit are exported to a receiving circuit. When it is disabled, data exportation stops. The data monitoring circuit receives signals of the data transmission circuit and export signals to the control selection circuit. The data monitoring circuit judges whether the data transmission is under a stable condition. If it is not yet, an unstable signal is exported to a first input end of the control selection circuit. A second input end of the control selection circuit receives an output enabling signal. The output end of the control selection circuit is connected to the control end of the data transmitting circuit.

Abstract: A system and method for performing data transfers within a computer system is provided The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.

Abstract: A system and methods are shown for accommodating high-speed data retention. Multimedia packetized stream data packets are received through a receiving hardware system. Program Specific Information and System Information data tables describing the programs and information in the packetized stream are sent as section packets within the packetized stream. Various fields are included with the section packets describing such information as the portion of the data table represented, the type of data table represented, and the version of the table represented. A host system configures the section parser to identify and pass only the section packets with the fields it specifies. The section parser then compares the fields to the configured values and determines whether to pass the packets to the host system or to discard the packets. Accordingly, processing overhead conventionally left to the host system is performed through the section parser.

Abstract: Systems, methods, apparatus and software can utilize storage resource locks to prevent modification (including relocation) of data in the storage resource while a third-party copy operation directed at the storage resource is occurring. A data transport mechanism such as a data restore application requests that a relevant portion of the storage resource be locked. Once locked, the data transport mechanism requests a data mover to perform a third-party copy operation whereby data is moved from a data source to the locked portion of the storage resource. When the third party-copy operation is complete, the data transport mechanism requests release of the lock on the portion of the storage resource.

Abstract: Systems, methods, apparatus and software can utilize an extent guard to prevent modification (including relocation) of data in the storage resource while a third-party copy operation directed at the storage resource is occurring. A data transport mechanism such as a data restore application provides an extent list to the extent guard, which monitors read and/or write activity to storage resources described by the extent list. The data transport mechanism requests a data mover to perform a third-party copy operation whereby data is moved from a data source to the storage resource. If a modification attempt is made on the portion of the storage resource described by the extent list, the extent guard stalls the modification attempt until the third-party copy operation is aborted.

Abstract: To realize a mechanism for executing an optimum cancelling method among a plurality of cancelling methods for many various print environments on the user side, there is provided a mechanism having means for obtaining limitation information of the cancellation, using the optimum cancelling method among the plurality of cancelling methods on the basis of the obtained limitation information of the cancellation, and executing it.

Abstract: An apparatus and method for transferring high speed asynchronous data using a DMA controller. By using a conventional Universal Serial Asynchronous Receiver Transmitter (USART) with a small buffer, high speed asynchronous data can be manipulated by the DMA controller by use by other applications, such as wireless communication applications. The wireless communication applications includes Global System for Mobile communications (GSM), Code Division Multiple Access (CDMA), or Personal Digital Cellular (PDC). These wireless communication applications utilize high asynchronous data rates that would require more expensive USART with additional buffer capacity. In the receive mode, the high speed asynchronous data shifted into a DMA FIFO buffer from the USART. The data is then flushed into a host memory, such as a protocol stack by the DMA controller once the FIFO is full or if a timer expires. The data in the protocol stack is then manipulated by the wireless communication application.

Abstract: A system for protecting a block in a destination storage device including a data mover operable to move data from a source storage device to the block, and a controller coupled to the data mover, the controller operable to detect an application write request to the block and to stall the application write request while a data move operation initiated by the data mover is terminated.

Abstract: A method and apparatus for the early termination or deletion of frame data that is being transmitted or is scheduled for transmission from one network station to another network station. A network interface in the transmitting network station is able to read and transmit frame data as a central processing unit in the transmitting network is writing frame data into memory. The network interface reads a descriptor associated with frame data to determine if the frame data, which is either being transmitted or is scheduled for transmission, has a termination field indicating that the frame data is to be deleted. A descriptor management unit in the network interface reads the termination field in the descriptor and determines whether the frame data is currently being sent or is scheduled for transmission. If the frame data is scheduled for transmission, then the frame data is flushed from the data memory of the transmitting network station.

Abstract: An information-processing device includes a bus, a plurality of processors connected to the bus, and a bus-control unit which detects whether an excessively retried address transaction is present. Each of the processors includes an issuing unit which issues address transactions, a monitoring unit which communicate with the bus-control unit, and a retry-control unit which controls the issuing unit to suspend or restrain issuance of address transactions, other than the excessively retried address transaction, and to put an already issued address transaction in a status of compulsory retry if the monitoring unit is informed of a presence of the excessively retried address transaction by the bus-control unit.

Abstract: A method for controlling a transmitter for a serial data port is provided. The method includes receiving a set of data at the serial data port. The data in the set of data is compared with a selected pattern of bits. When data in the set of data matches the selected pattern of bits, a bit in a register is set. When the bit in the register is set, transmissions stop. The method further includes processing the set of data to determine a flow control state. When processing the set of data determines that the flow control state is a first state, transmissions re-start.

Abstract: An encoder receives a video input that includes initial video data and encodes the initial video data as encoded video data, such that the encoded video data comprises fewer bytes than the initial video data. The encoded video data is transmitted through a computer network to a decoder that receives the encoded video data and reconstructs an image representative of the video input for viewing on a display. A sensor senses at least one of viewer information representative of at least one of a location and movement of a viewer, and display information identifying the display. Viewer data representative of the at least one of the viewer information and the display information is transmitted to the encoder to modify the method of encoding the initial video data.

Abstract: A stream of data words is sent from a memory thru a controller and an external data buffer to an I/O device by a method which includes the steps of: 1) transferring a segment of the stream of data from the memory into the controller while concurrently sending a subsegment of the segment from the controller thru the data buffer to the I/O device via a transmission burst in which the receipt of individual parts of the subsegment are not acknowledged by the I/O device; 2) receiving a signal in the controller from the I/O device at any time during the sending step, to terminate the transmission burst; 3) subsequently receiving a signal in the controller, from the I/O device, to restart the transmission burst beginning with a selectable part of the last subsegment that was sent; 4) removing from the controller, only the portion of the segment which precedes the selectable part of the subsegment; and, 5) repeating the above steps until the stream of data is received in its entirety by the I/O device.

Abstract: Aspects for handling destage requests during shutdown in a log-structured array storage subsystem are described. In a method aspect, the method includes receiving a shut-down command, and utilizing at least three data structures for tracking destage requests when the shut-down command is received, wherein closing of open segments before completion of the shut-down is ensured. A further method aspect includes maintaining an outstanding requests list and destage requests list, forming a missing requests list based on the contents of the outstanding requests list and destage requests list when a shut-down command occurs, and tracking destage request processing with the outstanding requests list, destage requests list and missing requests list until all destage requests have been successfully completed.

Abstract: A serial bus controller having improved bus performance when a physical read request or a physical write request is present. A link and physical layer logic unit is provided, coupled to a serial bus having at least one peripheral device coupled thereto. A host interface is provided, coupled to a host data bus. A request FIFO is provided, coupled to receive a host memory read or write request packet from the link and physical layer logic unit, and coupled to said host interface. A physical read request FIFO is provided, coupled to receive a physical read request from the request FIFO for further processing of the physical read request. A physical write request FIFO is provided, coupled to receive a physical write response for transfer to the peripheral device.

Abstract: A memory controller used to manage the memory interface (main store interface) for processor and input and output (I/O) device access, includes a trace array used for accumulating trace data signals to be stored to main store, control logic used to determine when the array should be updated and when its contents should be stored to main store, an address register which provides the starting address of main store assigned to store trace data, an offset address register which identifies the current address to store trace data, and a space size register used to identify the amount of main store reserved to store trace data. In a first implementation, the contents of the trace array are moved to main store when the trace array becomes full. An alternative implementation provides additional control registers and logic which allow memory to be updated from the trace array when the memory interface is not busy.

Abstract: Methods and systems for reducing power consumption in data communications is presented. Portable devices that interface with peripheral devices reduce power consumption by minimizing the time that a communications port is open. Rather than keeping the communications port open for the duration of a program, the communications port is opened at calculated times to allow bursts of data to pass through and closed in response to certain events. This invention also works with normal power cycling methods of portable devices and peripheral devices to produce even further power savings.

Abstract: A preferred method includes the steps of: sampling at least one of the signals at the chip pad (12, 404, 406) corresponding thereto to detect signal reflections, and; adjusting the at least one of the signals at the chip pad so that line delay and/or signal reflections are modified. So provided, performance of the integrated circuit (10, 402) is improved as compared with the performance of the integrated circuit prior to the step of adjusting. Systems also are provided.

Abstract: An input/output control device used to enhance the efficiency of accesses to input/output devices in a computer system is provided. The input/output control device includes a means for storing a mapping table containing pairs of address and response time data associated with the input/output control devices, respectively. When a central processing unit (CPU) accesses an input/output device, a ready signal RDY or a defer signal DEFER is transmitted to the central processing unit from the input/output control device according to a response time corresponding to the accessed input/output device. Thus, the standby time of the central processing unit is greatly reduced, resulting in a better efficiency for the entire computer system.

Abstract: A host computer logs in an image providing device such as a scanner connected by a serial bus, and reverses flow control of data transfer by issuing a Reverse command. The image providing device opens a transfer channel by an OpenChannel command, transfers image data in form of blocks. When the transfer of the image data has been completed, the image providing device closes the transfer channel by a CloseChannel command, and reverses the flow control of the data transfer again by the Reverse command. This changes the data transfer direction of a device having a bi-directional data transfer function, i.e., a device having a data reception function and a data providing function.

Abstract: Signal capture control circuitry for use integrated in a switch for a telecommunications network, includes circuitry for selecting at least one of the call paths corresponding to a given call, for signal capture for analysis. Capture control circuitry for controlling the signal capture on the selected call path and for communicating with the call control circuitry is also provided. Having the signal capture control as part of the switch, and communicating with call control circuitry of the switch, makes it becomes possible to analyse previously inaccessible signals in the switch or in its inputs or outputs. Also, it becomes possible to trigger signal capture based on call control events which do not appear externally.

Abstract: A serial port is shared by a microcontroller and a host application. The microcontroller initially responds to a remote user making connection to the serial port. Upon the remote user requesting connection to the host application, a hardware switch connects a serial port connector to serial port hardware utilized by the host application. The connection between the remote user and the host application is monitored, so that when the connection between the remote user and the host application is discontinued, the serial port connector is reconnected to the microcontroller.

Abstract: A method of transferring image data between an initiator device and a target device using a IEEE 1394 standard bus. The present invention combines management functions, command functions, and isochronous data transfer to achieve the transfer of image data. The present invention discovers a target configuration using IEEE 1394 reads of a target configuration read only memory space. As part of the management function, the present invention uses a modified asynchronous data transfer protocol to establish a connection between the initiator and the target. Next, the present invention uses command functions to begin a job to transfer image data over an isochronous channel. Also, the present invention uses asynchronous data transfer to exchange printer job language commands to end a job.

Abstract: The present invention provides for a computer program product for use with a computer system having a main storage device in processing communication with an information transfer interface mechanism capable of coupling to a plurality of input/output devices. The computer program device comprises of a data storage element included in the main storage device having a computer usable medium with computer readable program means for receiving and retrieving data and computer readable code means for concurrently receiving multiple packets of data from said interface mechanism. It also includes computer readable code means for concurrently storing multiple packets of data concurrently in said data storage element as well as computer readable code means for storage and retrieval of multiple packets of data concurrently between said interface mechanism and said data storage element.

Abstract: The present invention provides control bus (SMBus) management and interface for a smart battery system having an SMBus two-wire interface with a clock and data line. Electrostatic discharge protection circuitry which does not have the potential to inadvertently charge a dead battery is provided for the SMBus. SMBus mastering circuitry is also provided to work in conjunction with the SMBus interfacing routines for communications on the bus.

Abstract: A system and method are provided for remotely managing memory in a programmable portable information device, such as a programmable watch, from an external computer. The portable information device has an optical sensor and a rewritable data memory. The computer has a frame-scanning graphics display device and a memory with a capacity larger than that of the device memory. The device memory is mapped into a portion of the computer memory to create a virtual device memory therein. An input device for the computer is provided to permit a user to enter programming changes to be made to the information device,. The programming changes alter the virtual device memory within the computer memory from an initial arrangement to a modified arrangement. Upon modification, a memory manager resident in the computer determines what memory transactions are effective to change the virtual device memory from its initial arrangement to its modified arrangement.

Abstract: The present invention relates generally to the field of disc controllers, and more specifically to an efficient buffer manager for a disc controller. A state machine in the buffer manager is provided which is responsive to a clock controlled by a single frequency base clock signal and a speed selection signal which indicates the speed of the buffer memory and which is designed to provide a base clock signal for the state machine having a fixed base period and an extended second portion of the cycle period which is extended to reflect the time of the RAMs cycle, plus the necessary time to allow for circuit delays and the like. Thus, different speed RAMs can be used in association with the buffer manager designed in this manner, while always controlling access for reading and writing to the RAM during a single complete cycle of the buffer manager. This allows for direct gating of all control signals to the buffer RAM, simplifying the design of the buffer memory controller and its associated logic.

Abstract: A data recirculation apparatus for a data processing system includes at least one output buffer from which data are output onto an interconnect, a plurality of input storage areas from which data are selected for storage within the output buffer, and selection logic that selects data from the plurality of input storage areas for storage within the output buffer. In addition, the data recirculation apparatus includes buffer control logic that, in response to a determination that a particular datum has stalled in the output buffer, causes the particular datum to be removed from the output buffer and stored in one of the plurality of input storage areas. In one embodiment, the recirculated data has a dedicated input storage area.

Abstract: A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; determining if the first predetermined number of data items have been transferred; determining if the first device should release the bus based on whether or not there is a request from a second device after it is determined that the first predetermined number of data items have been transferred; and releasing the bus by the first device when it is determined that the first device should release the bus.

Abstract: Data transfer methods and systems are described. The methods and systems permit the transferring of data which is organized into a plurality of records from a readable data storage medium to a host system with reductions in overhead and processing complexity. In a preferred embodiment, the readable data storage medium comprises a tape drive and the records have variable lengths. A data transfer processor is provided and is operably configured for coupling between the host system and the tape drive. A first record length parameter value is defined and describes a length of at least one record which is to be transferred from the tape drive to the host system. A first record having a length corresponding to the first record length parameter value is read from the tape drive and into a temporary record-holding location. Reading of additional records from the tape drive continues until a record is read having a length which is different from the length of the first-defined record length parameter value.

Abstract: A tape storage device is used in conjunction with a host computer to archive data. The storage device has interface logic that buffers blocks of data from the host computer in a memory buffer. The interface logic processes data as the data is received to create a processed data block that is smaller in size than the original, unprocessed data block. While receiving elements of the data block, the interface logic repeatedly determines the amount of free memory in the memory buffer, and temporarily suspends the block transfer whenever the amount of free memory falls below a predetermined threshold. The block transfer is resumed when the amount of free memory becomes equal to or greater than the threshold. This utilizes nearly all available memory, while preventing buffer overflow, without any need to perform complex calculations to predict the size of the data block after processing.

Abstract: A data transfer apparatus is provided for transferring data with a DMA method between a plurality of disk apparatuses and a memory using a DMA command table. A processor generates the DMA command table composed of an array of the DMA commands which are each composed of an address (starting address) of the data area and a size of data to be transferred. A disk access unit transfers data between the disk apparatuses and the memory using the DMA command table. When it is judged that the disk apparatus currently transferring data has temporarily released the bus use right, the processor, concurrently in preparation for the resumption of the data transfer, updates the DMA command table by deleting DMA commands having been executed and adding new DMA commands. This eliminates or reduces the generation of the table update interrupt.

Abstract: A data processing system (10) capable of burst transfers having an external bus interface (30) which allows termination of a burst transfer prior to completion of the burst transaction. The present invention offers a method of terminating a burst transaction without the addition of wait states, and further allows termination to effectively interrupt the burst transaction rather than waiting for burst completion. In one embodiment, on the negation of a burst request signal during a burst transfer, external bus interface (30) terminates the burst transfer without waiting for the completion of the burst transaction.

Abstract: A communication protocol employing dummy input and output values is used in communicating blocks of data between an industrial controller and its I/O modules while preventing premature use of partially transmitted data by the I/O modules yet without the need for special handshaking type circuitry or the continuous overhead of such handshaking protocols.

Abstract: The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level.