Abstract: A data transfer system including a data transmission unit and a data reception unit, the data transmission unit including an arithmetic unit which, when accepting an interruption during data transfer, suspends processing in execution and immediately switches to a mode for executing the interruption processing, and the data reception unit including a received data accepting unit for temporarily accumulating received data, a data storage unit for receiving and storing received data accumulated at the received data accepting unit after the data transfer processing is completed, and a transfer control unit for inhibiting processing of shifting received data accumulated at the received data accepting unit to the data storage unit when detecting suspension of the data transfer processing due to generation of an interruption at the data transmission unit.

Abstract: A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA), and having hardware features which cause each ASP to notify the microprocessor core (i.e., execution unit) when a data frame having a last data bit equal to a predetermined value is received. Such hardware features allow the execution unit to determine when complete data packets are received. Each ASP is adapted to receive serial communication data, and is configurable to generate an internal DMA request signal in response to the serial communication data. The serial communication data is transmitted within data frames, wherein each data frame includes multiple data bits transmitted sequentially between a start bit and one or more stop bits. The last data bit of the multiple data bits is transmitted immediately before the one or more stop bits.