Abstract: Techniques for enabling a virtual machine (VM) executing on a physical node to access a partition of a storage system are described. One embodiment associates an identifier with the VM for use when communicating with the storage system, wherein the identifier differs from a default identifier of a host bust adapter (HBA) usable by the physical node to communicate with the storage system.

Abstract: The invention broadly encompasses a system including a communications network, a plurality of remotely located data sources to provide power data, the power data including quantitative and qualitative data of one or more renewable energy power generation units, and a performance monitor in communication with the plurality of remotely located data sources through the communications network, the performance monitor including a data store to store the power data, and a power manager to manage generation of power from the one or more renewable energy power generation units.

Abstract: A display device that has multiple inputs for receiving video data and peripheral data from multiple computing devices, and an output for attaching a peripheral. The display is operable in one of two states, to provide both a video and peripheral signal paths between a selected one of the interconnected computing devices and the display's panel and attached peripherals. At any given time only one of the computing devices may utilize both the display and any attached peripherals. Exemplary embodiments may handle video and peripheral data streams received from a computing device over a single physical link.

Abstract: In an embodiment, a method of operating a zone manager of an input/out system includes, in response to a storage device being inserted into a particular storage-device location of the input/output system, determining whether the particular storage-device location and the storage device are assigned to a same server of the input/output system, and assigning the particular storage-device location and storage device to the same server in response to determining that the particular storage-device location and the storage device are not assigned to the same server.

Abstract: Managed access to one or more peripherals of a service terminal is provided. A master controller controls access to the peripheral(s) by applications of the service terminal, wherein only a single application can access the peripheral(s) at a time, by identifying an application of the applications for placing into an on-focus state in order to enable access to the peripheral(s) by the identified application, and placing the identified application into the on-focus state, where access to the peripheral(s) by the identified application is enabled. The remaining applications of the applications execute in an off-focus state in which the master controller simulates, for the remaining applications, connectivity to the peripheral(s), and in which access to the peripheral(s) by the remaining applications is disabled transparent to the remaining applications while the access to the peripheral(s) by the identified application is enabled.

Abstract: Exemplary method embodiments for hierarchy multi-tenancy support for configuration of a plurality of host attachment through a plurality of resource groups in a computing storage environment are provided. In one embodiment, multiple data storage subsystems are configured with multiple operators for configuration and management of multiple host attachments to multiple logical volumes. A logical operator is designated with the responsibility of designating authority to a host attachment operator and the ability to configure multiple logical volumes. Limited authority is provided for the host attachment operator to configure multiple volume groups and multiple host ports to a specific user.

Abstract: Exemplary system and computer program embodiments for hierarchy multi-tenancy support for configuration of a plurality of host attachment through a plurality of resource groups in a computing storage environment are provided. In one embodiment, multiple data storage subsystems are configured with multiple operators for configuration and management of multiple host attachments to multiple logical volumes. A logical operator is designated with the responsibility of designating authority to a host attachment operator and the ability to configure multiple logical volumes. Limited authority is provided for the host attachment operator to configure multiple volume groups and multiple host ports to a specific user.

Abstract: An I/O control system for controlling I/O devices in a multi-partition computer system. The I/O control system includes an IOP partition containing an I/O processor cell with at least one CPU executing a control program, and a plurality of standard partitions, each including a cell comprising at least one CPU executing a control program, coupled, via shared memory, to the I/O processor cell. One or more of the standard partitions becomes an enrolled partition, in communication with the I/O processor cell, in response to requesting a connection to the IOP cell. After a partition is enrolled with the I/O processor cell, I/O requests directed to the I/O devices from the enrolled partition are distributed over shared I/O resources controlled by the I/O processor cell.

Abstract: An input switching apparatus includes a plurality of AV signal input units; a communication unit that communicates with another AV device; an input selection unit that selects one of the plurality of AV signal input units; and a selection control unit that switches selection of the input selection unit in accordance with a switching request message for requesting switching of the input selection unit from an origin position to a destination position when the communication unit receives the switching request message. While the input position holding mode is activated, the selection control unit holds the selection of the input selection unit even when the switching request message is received, and transmits a message for causing another device to perform a switching from the destination position to the origin position.

Abstract: Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency and/or the latency window of a memory device such that a data signal and a data strobe signal are received by the memory device within the latency window of the memory device.

Abstract: Systems and methods for encoding/decoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word to be encoded using code words. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table.

Abstract: In a data processing system which runs a plurality of operating systems, a channel device can be shared by the plurality of operating systems. In addition, a channel device which supports port multiplexing can also be shared by a plurality of operating systems. The channel device includes a plurality of IDs each indicating that the channel device is a medium for performing input/output processing, and an input/output processing controller for assigning one operating system to each of the IDs, and controlling a data transfer independently for each ID to control a plurality of data transfers. Further, in a channel device which has a plurality of ports, an input/output processing controller is provided for assigning an operating system to each of the ports, and transferring data independently for each port to control the plurality of ports.

Abstract: A method and apparatus for resource management in a multicore processor is disclosed. A system management controller (130) provides omnipresent scheduling, synchronization, load balancing, and power and memory management services to each processing resource (150) within in a multicore processor (10), via a plurality of system management clients (120) implemented in hardware or software. The controller (130) allocates the tasks executing in each processing resource (150) by means of interrupt control signals, which interact directly with the system management clients (120), enabling processing resources (150) to autonomously create, execute and distribute tasks around a parallel system architecture whilst monitoring and policing the use of shared system resources (140).

Abstract: A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests to access the bus by a first bus master and one or more other bus masters. Accesses by the one or more other bus masters to the bus are restricted in response to a signal indicative of a change in a mode of operation of the RF circuit. In one particular implementation, a communication apparatus employs time domain isolation wherein the digital processing circuit may be placed in a shutdown mode when the radio frequency circuit is active.

Abstract: A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes programmed I/O (PIO) configuration registers corresponding to hardware resources, and a storage for storing a resource table that includes a plurality of entries. Each entry corresponds to a respective hardware resource. A system processor may allocate the hardware resources to functions that may include physical and virtual functions, and may program each entry of the resource discovery table for each function with an encoded value that indicates whether a requested hardware resource has been allocated to a requesting process, and whether the requested hardware resource is shared with another function. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.

Abstract: A method to adjust a multi-path device reservation by supplying a computing device and a storage controller interconnected with a communication link. The method further reserves a data storage device in communication with the storage controller, where that data storage device reservation is held by a first communication path group comprising a first plurality of communication paths configured in the communication link. If the method detects a failed communication path configured in the first communication path group, the method configures a second communication path group by removing the failed communication path from the first communication path group, wherein the second communication path group maintains the data storage device reservation.

Abstract: This document describes techniques (300, 600) and apparatuses (102, 106, 700, 800, 900) for peripheral authentication. These techniques (300, 600) and apparatuses (102, 106, 700, 800, 900) may configure data lines for authentication between host device (102) and peripheral (106), use these configured data lines to authenticate the peripheral (106), and then reconfigure the data lines for use. These techniques (300, 600) may also or instead transmit time stamps to a remote entity (402) for tracking peripheral use and/or present home screens (122) responsive to connection to a peripheral (106).

Abstract: A field device interface module includes a connector, a plurality of terminals, a protocol interface module, a controller and a power supply module. The connector is configured to operably couple to a computer. The terminals are operably coupleable to a field device. The protocol interface module is coupled to the plurality of terminals and configured to generate signals in accordance with a process communication protocol. A power supply module is coupled to the plurality of terminals. The controller is coupled to the protocol interface module and to the power supply module and is configured to measure a voltage across the plurality of terminals and selectively cause the power supply module to provide power to the field device.

Abstract: A system including a server apparatus executes an application program and a client apparatus enabling a user to utilize the application program by communicating with the server apparatus based on an instruction of the user. The server apparatus includes: an output detection section for detecting output-processing which is processing of outputting data from the application program into a shared area; and an output control section for storing instruction information in the shares area, instead of storing the output data outputted from the application program therein, in response to the detection of the output-processing, the instruction information specifying an acquisition method by which an authorized client apparatus acquires the output data.

Abstract: An electronic device includes a response-request transmitting unit and a response receiving unit. The response-request transmitting unit transmits a response request including an identifier of the response-request transmitting unit on a second network to an external device through a first net work. The response receiving unit that receives a response including an identifier of the external device on the first network, transmitted through the second network in response to the response request.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: In one embodiment, a computer-implemented method for creating redundant system configurations is presented. The computer-implemented method creates a set of virtual function path authorization tables, and receives a request from a requester to provide requested data from a virtual function wherein the virtual function is performed by a single root or a multi-root peripheral component interconnect device. Further a receive buffer is created in a selected address range in a set of addresses ranges as well as a virtual function work queue entry for the virtual function containing an address of the receive buffer in the selected address range. Responsive to a determination that the virtual function is authorized, writing the requested data into the receive buffer of the selected address range in the one or more systems, and responsive to writing the requested data, issuing a notice of completion to the requester.

Abstract: Various technologies and techniques are disclosed for improving performance of parallel scans. Disk head randomization that occurs when performing a parallel scan is minimized by assigning a worker entity to each disk involved in the parallel scan, and by ensuring data is only accessed on a respective disk by the worker entity assigned to the disk. A parallel scan can be performed that is NUMA aware by ensuring a particular sub-set of data is resident in the same memory node during each parallel scan, and by ensuring the particular sub-set of data is processed by a worker entity assigned to a node in which the sub-set of data is resident. A process for performing a parallel scan involves breaking up work into sub-sets, assigning work to each worker entity that corresponds to a respective disk, and having the worker entities process the assigned work to complete the parallel scan.

Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include sending a referral response from a first storage system included in a plurality of storage systems of the block storage cluster to the initiator system when data associated with the first I/O request is stored in more than one storage system of the plurality of storage systems of the block storage cluster. Additionally, the method may include directing a referral I/O to the first storage system and the second storage system for transferring data to or transferring data from the first storage system and the second storage system, and transferring data associated with the referral I/O to or transferring data associated with the referral I/O from the first storage system and the second storage system.

Abstract: One embodiment is a virtualized mobile device including virtualization software that supports one or more virtual machines and further includes: (a) device emulation software that communicates with device driver software in the one or more virtual machines; (b) device driver software that communicates with one or more physical devices of the mobile device; and (c) transformer stack software that interacts with the device emulation software and the device driver software.

Abstract: A data processing apparatus includes an arithmetic circuit and a peripheral device protection circuit that controls access of the arithmetic circuit to the peripheral devices. The peripheral device protection circuit has a first protection preset value and a second protection preset value set as a protection level higher than that of the first protection preset value. The peripheral device protection circuit includes: a setting selection circuit that generates access permission/denial information by referring to the first protection preset value and the second protection preset value when the arithmetic circuit operates at a first operation authority level, or by referring to the second protection preset value when the arithmetic circuit operates at the second operation authority level. An access protection circuit that determines permission/denial of access to the peripheral devices based on access information output from the arithmetic circuit and the access permission/denial information.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: Disclosed is a method and a SAS controller device that abstract access from one or more virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical devices may be replicated/cloned within the virtual ports. Each replicated/cloned SAS physical device may be assigned a unique SAS address for the SAS controller (i.e., unique for the SAS controller such that other replicates/clones on other virtual ports have a different SAS address).

Abstract: A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.

Abstract: A multi-processor system and a dynamic power saving method thereof are provided. The multi-processor system includes a plurality of processors and a chipset. Each of the processors has a plurality of standard bus request pins and a specific bus request pin, and the standard bus request pins of each processor are alternately connected to the standard bus request pins of other processors respectively. The chipset is coupled to the specific bus request pins of the processors for detecting a control request signal on the specific bus request pins. When the chipset detects the control request signal, the chipset turns on an input buffer connected with the processors so that the processors can access data through the input buffer. When the chipset does not detect the control request signal, the chipset turns off the input buffer.

Abstract: A method is provided for processing operation command in a computer that has a display and a host which includes a first display processing unit for local displaying and a second display processing unit for remote displaying. The operation command is from a remote data processing terminal. The method includes: receiving a first operation command from the data processing terminal, the first operation command being a power-on command; performing power-on of the computer, shielding the first display processing unit and loading only a driver of the second display processing unit according to first operation command; receiving a second operation command from the data processing terminal, the second operation command being not a power-on command; executing the second operation command to obtain operation results, the operation results being image data processed by the second display processing unit, and sending the operation results to the remote data processing terminal, for remote displaying.

Abstract: An aspect of the invention is directed to a method for storage I/O (input/output) path configuration in a system that includes a storage system connected via a network to a plurality of nodes. The method comprises receiving an I/O access to one or more storage volumes in the storage system from one of the nodes; if the I/O access is an initial I/O access to any of the storage volumes in the storage system from any of the nodes in the system, allowing the initial I/O access from the one node and prohibiting I/O access to the storage volumes in the storage system by other nodes in the system; and if the I/O access is not an initial I/O access to any of the storage volumes in the storage system from any of the nodes in the system, allowing the I/O access only if the I/O access is from the one node which made the initial I/O access and rejecting the I/O access for other nodes in the system.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: A method, computer program product, and distributed data processing system that enables host software or firmware to allocate virtual resources to one or more system images from a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, is provided. Adapter resource groups are assigned to respective system images. An adapter resource group is exclusively available to the system image to which the adapter resource group assignment was made. Assignment of adapter resource groups may be made per a relative resource assignment or an absolute resource assignment. In another embodiment, adapter resource groups are assigned to system images on a first come, first served basis.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: A storage apparatus 10 includes channel devices (each being CHA_PK 11) and microprocessors (each being MP_PK 12). CHA_PK 11 and MP_PK 12 respectively store therein control information being information designating logical volumes (LDEVs) 171 accessible by respective MP_PKs 12. Upon receipt of an I/O request from a management apparatus 20, CHA_PK 11 transmits, based on the control information stored therein, an I/O command to MP_PK 12 having an access right to a logical volume to which the I/O request is directed. In the storage apparatus 10, MP_PK 12 having received the I/O command from CHA_PK 11 judges based on the control information stored therein whether MP_PK 12 itself has an access right to the logical volume, and transmits the control information therein to CHA_PK 11 when judging that it does not have the access right, whereby the control information in CHA_PK 11 is updated.

Abstract: A multithreaded processor with a banked cache is provided. The instruction set includes at least one atomic operation which is executed in the L2 cache if the atomic memory address source data is aligned. The core executing the instruction determines whether the atomic memory address source data is aligned. If it is aligned, the atomic memory address is sent to the bank that contains the atomic memory address source data, and the operation is executed in the bank. In one embodiment, if the instruction is mis-aligned, the operation is executed in the core.

Abstract: Disclosed are a method and system of tracking real time use of I/O control blocks on a processing unit basis, in a multiprocessing system, such that in the case of a processing unit failure, a list accurately and concisely identifies the control blocks that need to be recovered. This eliminates the need to scan all the I/O control blocks, greatly reducing the overall system recovery time and minimizing impact to the rest of the running system. The preferred embodiment of the invention uses a task control block structure to record which I/O control blocks are in use by each Processing Unit. Also, the lock word structure defined in the I/O control blocks is provided with an index back into the task control block to facilitate managing the task control block entries.

Abstract: An arbitration logic including one or more modular priority encoders. Each modular priority encoder includes a first logic circuit, a comparator circuit, a second logic circuit, and an encoder circuit. The first logic circuit may be configured to generate a first output signal in response to a plurality of request signals. The comparator circuit may be configured to compare all possible pairs of a plurality of priority signals. The second logic circuit may be configured to generate a control signal in response to (i) the plurality of request signals and (ii) a result of comparing all possible pairs of the plurality of priority signals. The encoder circuit may be configured to generate a second output signal in response to the control signal.

Abstract: A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.

Abstract: A network apparatus is provided that is capable of requiring a reservation for an access right to a peripheral device that is not yet connected to the network apparatus from one of the terminals on a network. A server (network apparatus) may receive a reservation command and a sender identifier (ID) from one of the terminals on the network that requests to reserve an access right for a peripheral device that is not yet connected to the server. In a case where a new connection of a peripheral device is detected, the server allows the terminal identified by the sender ID that accompanied the reservation command to access the peripheral device. While the reservation is established, access to the detected peripheral device from senders other than the identified terminal is rejected.

Abstract: A mechanism is provided for locking an end device for the period of time that the device is needed, thus disabling access by any other application or process. Having the device locked, rather than the bus, allows other applications to use the bus to access other devices at the same time. This is achieved by providing a virtual bus arbitration, which arbitrates applications' use of the physical bus. The virtual bus arbitration algorithms allow bus operations from different applications to overlap on the physical bus as long as their target devices and associated bus locks are on different end devices.

Abstract: A computer design based on a platform of multiple central processing units (CPUs). When running multiple applications, each of the multiple CPUs performs all the processing for one of the individual applications. All of the multiple CPUs may operate below the physical layer of the OSI model. They may communicate with each other in a various manners, and they each communicate with a “gateway” CPU that is logically disposed above them on the physical level. The gateway CPU acts as a door or clearinghouse to and from the underground layer. The processing that occurs by the multiple CPUs on the underground layer allows a higher level of security, reliability, and speed compared to conventional single-CPU multitasking systems.

Abstract: A cellular phone. The cellular phone comprises a connector, a first memory module, a second memory module, and a controller. The connector is used for physically connecting the cellular phone to an external device. The first memory module stores phone data. The second memory module stores application data received from the external device. The controller determines whether the connector is connected to the external device. If the connector is not connected to the external device, access right of both the first and second memory modules is granted exclusively to the cellular phone. If the connector is connected to the external device, access right of the first memory is granted exclusively to the cellular phone, and access right of the second memory module is granted exclusively to the external device.

Abstract: A method and apparatus are described to provide shared switch and cache memory. The apparatus may comprise a message switch module, a cache controller module, and shared switch and cache memory to provide shared memory to the message switch module and to the cache controller module. The cache controller module may comprise pointer memory to store a plurality of pointers, each pointer pointing to a location in the shared switch and cache memory (e.g., point to a message header partition in the shared switch and cache memory). If there is a corresponding pointer, a memory read response may be sent to the requesting agent. If there is no corresponding pointer, a write data request may be sent to a corresponding destination agent and, in response to receiving the requested data, a pointer to the stored data in the pointer memory may be provided.

Abstract: A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator. Upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

Abstract: A data transfer device arranged in a node for connection in compliance with a communication standard. The data transfer device includes a request signal generation circuit for generating request signals defined by the communication standard with different levels of priority. A determination circuit determines the request signal having the highest level of priority. Priority is given to the transfer of data corresponding to the request signal determined to have the highest level of priority by the determination circuit. A top priority request signal generation unit generates a top priority request signal that differs from the request signals defined by the communication standard. The determination circuit includes a priority determination table in which the uppermost priority request signal is set to have a level of priority that is higher than the levels of priority of the plurality of existing request signals.

Abstract: A computer system that includes a plurality of servers, and a shared I/O subsystem coupled to each of the servers and to one or more I/O interfaces. The shared I/O subsystem services I/O requests made by two or more of the servers. Each I/O interface may couple to a network, appliance, or other device. The I/O requests serviced by the shared I/O subsystem may alternatively include software initiated or hardware initiated I/O requests. Different servers coupled to the shared I/O subsystem may use different operating systems, and each I/O interface may be used by two or more servers.

Abstract: A storage system that includes: a plurality of microprocessors; a plurality of storage areas to be formed to a drive group; an assignment section that assigns, to each of the microprocessors, an ownership of accessing any of the storage areas; a management section that manages, as an operating ratio, a proportion of a time to be taken for each of the microprocessors to execute a request issued to each of the storage areas; a search section that searches, for transferring the ownership assigned to an arbitrary one of the microprocessors to any of the another microprocessor determined based on the operating ratio, one or more of the storage areas under the ownership of the arbitrary microprocessor for a transfer-target storage area; and a transfer section that transfers, to the another microprocessor, the ownership of the transfer-target storage area that is assigned to the arbitrary microprocessor.

Abstract: An apparatus for providing I/O support to a computer system and a method of use thereof is disclosed. The apparatus in accordance with the present invention includes an internal control element located within the apparatus. The control element allows the apparatus in accordance with the present invention to relinquish ownership of the associated I/O devices for the purpose of being used by another computer. Accordingly, through the use of the apparatus in accordance with the present invention, expensive KVM switches and cabling, along with the accompanying I/O devices, are no longer needed to provide I/O support for computer networks. A first aspect of the present invention provides an apparatus for providing I/O support to a computer system. The apparatus comprises an I/O device and an internal control element coupled to the I/O device for relinquishing ownership of the I/O device from the apparatus to the computer network.