Abstract: A method for managing execution priorities in a multitasking operating system. The user sets execution priorities by the position of the application window on the screen relative to the other windows. When the user changes the position of the window, the system determines the new position relative to the other windows and reallocates the execution priorities based upon that window's new position. The allocation is done separately from the active window with which the user is currently interacting. In some instances, constraints may be placed upon the execution priority settings that prevent the system from exceeding certain maximums or going below certain minimums.

Abstract: It is provided a data storage device which reads data from and/or writes data to a memory medium, comprising: a storage unit for storing a first identifier; an identifier acquisition unit for acquiring a second identifier recorded on a memory medium which is set to said data storage device; and a controller for comparing said first identifier with said second identifier, and controlling to access to said memory medium for data reading and/or writing according to a relationship between said first identifier and said second identifier. For example, when the first identifier does not match the second identifier, the controller inhibits access to the memory medium for the reading and writing of data. But when the first and the second identifiers match, the controller permits access to the memory medium for the reading and writing of data.

Abstract: An input/output circuit in which a reset control circuit is provided in an NC board, and a logic circuit comprising a REG0 register and a REG1 register each for setting an object for reboot processing, two inverters, an AND gate, and an OR gate is provided in the reset control circuit. According to the setting in the registers, a reset signal RST* for starting reboot processing to the NC board while a PC control section is kept on operating is validated by the logic circuit. On the other hand the reset signal RST* is invalidated by the logic circuit when the reboot processing is executed to the PC control section.

Abstract: A reception apparatus or transmission and reception apparatus has a plurality of input terminals, and a plurality of apparatus are connected by a chain connection to a predetermined one of the input terminals. The input terminal at which the apparatus is to receive a signal is successively switched among the input terminals by selection operation of a user, and the apparatus connected to the predetermined input terminal are successively searched in response to the same selection operation of the user.

Abstract: A method and apparatus is provided for providing communication with input/output devices without being bound by the limitations of an existing input/output bus while still providing compatibility with software intended to communicate with input/output devices using the existing input/output bus. The software image of the input/output devices as being associated with the input/output bus is preserved, but a technique is provided to allow communication with the input/output devices to bypass the existing input/output bus. A translation lookaside buffer is utilized to remap accesses to an internal input/output device from virtual address space for input/output-bus-based input/output devices to physical address space for the internal input/output device. Circuitry for interfacing with the input/output devices separately from the existing input/output bus may be fabricated as a single integrated circuit device along with other system components, such as a central processing unit.

Abstract: A novel method and apparatus for managing communication transactions between electronic appliances is presented. The invention includes a source input/output (I/O) communications function which establishes a first communication link between the apparatus and a source appliance, and a destination I/O communications function which establishes a second communication link between said apparatus and a destination appliance. The apparatus stores and executes a communications program in program memory which manages communications transactions between the source I/O communications function and destination communications function.

Abstract: Disclosed is a method and device adapter for managing devices in a data processing system that includes a plurality of device adapters connected for independent communication with at least one shared device (e.g. disk data storage device). The method comprises the steps of: issuing a command from a first of the plurality of adapters to the at least one shared device; setting, in the first adapter, first and second timeouts associated with the command; on expiration of the first timeout value, issuing a message from said first adapter to other(s) of the plurality of adapters to request the other adapter(s) to notify the first adapter of any work requested of the shared device by the other adapter(s); and on expiration of the second timeout value, initiating a recovery operation in the data processing system.

Abstract: An apparatus and a method for connecting peripheral devices to each other in a computer supporting IEEE1394 are provided. An apparatus for connecting peripheral devices in a computer supporting IEEE1394 according to the present invention for connecting internal 1394 peripheral devices connected to 1394 physical layer ports in the computer supporting the IEEE1394 includes a controller for generating a control signal for selecting either the computer or the 1394 peripheral device using apparatus, external 1394 ports connected to 1394 connectors of the 1394 peripheral device using apparatus, and a switching unit for selectively connecting the internal 1394 peripheral devices to either the 1394 physical layer ports or the external 1394 ports in response to the control signal.

Abstract: The invention relates to a security lock for devices connectable to a computer bus. The devices receives from the computer information as to the owner of the computer, and compares the information it receives from the bus to information regarding the legitimate owner, which is permanently stored in the device. When the information received from the bus is different from the information stored in the device, the operation of the device is restricted. The invention prevents use of a device on a computer other than the one of the legitimate owner. It discourages theft of the device.

Abstract: A data storage device reads data from and/or writes data to a memory medium. The data storage device includes a storage unit for storing a first identifier, an identifier acquisition unit for acquiring a second identifier recorded on a memory medium which is set to the data storage device, and a controller for comparing the first identifier with the second identifier, and then controlling to access to the memory medium for data reading and/or writing according to a relationship between the first identifier and the second identifier. For example, when the first identifier does not match the second identifier, the controller inhibits access to the memory medium for the reading of data. But, when the first and second identifiers match, the controller permits access to the memory medium for the reading and writing of data.

Abstract: Various embodiments of the invention provide for selection of a port in a portable computer as a pathway for exchanging data between the portable computer and an external data source. These embodiments can function with a variety of physical accessories, such as docking port cradles and modems, that connect the portable computer with apparatus that include an external data source. Some of the embodiments provide methods that include the receiving of a request signal for data exchange, and determining whether the signal is from a physical accessory. If the signal is from a physical accessory, the portable computer exchanges data through the corresponding physical accessory. On the other hand, if the portable computer determines that the signal is not from a physical accessory, the portable computer exchanges data through a predetermined port, such as a default port, or a port specified by the user as a preferred port.

Abstract: A method of using bank tag registers in a multi-bank memory device to avoid background operation collision is described. A memory controller includes a plurality of bank registers, each of which is associated with one of a plurality of memory banks, wherein a bank register is arranged to store information, a bank number, a bank status, and a bank counter for a particular bank. The memory controller further includes an adjustable bank comparator coupled to each bank register. The memory controller receives an incoming system address request, which includes a requested bank number. The requested bank number is used to configure the adjustable bank comparator with the particular bank operating characteristics, to locate the bank register, and to determine the bank status and the bank entry status of the requested memory bank. The requested memory bank is accessed when the bank entry status identifies the requested memory bank as open.

Abstract: A new protocol of a standard game port for interfacing an external HSP modem, and game port devices is disclosed. The invention provides an external HSP modem housed in a compact case which includes a connector for mounting on a PC game port and a connector for coupling to a joystick and a MIDI interface. Inside the case, a bridge module is coupled to a modem module to forward the modem data input in response to a plurality of serial port clocks. The modem data input is then forwarded to an encode/decode module via multiple redefined read-only ports. The encode/decode module is on a sound chip for restoring the modem data input to their original formats. The restored data will be forwarded to a system bus for CPU to access via an HSP modem interface. The signal transmissions for the joystick and the MIDI I/O device are basically the same because the bandwidth of the game port is still enough if the modem, the joystick, and the MIDI I/O device are operated simultaneously.

Abstract: A method and apparatus for distributing input/output (I/O) operations among at least two paths in a multi-path computer system including a host computer, a system resource and a plurality of paths coupling the host computer to the system resource. For a next I/O operation to be assigned for transmission between the host computer and the system resource, a selection is made of one of the at least two paths for transmission of the next I/O operation based upon a state of previously assigned I/O operations queued for transmission over the at least two paths.

Abstract: A direct input/output port access device according to the invention which can control data accesses directly between an input port and an output port. The direct input/output port access device includes a local data bus which electrically connects the input port and the output port, an input/output port read/write controller and a data bus transceiver. In a direct input/output port access operating mode, the data bus transceiver is controlled by the input/output port read/write controller to electrically separate the local data bus from a system data bus. Simultaneously, the input/output port read/write controller generates can control data accesses directly between the input port and the output port according to read/write request status signals of the output port and the input port. At this time, a microprocessor can process other operations using the system data bus.

Abstract: Security is provided for a docking station. Within the docking station a docking password is stored. Upon a portable computer being attached to the docking station, a password stored in the portable computer is compared to the docking password. If the password stored in the portable computer is equal to the docking password, the portable computer is allowed to access the docking station. If the password stored in the portable computer is not equal to the docking password, the portable computer is prevented from accessing the docking station.

Abstract: In a network implemented based on IEEE 1394, when an HDD is connected to a personal computer via an IEEE 1394 connection unit and a GUID terminal connection unit, the HDD obtains a GUID via the GUID terminal connection unit. When the personal computer requests acquisition of an access right, the HDD obtains a GUID via the IEEE 1394 connection unit, and compares it with the GUID obtained via the GUID terminal connection unit, and since the GUIDs match, the HDD assigns an access right to the personal computer. Even if another personal computer not connected to the HDD via the GUID terminal connection unit, transmits a GUID to the HDD via the IEEE 1394 connection unit, because the GUID differs from that of the personal computer connected to the HDD via the GUID terminal connection unit, an access right is not assigned to the personal computer not connected to the HDD via the GUID terminal connection unit.

Abstract: In a small and thin memory module for sharing data among electronic devices such as information processing apparatuses, a write prohibit state can be visually recognized. A conductive seal is attached to a predetermined position on a support member, thereby setting the memory module in the write prohibit state. The conductive seal visually indicates the write prohibit state. When the memory module is mounted in a connector section of a card-shaped holder, connector pins are electrically connected to each other via the conductive seal. Thus, a write prohibit mechanism is realized at low cost.

Abstract: In a data communication apparatus provided with first and second digital interfaces respectively connectable to first and second external devices, communication (including synchronous communication and asynchronous communication) is conducted between the first external device and the first digital interface. When connection between the second digital interface and the second external device is detected, priority is given to communication with the second external device connected to the second digital interface. Preferably, the data communication apparatus causes the first external device to recognize the new connection configuration. As a result, the data communication apparatus can rapidly conduct data communication with a prescribed device without imposing a large load on the network.

Abstract: A data processing system and method are disclosed for protecting data stored on a device included within the system. A device key pair is established which identifies a particular device included within the system. The device key pair includes a device public key and a device private key. The device includes data stored on the device which may not be fully accessed initially. A planar key pair is established which identifies a planar board included within the system. The planar key pair includes a planar public key and a planar private key. The particular device is associated with the planar by storing the device public key only within the planar, and by storing the planar public key only within the device. Access to the data stored within the device is limited to only a planar which has the stored device public key.

Abstract: An apparatus and method which provide increased data flow through a compute platform by optimizing data flow between an external device and the internal circuitry without the need for user intervention. A port router is provided which includes a controller switch, a port switch, and one or more connections between the controller switch and the port switch. The controller switch, the port switch and the one or more connections are adapted to provide dynamic re-routing of connections between the port switch inputs and the controller switch outputs. A method is also provided for dynamically routing ports to internal circuitry of a compute platform.

Abstract: One aspect of the present invention provides a packer-unpacker (PUP) for a digital serial interface which allows a plurality of processors to access time slot registers of a serial data stream relating to the digital serial interface. A configuration register is maintained either by one of the plurality of processors or by each of the processors to arbitrate access to the individual time slot registers. Another aspect of the invention allows one or more processors to efficiently access and/or write more bits to a resource such as a time slot register than the width of the processor's respective data bus allows. Extra bits registers are maintained for at least one of the read and write direction data busses. The extra bits correspond to the least significant bits conventionally ignored in changing from a data bus of one width to a data bus of a narrower width. The extra bits in the write direction are accessed, e.g.

Abstract: A one-to-many bus bridge includes a system bus interface, a first I/O bus interface, a second I/O bus interface, a multiple logical FIFO system wherein first and second logical FIFOs share a common storage system, and demultiplexer and control circuitry. The demultiplexer and control circuitry are configured so that cycle information destined for the first I/O bus interface is enqueued from the system bus interface into the first logical FIFO and is dequeued from the first logical FIFO into the first I/O bus interface. Cycle information destined for the second I/O bus interface is enqueued from the system bus interface into the second logical FIFO and is dequeued from the second logical FIFO into the second I/O bus interface. A level-of-fullness monitor monitors the common storage system and generates first and second level-of-fullness indications responsive thereto. The system bus interface is operable to declare I/O halt and I/O resume conditions on a system bus responsive to halt and resume commands.

Abstract: In an operating system for facilitating the execution of a communication application typically comprised of a single port interface, a method for facilitating the interaction of the single port interface of the communication application with a plurality of hardware devices through the selection of corresponding and compatible port drivers is presented. A device driver router is designated as the port driver for the specific communication application. The port driver router functions as an intermediate device driver for evaluating conditions that exist among the possible target hardware devices. The device driver router initiates the loading of the determined port driver and hooks the responding port handle from the device driver. The device driver router modifies the port information structure of the device driver to enable the device driver router to perform the closing and unloading of the port driver.

Abstract: The present invention provides a cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus ports, the slave bus ports adapted to receive a plurality of slave buses; a manner of switching for selectively coupling the plurality of master bus ports to the plurality of slave bus ports; and a manner of configuration for prioritizing access requests by the plurality of master buses to the plurality of slave buses via the switching means. The cross-bar switch of the present invention has the capability of prioritizing requests between multiple parallel high speed buses. In a preferred embodiment, this arbitration is accomplished through Configuration Registers on the cross-bar switch. The Configuration Registers are programmable through the Device Control Register bus, which allows the cross-bar switch to be dynamically programmed and changed by a processor in a larger system.

Abstract: A data transfer system is constructed for transferring data by routing from primary nodes to secondary nodes through a plurality of channels. In the system, one primary node is comprised of a setup device, a backup device, a routing device and a transmitting device. The setup device automatically tries to secure an exclusive access to a default channel which is initially allotted to said one primary node when the same sets up the routing. The backup device alternatively secures an access to a substitute channel when the setup device fails to secure the exclusive access to the default channel due to conflict with another primary node which is allotted the same default channel. The routing device circulates a message directed to a secondary node to notify thereto the substitute channel secured by the one primary node in place of the default channel, and consequently establishes the routing between the one primary node and the secondary node.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set, and a device bus. A bridge control mechanism is configured to provide geographic addressing for devices on the device bus and to be responsive to a request from a device on the device bus for direct access to a resource of a processing set to verify that an address supplied by the device falls within a correct geographic range. A different geographic address range can allocated to each of a plurality of device slots on the device bus. A different geographic address range can also be allocated to the processor set resources (e.g., processor set memory). An address decoding mechanism maintain geographic address mappings, and verifies geographic addresses for direct memory access. The geographic address mappings can be configured in random access memory of the bridge. A slot response register is associated with each slot on the device bus.

Abstract: An integrated recorder system includes a recorder main part having a control unit which records instrumental data in a data memory, the control unit and the data memory being interconnected by a shared bus. A plurality of modules are arbitrarily inserted in or withdrawn from the recorder main part, the modules including an input module, the input module having a connector terminal from which an instrumental signal is supplied. A data interface unit is provided in the recorder main part and has a plurality of slots which connect the plurality of modules inserted therein to the data interface unit, the data interface unit being controlled by the control unit through the bus to read the instrumental signal from the input module when inserted in the recorder main part, such that the instrumental data is recorded in the data memory, and controlled by the control unit through the bus to transmit the instrumental data, recorded in the data memory, to an output module when inserted in the recorder main part.

Abstract: An IO controller device and method for controlling data flow, the method including determining a desired configuration for the IO controller, reprogramming the IO controller to allow for processing of one or more descriptor lists, modifying the configuration of the IO controller to reflect the addition or deletion of one or more virtual controllers, re-enumerating the IO controller, and processing a descriptor list for each of the IO controller and the one or more virtual controllers. The integrated circuit device for use as an IO controller includes a system bus interface, a programmable list processor and a port router. The integrated circuit device is adapted for reconfiguration to add or delete one or more virtual controllers. The virtual controllers provide substantially the full bandwidth supported by the integrated circuit device.

Abstract: A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that polls buffer descriptors when in idle mode. This polling is to determine whether the software has set up a buffer or group of buffers transmission and transfer ownership of those buffers to the DMA unit. To reduce interrupt latency and bandwidth occupation, the polling of these buffer descriptor ownership flags is staggered for the DMA channels. For example, if eight DMA channels are implemented, the polling of their buffer descriptors can be distributed throughout a 1.28 millisecond polling interval.

Abstract: A method and apparatus for processing pipelined command packets in a packefized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a “read” or a “write”) and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal.

Abstract: A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation—one which might affect the storage hierarchy as perceived by other devices within the system—is posted in the snoop queue of a remote snooping device. The flag remains set and is reset only when a synchronization instruction (such as the “sync” instruction supported by the PowerPC™ family of devices) is received from a local processor. The state of the flag thus provides historical information regarding architected operations which may be pending in other devices within the system after being snooped from the system bus. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered and additional system bus cycles made available for other purposes.

Abstract: An initiator device, in a data processing system utilizing a Serial Storage Architecture subsystem, directs an I/O process via secondary path if a primary path is unavailable, even if the primary path is shorter. Also, an initiator device may send outbound data frames, on a secondary path, simultaneously with the SCSI command. Additional flexibility is attained by utilizing an adapter and target storage devices that all support Out of Order Transfers ("OOT"). If a target supports OOT, individual data frames that comprise an I/O process may be sent on multiple paths, allowing greater flexibility in routing. Also, an initiator device may send outbound data frames, on an alternate path, simultaneously with the SCSI command.

Abstract: Apparatus for permitting any of a plurality of driver circuits to control a select lead. In the preferred embodiment, the plurality of drivers are in separate peripheral component interconnect (PCI) host bridges. The drivers when active are in one of two low impedance states. A resistor whose impedance is substantially less than the high impedance of a driver when in the inactive state is connected to ground and pulls the voltage on the select lead toward ground when none of the drivers connected to the select lead are active. Advantageously, a plurality of drivers can control a single select lead, and only a short time is required as a guard interval between the time that two different drivers control the select lead.

Abstract: An I/O device driver is shared between a number of processes within a computer system while security and protection for system memory is maintained. Controlled access to the I/O device is provided by managing an authorized list in an I/O processor which is used to keep track of users of the I/O device according to types of claims for access to the I/O device. Claim types include primary, authorized, secondary, and management.

Abstract: An input circuit for an input/output device adapted for use in a computer system in which a command includes information indicating an application program which initiated the command, the input circuit including a first-in first-out (FIFO) buffer circuit having a plurality of stages, each stage providing storage for commands from application programs including both data and an address for the data, a direct memory access circuit for transferring data between a buffer established in system memory by an application program and the FIFO buffer circuit, computer implemented software means for establishing a transfer buffer in system memory, circuitry for determining from a command which application program has initiated the command, and circuitry for assuring that commands from only one application program reside in the FIFO buffer circuit at any time.

Abstract: An apparatus for and a method of arbitrating a stream of access requests over multiple outputs. In one embodiment, the apparatus is implemented with D*[W+(N+1)log.sub.2 D] storage elements, where D is a maximum number of outstanding requests allowed by an issuing agent, N is a number of different request types, and W is a width of access requests measured in bits. The present embodiment comprises a main queue, an input address selection circuit coupled to the main queue for selecting storage locations to receive a stream of access requests, and a plurality of output address selection circuits coupled to the main queue for selecting storage locations to be read. Significantly, the input address selection circuit includes an input address list pointing to vacant storage locations in the main queue, and the input address list is updated each time an access request is stored in, or read out from, the main queue.

Abstract: A virtual connection created between an application program and a selected I/O device is used as a communications medium for controlling I/O processing of the I/O device by the application program. The virtual connection is implemented as a system area network connecting a process of the application program and the I/O device. The application program registers the application program's memory that the application program shares with the I/O device (i.e., gives access rights to the I/O device) with the system area network. Once the virtual connection is created and initialized, the application program uses the virtual connection to send request messages for I/O services to the I/O device and to receive reply messages from the I/O device. The I/O device uses the virtual connection to obtain source data from the application program's memory for I/O write operations and to transfer data to the application program's memory for I/O read operations.

Abstract: A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slots through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus.

Abstract: A system whereby a receiving module, in a mixed network of hardware and software-emulated modules, requires an Interrupt before it can use a Get Message OP to access a message from a message queue and which also provides a Fast Empty of messages in a message queue by eliminating the need for an Interrupt before each succeeding message access.

Abstract: A communication system is provided that includes a mechanism for selectively addressing memory banks depending upon the configuration of that system. The communication system can therefore operate in accordance with two possible modes of operation. According to a first mode, the local CPU can access one set of memory banks concurrent with an external device accessing the other set of memory banks. According to a second mode of operation, either the local CPU can access the memory banks or an external device can access the memory banks, one exclusive of the other. In one version of the second mode of operation, address signals to the memory banks can be physically connected leaving signals free to be used as general purpose input/output signals. The mechanism by which memory banks can be addressed and data transferred to and from those banks readily lends itself to communication applications to which the present system may be attributed.

Abstract: A system for allowing a peripheral device to be inserted directly into a port of a computer system while the computer system is powered on. The insertion of a peripheral device into the computer system port is automatically detected, and a configuration operation is automatically performed when insertion of the peripheral device is detected. The system also allows a plurality of peripheral devices to be connected to a single port of a computer system by automatically determining the number of peripheral devices and assigning a unique address to each of the peripheral devices. The peripheral device may have a host port for communicating with the computer system, a slave port for connecting to a slave device, and a device manager which identifies if a slave device is connected.

Abstract: Auto run apparatus, and an associated method, selectively permits execution of an auto run CD received at a CD ROM drive of a convergent device. When the auto run CD is received at the CD ROM drive, the operational mode of the convergent device is transferred to a computer mode. Thereafter, automatic execution of the CD is permitted.

Abstract: A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.

Abstract: DMA channel receive packet comparator logic (74) of PCI-interface ASIC (20) assigns a data packet (106) through a data communications channel and includes DMA channel comparator logic (110) for receiving at least a portion of an incoming data packet (108) in data comparison circuit (110). Data packet comparison circuit (120) compares at least a portion of incoming data packet (108) to a predetermined match data set (122). Packet portion (108) and the match data set (122) form programmably varying data fields (WD0, WD1) corresponding to at least one data communications channel (117, 119,121, 123). In the event of a predetermined correspondence between portion (108) and match data set (122), a channel select signal (117, 119, 121, 123) goes to a channel priority encoder (125).

Abstract: A method and system of message transfers in a multiple sender-multiple receiver network provides a specialized sequence for a Sender to acquire a message slot and place a message in a message queue, and a retrieval sequence for the Receiving module that insures message transmission integrity and proper chronological sequence of message delivery.