Abstract: In order to provide a solution for performing priority arbitration, a mask and reset-mask are generated in concert with a priority arbitration scheme. A plurality of requestors may issue requests for a shared resource. The priority arbitration scheme may grant access to a single requestor for a single priority assignment period. The mask may assist the priority arbitration scheme to assign priority to the plurality of requestors by temporarily removing a subset of the plurality of requestors for a particular priority assignment period. If the mask allows for no allowable requestors during the priority assignment period, a reset-mask scheme is implemented to reset the mask to permit an increased number of requestors access to the priority arbitration scheme.

Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.

Abstract: A communication apparatus which prevents one host computer from occupying the apparatus and enables a user of the host computer having sent a processing request thereto to quickly know a processing result. A connection request is accepted from one of a plurality of host computers. In response to the accepted connection request, the host computer having sent the connection request is connected, and a process requested by the connected host computer is executed. Information indicative of the connected host computer is stored. Control is performed such that a reconnection request from the host computer indicated by the stored information is accepted with priority over connection requests from other host computers.

Abstract: Methods and systems for migrating data between storage tiers may include various operations, including, but not limited to: determining at least one activity index of at least one data storage region; receiving an input/output request addressing at least one data segment included in the at least one data storage region; qualifying a data segment addressed by the input/output request for migration to at least one higher-performing storage device; and adding a data segment reference associated with a qualified data segment to a priority queue according to the at least one activity index.

Abstract: Interaction between a client and a service in which the service responds to requests from the client. In addition to responding to specific client requests, the service also anticipates or speculates about what the client may request in the future. Rather than await the client request (that may or may not ultimately be made), the service provides the unrequested anticipatory data to the client in the same data stream as the response data that actual responds to the specific client requests. The client may then use the anticipatory data to fully or partially respond to future requests from the client, if the client does make the request anticipated by the service. Thus, in some cases, latency may be reduced when responding to requests in which anticipatory data has already been provided. The service may give priority to the actual requested data, and gives secondary priority to the anticipatory data.

Abstract: Input and output (I/O) operations performed by a data storage device are managed dynamically to balance aspects such as throughput and latency. Sequential read and write requests are sent to a data storage device whereby the corresponding operations are performed without time delay due to extra disk revolutions. In order to minimize latency, particularly for read operations, random read and write requests are held in a queue upstream of an I/O controller of the data storage device until the buffer of the data storage device is empty. The queued requests can be reordered when a higher priority request is received, improving the overall latency for specific requests. An I/O scheduler of a data server is still able to use any appropriate algorithm to order I/O requests, such as by prioritizing reads over writes as long as the writes do not back up in the I/O queue beyond a certain threshold.

Abstract: An aspect of the invention is a storage networking system comprising subsystems coupled with a network. The subsystems include an initiator subsystem having an initiator I/O (input/output) control unit, and a plurality of target subsystems each having a target I/O control unit. The initiator subsystem is configured to: place priority information in packet address of an I/O command packet, the priority information being based on a priority table; send the I/O command packet to one or more of the plurality of target I/O control units; and receive a return I/O packet from each of the target I/O control units that received the sent I/O command packet, the return I/O packet having the same priority information. The priority information provided in the priority table is priority of storing I/O data. The I/O data is transferred according to the priority information placed in the packet address of the I/O command packet.

Abstract: Described herein is a system (102) having a virtualization and switching system configured to virtualize I/O devices (108) and perform switching of the I/O devices (108) and I/O requests. The virtualization and switching system (102) includes a peripheral virtualization controller (PVC) (204), at least one device control module (206) connected to the PVC (204), and at least one command parser (210). The PVC (204) is configured to manage I/O virtualization and I/O command access of different I/O devices (108). The device control module (206) is configured to store configuration and I/O device registers, implemented by the PVC (204) to enable virtualization of I/O devices (108). The device control module (206) also implements the I/O command and switching logic to perform graceful handling of the I/O commands and virtualized I/O devices between multiple host processors (104).

Abstract: Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.

Abstract: A method to adjust a multi-path device reservation by supplying a computing device and a storage controller interconnected with a communication link. The method further reserves a data storage device in communication with the storage controller, where that data storage device reservation is held by a first communication path group comprising a first plurality of communication paths configured in the communication link. If the method detects a failed communication path configured in the first communication path group, the method configures a second communication path group by removing the failed communication path from the first communication path group, wherein the second communication path group maintains the data storage device reservation.

Abstract: Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.

Abstract: A scanning apparatus and a method thereof include a scanning unit scanning a document and outputting a scanned result, at least one external storage unit detachably attached to the apparatus, at least one internal storage unit, and a controller detecting an attachment state of the external storage unit and storing the scanned result in one of the external storage unit and the internal storage unit according to the attachment state of the external storage unit. The scanning unit of the scanning apparatus is combined with a user scanning unit and a user printing unit into a combination apparatus, and the scanned result is printed in a printing apparatus spaced-apart from the scanning apparatus by a distance, thereby removing cables between the scanning or printing apparatus and a personal computer.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.

Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.

Abstract: In some embodiments, a method for supporting multiple devices on a high speed physical link may be described. An embedded device may assert a link request pin to request to transmit data on a multi-point communications link that may serve a plurality of embedded devices. A controlling device may receive the link request signal. When the controlling device finishes sending data on the link, it may address the plurality of embedded devices in a round robin format and may determine which device asserted the link request pin. The embedded device that asserted the link request pin may send an acknowledgement signal to the controlling device when it is addressed.

Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include sending a referral response from a first storage system included in a plurality of storage systems of the block storage cluster to the initiator system when data associated with the first I/O request is stored in more than one storage system of the plurality of storage systems of the block storage cluster. Additionally, the method may include directing a referral I/O to the first storage system and the second storage system for transferring data to or transferring data from the first storage system and the second storage system, and transferring data associated with the referral I/O to or transferring data associated with the referral I/O from the first storage system and the second storage system.

Abstract: A unique system and method for ordering commands may reduce disc access latency while giving preference to pending commands. The method and system involves giving preference to pending commands in a set of priority queues. The method and system involve identifying a pending command and processing other non-pending commands in route to the pending command if performance will not be penalized in doing so. The method and system include a list of command node references referring to a list of sorted command nodes that are to be scheduled for processing.

Abstract: Described embodiments provide a media controller for processing one or more data transfer requests received from at least one host device. The media controller includes a buffer to receive data of a data transfer request from a communication link and a command parser to generate one or more contexts corresponding to the data transfer request. The one or more contexts are stored in the buffer. At least one queue of the media controller includes a regular context queue for queuing regular-priority contexts, and a high-priority context queue for queuing high-priority contexts. A context manager coordinates processing of regular-priority contexts and high-priority contexts of the at least one queue based on context boundaries, wherein, when a context is processed at a context boundary, data corresponding to the processed context is data is transferred between the communication link and at least one of the buffer and the at least one storage media.

Abstract: The present invention relates to a playback apparatus, a method, and a program which can appropriately perform jump playback when content transmitted through a network is played back in real time. A terminal 3 receives stream data transmitted from a server 1, buffers the stream data, and plays back the buffered data. The terminal 3 has multiple buffers to allow content data of the positions of jump destinations that can be specified as a jump destination during jump playback to be pre-buffered in the multiple buffers. As a result, upon receiving a request for jump playback, the terminal 3 can start playback from a jump destination without delay, since the data of the jump destination has already been buffered. The present invention is applied to, for example, television receivers.

Abstract: A DMA transfer control device comprises: a DMA arbiter that performs DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits that control the DMA arbiter; a judgment unit and a transfer time calculation unit that calculates a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter that times the judgment time at a unit time interval, and a comparator that compares the judgment time at which a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter when an output of the comparator indicates that the judgment time is not earlier than the DMA transfer scheduled time. The efficiency of data transfer by dynamically controlling DMA transfer is performed.

Abstract: A data transmission method is provided, which includes: obtaining a current queue length of a queue corresponding to an output port; when the current queue length meets a back-pressure requirement, determining a back-pressure priority corresponding to the current queue length according to the current queue length and a mapping relationship between a preset queue length and the back-pressure priority, and generating back-pressure information, where the back-pressure information inhibits a line card from sending data with a data priority less than or equal to the back-pressure priority to the output port; and sending the back-pressure information to a line card.

Abstract: A method, apparatus, system, and computer program product for enabling out-of-band access to storage devices through port-sharing hardware. Providing out-of-band access to storage devices enables system management functions to be performed when an operating system is non-functional as well as when the operating system is active. Storage commands originating with a management service can be interleaved with storage commands issued by the host operating system. The host operating system maintains ownership and control over its storage devices, but management activities can be performed while the host operating system is operational.

Abstract: A system for processing routing according to priorities of logical interfaces is provided. The system includes a priority setting unit for setting priorities of a plurality of logical interfaces set in a physical interface, and a priority scheduler for determining a priority of a respective logical interface from an input frame, and for outputting the input frame to a driver queue of the physical interface when the input frame is output from a logical interface having the highest priority. Traffic burstiness caused by queuing can be reduced in a network routing system employing at least one logical interface.

Abstract: Shared memory device apparatus and related methods are disclosed. An example method includes obtaining memory operation commands. The memory operation commands are received by a command dispatcher in a same order as obtained by the queue arbiter from the host device. The example method further includes separately and respectively queuing the memory operation commands for each of a plurality of memory devices and dispatching the memory operation commands for execution. The example method also includes receiving the dispatched memory operation commands at a plurality of command queues, where each command queue is associated with a respective one of the plurality of memory devices. Each command queue is configured to receive its respective dispatched memory operation commands from the command dispatcher in a same order as received by the dispatcher and provide the received memory operation commands to its respective memory device in a first-in-first-out order.

Abstract: Methods, system and computer products for user-managed multi-path performance in balanced or unbalanced fabric configurations. Exemplary embodiments include a path priority selection method, including selecting a first I/O data path to be a highest priority path in a storage area network system, selecting a second I/O data path to be a low priority path, selecting an I/O threshold value, the I/O threshold value indicating that I/O data load is excessive, directing the load balance of I/O traffic to the first I/O data path, thereby placing the second I/O data path in a standby state, monitoring the first I/O data path, determining if the first I/O data path has reached the threshold value and performing a controlled failover of the first I/O data path to the second I/O data path when an I/O data load on the first data path has reached the threshold value.

Abstract: A multi-core SOC synchronization component comprises a key administration module, a thread schedule unit supporting data synchronization and thread administration, and an expansion unit serving to expand the memory capacity of the key administration module. The key administration module stores, distributes and manages keys. When the key is assigned to a data synchronization process, the key administration module supports the data synchronization process. When the key is assigned to a thread process, the thread schedule unit performs thread administration. The expansion unit is coupled to an external memory and able to expand the memory of the key administration module. When the keys are expanded or the internal memory is insufficient, the keys are stored in the external memory.

Abstract: Input and output (I/O) operations performed by a data storage device are managed dynamically to balance aspects such as throughput and latency. Sequential read and write requests are sent to a data storage device whereby the corresponding operations are performed without time delay due to extra disk revolutions. In order to minimize latency, particularly for read operations, random read and write requests are held in a queue upstream of an I/O controller of the data storage device until the buffer of the data storage device is empty. The queued requests can be reordered when a higher priority request is received, improving the overall latency for specific requests. An I/O scheduler of a data server is still able to use any appropriate algorithm to order I/O requests, such as by prioritizing reads over writes as long as the writes do not back up in the I/O queue beyond a certain threshold.

Abstract: Methods and systems for migrating data between storage tiers may include various operations, including, but not limited to: determining at least one activity index of at least one data storage region; receiving an input/output request addressing at least one data segment included in the at least one data storage region; qualifying a data segment addressed by the input/output request for migration to at least one higher-performing storage device; and adding a data segment reference associated with a qualified data segment to a priority queue according to the at least one activity index.

Abstract: An image display device that controls an external device and a method therefore are provided. The image display device includes an interface unit which is connected to an external device, a determining unit which determines whether another external device that has a control ownership of the external device exists, and a control unit which registers the control ownership of the external device if it is determined that the other external device does not exist. The external device is controlled by registering the control ownership.

Abstract: A balancing process between I/O processor groups of a non-uniform multiprocessor system enables spreading of I/O workload across multiple I/O processor groups on a group base as soon as the I/O processor group with maximum group utilization reaches a certain high limit together with other processor groups being utilized significantly lower. The additional balancing is decreased step by step again when a certain low utilization limit is reached or the workload becomes more evenly balanced between the I/O processor groups. Checking if increase or decrease of the balancing is required is done periodically, but with low frequency to not affect overall performance. The checking and balancing happens asynchronously in predefined intervals. This solves the problem that with an increasing number of I/O processors the handling of initiatives leads to increased cache traffic and contention due to shared data structures, which slows down the I/O workload handling significantly.

Abstract: Arbitration of IO accesses and band control based on the priority of virtual servers is enabled while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system includes a CPU, a memory, a hypervisor that generates plural virtual servers, and an IO controller that controls an IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.

Abstract: The present disclosure relates to a method for enabling a virtual processing unit to access a peripheral unit, the virtual processing unit being implemented by a physical processing unit connected to the peripheral unit, the method comprising a step of transmitting to the peripheral unit a request sent by the virtual processing unit to access a service provided by the peripheral unit, the access request comprising at least one parameter and an identifier of the virtual unit, the method comprising steps, executed by the peripheral unit after receiving an access request, of allocating a set of registers to the virtual unit identifier received, storing the parameter received in the register set allocated, and when the peripheral unit is available for processing a request, selecting one of the register sets, and triggering a process in the peripheral unit from the parameters stored in the selected register set.

Abstract: A method and apparatus for allowing a limited functionality Universal Serial Bus (USB) host controller to manage specific USB peripheral devices on a downstream facing USB port is provided. The port is also capable of dynamically interfacing to any USB compliant peripheral device, even one not supported directly by the limited capabilities of the host controller.

Abstract: Methods and apparatuses for delaying execution of input/output (I/O) requests for solid state drives are contemplated. Some embodiments comprise receiving I/O requests for a solid state drive and calculating amounts of time based on characteristics of the requests, such as differences of the logical block addresses (LBAs) of the requests. The embodiments may then delay responses by the solid state drive for the requests. Calculating the amounts of time and delaying the responses by the amounts of time may allow the solid state drives to emulate the responses of various types of hard disk drives. Some embodiments comprise an apparatus for delaying execution of the I/O requests for solid state drives. The apparatuses may have numerous modules, such as a request receiver to receive the I/O requests, a calculation module to calculate the amounts of delay times, and a delay module to delay the responses of the I/O requests.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests.

Abstract: An information processing apparatus includes: a processor configured to run an operating system; a plurality of storage devices connected to the processor; a detection module configured to detect a boot process for installing the operating system; a determination module configured to acquire device information from each of the storage devices and determine priority rank of the storage devices based on the device information when the detection module detects the boot process being originated from a device other than the storage devices; and a control module configured to install the operating system in a target storage device that is selected from among the storage devices, the target storage device having the highest priority rank determined by the determination module.

Abstract: A direct memory access (DMA) engine schedules data transfer requests of a system-on-chip data processing system according to both an assigned transfer priority and the deadline for completing a transfer. Transfer priority is based on a hardness representing the penalty for missing a deadline. Priorities are also assigned to zero-deadline transfer requests in which there is a penalty no matter how early the transfer completes. If desired, transfer requests may be scheduled in timeslices according to priority in order to bound the latency of lower priority requests, with the highest priority hard real-time transfers wherein the penalty for missing a deadline is severe are given the largest timeslice. Service requests for preparing a next data transfer are posted while a current transaction is in progress for maximum efficiency. Current transfers may be preempted whenever a higher urgency request is received.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to t

Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on a one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.

Abstract: A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.

Abstract: A data buffer device includes: a tag value generation circuit that generates a tag value; a first buffer that stores first priority data; a second buffer that stores second priority data; and a data output circuit that outputs the first priority data or the second priority data, wherein the tag value generation circuit sets a tag value for the following second input data to a second tag value which differs from a first tag value for second preceding input data, and sets a tag value of the following first input data to a fourth tag value that is the same as a third tag value for the first preceding input data, and wherein the data output circuit outputs the first priority data or the second priority data in a first mode based on the tag values and outputs the first priority data earlier in a second mode.

Abstract: A self programming slave device controller is described which comprises interface circuitry and control circuitry. The interface circuitry is responsive to one or more configuration parameters to communicate data between the slave device controller and a slave device in accordance with the one or more configuration parameters. The control circuitry is responsive to one or more operating parameter signals indicative of one or more operating parameters influencing current performance characteristics of the slave device to set the one or more configuration parameters so as to control an access operation for accessing the slave device to accommodate the current performance characteristics of the slave device. In this way, an access operation can be conducted efficiently and reliably having regard to the current performance characteristics of the slave device.

Abstract: A memory control apparatus generates a plurality of commands whose unit of data transfer is smaller than the unit of data transfer of a memory access request, and when the memory access requests are transmitted from a plurality of request sources, issues the plurality of commands to a memory in alternate order for each request source. The plurality of memory access requests are executed by time division and concurrently.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.

Abstract: A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.

Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.