Abstract: The invention relates to management of I/O in data storage systems. In an embodiment, the invention provides a data storage subsystem processing I/O requests each having a priority, comprising a processor, a memory coupled to the processor, a disk array, an array controller coupled to the processor and the disk array, a network interface, coupled to the processor, to receive an I/O request with a priority, and a program in the memory for managing the I/O request based on the priority, a clip level of the priority, the total workload in the data storage subsystem, and processing I/O requests based on priority, workload clip levels, and fairness levels. The invention also contemplates the use of static and dynamic adjusted clip levels.

Abstract: For use in a data storage system, a method of dynamically controlling accesses to and from the storage device array.

Abstract: A system and method for managing memory data is provided. Data stored within a main memory may be requested by multiple requesters that may include one or more cache memories. When the data is provided by the main memory to a requester, it will be provided in a state that is based on the way the data was recently used by the requesters. For example, if a pattern of read-only usage has been established for the data, the data will be returned to a requester in a shared state. If data that was provided in a shared state must be updated such that the requester is required return to main memory to obtain read/write privileges, the main memory will thereafter provide the data in an exclusive state that allows write operations to be completed. This will continue until a pattern of read-only usage is again established.

Abstract: A system is provided for switching the I/O channel for disk drives between multiple computers. The system incorporates the switch into removable drive modules, or a docking base for a removable drive module. The incorporation of switching into the system, such that it is integral with the drives, can reduce overall system failures, by reducing the number of elements which flow through a central switching element. Thus, even where a switch fails other drive modules of the system may continue to operate in the system and provide information to different computers of the system.

Abstract: A host channel adapter is configured for servicing received work notifications based on identifying the work notifications associated with the virtual lanes (VL) having a prescribed ordering position identified by the link layer operations. The host channel adapter, in response to receiving a work notification for a prescribed service level (SL), determines the virtual lane associated with the specified service level based on a prescribed service level to virtual lane mapping. If necessary (e.g., for an unreliable datagram service type), the work notification supplies the prescribed service level (SL) for the host channel adapter. The host channel adapter also determines an ordering position for the determined virtual lane from the link layer module, and selectively services the work notification based on the corresponding ordering position.

Abstract: Systems and methods for optimizing storage network functionality. The methods and systems of the present invention are particularly useful for optimizing storage network performance for cases in which some components of the network may be separated by significant distances and/or which include communication links with relatively limited bandwidth. In certain aspects, the present invention provides methods and systems for implementing access to and management of geographically distributed storage resources through multiple peer-to-peer storage network array management functions (AMFs) that may also be geographically distributed. The methods and systems of the present invention, in certain aspects, provide geographically aware cache sharing, cache replication, cache coherence, traffic routing, redundancy group structure, source and destination selection, pre-fetching of data, message gathering and other useful features.

Abstract: A hardware command queue for mass storage systems having a memory device. A plurality of entries are defined in the memory device, at least some of which are active entries. At least some of the active entries correspond to pending access commands and at least one entry is a head entry corresponding to an in-flight access command.

Abstract: Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media stream based on a sampling rate of the media stream. The mode of operation may be a wideband mode and/or a narrowband mode. Depending on the determined mode, the adaptive multimode media queue may be partitioned into a low band media queue and a high band media queue. A wideband media stream split into a high band and a low band is buffered into the adaptive multimode media queue wherein the high band is stored in the high band media queue, and the low band is stored in the low band media queue. The high band media queue and low band media queue may be a contiguous memory block within the adaptive multimode media queue. The received media stream, which may have different sampled data rates may be buffered within the partitioned adaptive multimode media queue.

Abstract: Disclosed a processes and an apparatus which relates to an improved technique for sharing a computer resource.

Abstract: A method for transmitting packets from a network computer onto a network. At least two data sets are received. A priority value is determined for each of the at least two data sets. A composite data set is composed comprising portions of the at least two data sets such that an amount of data from each of the data sets within the composite data set is based upon relative priorities between each of the at least two data sets. The composite data set is transmitted onto the network.

Abstract: A scheduling method and apparatus for use by a processor that controls storage devices of a data storage system is presented. The method allocates processing time between I/O operations and background operations for predetermined time slots based on an indicator of processor workload.

Abstract: A method for selectively inserting cache entries into a cache memory is proposed in which incoming data packets are directed to output links according to address information. The method comprises the following steps: a) an evaluation step for evaluating for each incoming data packet classification information which is relevant to the type of traffic flow or to the traffic priority to which the data packet is associated; b) a selection step for selecting based on the result of the evaluation step whether for the data packet the cache entry is to be inserted into the cache memory; c) an entry step for inserting as the cache entry into the cache memory, in the case the result of the selection step is that the cache entry is to be inserted, for the data packet the address information and associated output link information.

Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Abstract: There are two classes of scheduling policy: a first class in which a completion of data transfer requested by a data transfer request within a deadline for completing the requested data transfer, specified for the request, is a primary key factor in determining an order of processing, and a second class in which a reduction of amounts of mechanical actions of a storage device required in carrying out the data transfer requested by the request is a primary key factor in determining the order of processing. Data transfer requests with respect to the storage device are sequentially accepted. Each data transfer request is classified into the second class while the current time has not yet exceeded a time earlier by a certain time than the deadline. Each data transfer request is classified into the first class after the current time has already exceeded the time.

Abstract: Data shared by plural processes of a program are identified and identification information is affixed to the shared data. When the program is linked by a linker, only the shared data to which identification information is affixed are extracted and a shared data area is created for the shared data. During program execution, this shared data area is prevented from being and the main memory is referred to or updated or the cache is invalidated prior to access of the shared data area by the linker. An address of data in a processor is computed from an address of the data in another processor based on a specific expression.

Abstract: In a control apparatus for operating with program data, it is possible to alter the operation of a control circuit by rewriting the data of the program memory built in an LSI, with ease and at a low cost independently of the operation of the control circuit. For that purpose, the control apparatus includes a ROM, a SRAM, a means for writing data in the SRAM, a selection means for selecting the output from the ROM or the SRAM in accordance with the addresses supplied to the ROM and the SRAM, and a control means for outputting the addresses to the ROM and the SRAM and operating with the output from the selection means as program data.

Abstract: A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an on-chip bus to the contending transactions. In one embodiment, an integrated circuit includes the on-chip bus and a number of the subsystems interacting with each other through transactions across the on-chip bus.

Abstract: The network arrangement includes at least one common bus. An input member is connected to the common bus. An output member is connected to the common bus. The input member comprises at least one input contact defined with a unique identity. The output member comprises at least one output contact defined with a unique identity. The input member is adapted to receive an input signal through the at least one input contact. The output member is adapted to provide an output signal through the at least one output contact. The input member is arranged to generate an action signal transmitted over the buss from the input member to the output member. The action signal comprises an address corresponding to the unique identity of an output contact.

Abstract: A storage element pending command queue prioritization system using multiple pending queues each assigned to a particular RAID command type. Pending commands from each of the queues are organized in such a way that lower priority commands are guaranteed a fixed amount of storage element bandwidth. Storage element throughput is optimized by limiting higher priority commands to a maximum service level and processing lower priority requests with the added storage element bandwidth, allowing lower priority requests to exceed their minimum service levels.

Abstract: A clustered computer system includes a shared data storage system, preferably a virtual shared disk (VSD) memory system, to which the computers in the cluster write data and from which the computers read data, using data access requests. The data access requests can be associated with deadlines, and individual storage devices in the shared storage system satisfy competing requests based on the deadlines of the requests. The deadlines can be updated and requests can be killed, to facilitate real time data access for, e.g., multimedia applications such as video on demand.

Abstract: A method and system for arbitrating among memory access commands from clients seeking access to a DRAM or other memory, and an arbiter for use in implementing such method or system. When arbitrating among competing commands that include at least one command of the same read/write type as the current command, the arbiter selects a command of the same read/write type as the current command. In a wait mode, when arbitrating among a set of the commands that includes no command of the same read/write type as the current command, the arbiter prevents each command in the set from reaching the memory. Preferably, after operating in the wait mode for a limited time, the arbiter enters another arbitration mode in which it can select a command of the opposite read/write type as the current command. Preferably, the arbiter is implemented to be operable in any of multiple operating modes. For example, it can have separately programmable wait times for “read to write” and “write to read” situations.

Abstract: Systems and methods are disclosed for arbitrating requests from a plurality of clients requesting access to a shared real-time resource. In one embodiment, a plurality of sub-clients are aggregated into an aggregate client. At the aggregate client, access requests from the sub-clients are arbitrated to generate an aggregate request. An aggregate deadline is determined and access requests from the aggregate client and other clients are arbitrated using the aggregate deadline as the deadline of the aggregate client. In one embodiment, a critical instant analysis of the system is performed using the aggregate deadline as the deadline of the aggregate client. In another embodiment, a block-out counter is employed at an aggregate client to regulate the rate at which the aggregate client provides access requests to the shared resource.

Abstract: A buffer management system for cooperating with a packet based switching system is proposed. The purpose of this system is to reduce traffic congestion, ameliorate its effects, provide fairness to each data source, and to increase functionality while respecting advantageous system characteristics. Fabric output buffers include an arbitration function, a quality of service function, and are associated with individual routing tables. The system uses shallow logic that allows for single clock cycle operation even at high clock speeds. In order to provide for system control of bandwidth, sources with bandwidth practices counter to system interests are addressed. Where there is a conflict of sources over a resource, the buffer management system arbitrates traffic to resolve conflicts in a timely manner while fairly allocating traffic share using a weighted round robin arbitration scheme.

Abstract: A circuit generally comprising a plurality of read input registers, a read output register, a write input register and a plurality of write output registers is generally disclosed. The read input registers may be configured to buffer a first read signal received within a plurality of first transfers. The read output register may be configured to transmit the first read signal in a second transfer. The write input register may be configured to buffer a first write signal received in a third transfer. The write output registers may be configured to transmit the first write signal within a plurality of fourth transfers.

Abstract: Memory bandwidth may be enhanced by reordering read and write requests to memory. A read queue can hold multiple read requests and a write queue can hold multiple write requests. By examining the contents of the queues, the order in which the read and write requests are presented to memory may be changed to avoid or minimize page replace conflicts, DIMM turn around conflicts, and other types of conflicts that could otherwise impair the efficiency of memory operations.

Abstract: An interface circuit for interfacing one or more compute nodes to a mesh and for serving a wide range of MPP systems and a method for exchanging data between a first agent on an expansion bus and a second agent on a system bus through a bus bridge so as to maintain cache coherency with data cached by one or more agents on the system bus. Transaction requests are queued within the bus bridge, transactions are snooped on the system bus, and a record of pending transaction addresses is maintained. Issuance of a queued transaction having the same cache line address as a pending transaction is stalled until the pending transaction has been completed.

Abstract: A serial bus controller using a nonvolatile ferroelectric memory is provided. The memory controller structure using a nonvolatile ferroelectric register enables control of variable access time according to addresses when data are exchanged through a serial bus. In the serial bus controller according to an embodiment of the present invention, access latency time by addresses is programmed using a nonvolatile ferroelectric register, and address access time is differently controlled depending on the programmed access latency when data are exchanged between a master and a FRAM chip through a serial bus, thereby improving system performance.

Abstract: An apparatus comprising a shared memory and a multiprocessor logic circuit. The shared memory may be configured to store data. The multiprocessor logic circuit may comprise a plurality of processors and a message circuit. The message circuit may be configured to pass messages between the processors.

Abstract: The present invention allows program specific configuration of several physical or logical readers, or other I/O devices, by using a configuration tool and a reader access layer. In an example embodiment, a configuration tool allows, a specifying access rights and priority rights for each single reader in conjunction with each single program. A reader access layer communicates with each program directly, calls up the reader access list for the requesting program, checks the access rights and the priority order for the available readers and returns a response to the requesting program containing information for accessing the active reader with the highest available priority. It secures previously defined access rights and access priorities between readers and programs defined in the reader access list remain unchanged independently when new readers are added.

Abstract: In a disk control device arranged to include a CPU, a plurality of channel control units, a plurality of disk control units, a cache memory, and a data transfer integrated circuit communicably connected to the cache memory via a plurality of data buses, when receiving a request for access to the cache memory from any one of the CPU, the channel control units and the disk control units, the data transfer integrated circuit provides access to the cache memory by use of a certain number of one or ones of the data buses, which number is determinable in accordance with a transfer data length that is set in the access request.

Abstract: A method and system for scheduling multiple frames and packets that are queued for transmission over a link, and queued from a link for storing into main memory. It recognizes priorities, provides fairness, and guarantees forward progress of all users. This method and system provides a mechanism that achieves the objectives with a very small state machine. It takes advantage of the nature of the traffic to calculate priorities in parallel to frame transmission.

Abstract: A controller embeds a volatile memory, a plurality of application circuits and an arbiter. Each of the application circuits is capable of sending a request signal to request access the volatile memory and has a unique priority. When some of the application circuits send requests in a same period, the arbiter selects application circuits with higher priority among those application circuits such that the selected application circuits are allowed to access the volatile memory. The arbiter includes a plurality of arbiter modules and a main arbiter module. Each of the arbiter modules is assigned to a unique set of application circuits in the controller such that the arbiter modules can select higher priority application circuits in the corresponding sets at the same time. The main arbiter module further selects application circuits for accessing the volatile memory according to application circuits selected by the arbiter modules.

Abstract: A method for associating reliable datagram queue pairs with an underlying end-to-end context of a channel adapter is provided. The method comprises storing a reliable datagram domain (RDD) within the context of a reliable datagram queue pair (RD QP). The same RDD is stored within an end-to-end context (EEC). A partitioning key (P—key) is also stored within the EEC. The RDD cannot be accessed by consumer processes. In the case of incoming messages, the P—keys of the incoming data packet and EEC are compared. If P—keys match, then the RDD's of the RD QP and EEC are compared. If the RDD's match, the packet is processed normally. In the case of outgoing messages, the RDD's of the RD QP and EEC are first compared, and if they match, the P—Key of the EEC is inserted into the transport header of the data packet.

Abstract: A microprocessor prioritizes cache line fill requests according to request type rather than issuing the requests in program order. In one embodiment, the request types include blocking accesses at highest priority, non-blocking page table walk accesses at medium priority, and non-blocking store allocation and prefetch accesses at lowest priority. The microprocessor takes advantage of the fact that the core logic clock frequency is a multiple of the processor bus clock frequency, typically by an order of magnitude. The microprocessor accumulates the various requests generated by the core logic each core clock cycle during a bus clock cycle. The microprocessor waits until the last core clock cycle before the next bus clock cycle to prioritize the accumulated requests and issues the highest priority request on the processor bus.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: Disclosed is a system, method, and program for transferring data. Whether data is being transferred to physical volumes in peak mode is identified. If the data is being transferred in peak mode, whether a large chain of data is available for transfer to physical volumes is determined. If the large chain of data is not available, whether a small chain of data is available for transfer to physical volumes is determined. If the small chain of data is available, the small chain of data is transferred to physical volumes. Additionally, if one or more files that have ages greater than a steady state age threshold are available, the one or more files are transferred to the one or more physical volumes. If one or more files that have ages greater than a peak age threshold are available, the one or more files are transferred to the one or more physical volumes.

Abstract: Memory transactions are carried out in an order that maximizes concurrency in a memory system such as a multi-bank interleaved memory system. Read data is collected in a buffer memory to be presented back to the bus in the same order as read transactions were requested. An adaptive algorithm groups writes to minimize overhead associated with transitioning from reading to writing into memory.

Abstract: A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other threads to reclaim its queue node immediately (in the absence of preemption), or mark its queue node to allow reclamation by a successor thread.

Abstract: A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a load buffer for holding load access requests from the processor, and a memory control unit for processing access requests from the processor, from the store buffer and from the load buffer. The memory control unit may include prioritization logic for selecting access requests in accordance with a priority scheme and bank conflict logic for detecting and handling conflicts between access requests. The pipelined memory may be configured to output two load results per clock cycle at very high speed.

Abstract: Digital camera techniques improve the convenience of a live view display and the like. Image processing in a digital camera includes image processing (i.e., live view processing) for real-time display of a subject on a liquid crystal monitor and image processing performed on image signals followed by image capture for recording. Both the image processing is performed by a single common image processor. In image capture for recording, high-priority live view processing (Pc) is performed between writing (Pa) of image signals outputted from a CCD into memory and captured image processing (Pb). This shortens the time of not displaying a live view image, thereby preventing a shutter release opportunity from being missed and improving the convenience of a live view display.

Abstract: A bus arbiter for a group of masters and a bus access control method. An arbitration priority control section output basic priority data for each of the masters. An arbitration priority generating section is provided for each of the masters, and combines the basic priority data for the corresponding master with request indication data indicating existence or non-existing of a bus access request from corresponding master to generate arbitration priority data. An arbitration priority comparing section compares the arbitration priority data for the masters with each other to determine the arbitration priority data which has the highest priority, and outputs a comparison resultant signal containing data for specifying the master corresponding to the arbitration priority data with the highest priority. An arbitration result notifying section outputs a bus use permission signal to the corresponding master with the highest priority in response to the comparison resultant signal.

Abstract: A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding request table is implemented as a memory module for storing identifying information associated with commands received from multiple host devices, and a free pointers queue is maintained to track slots available in the outstanding request table. A command tracker state machine decodes incoming requests from hosts, monitors the execution by these commands by the ATA device, and updates the memory module to reflect completion of commands. Also disclosed is a storage system including an adapter of the present invention and ATA storage devices.

Abstract: A method and apparatus are provided for scheduling data for transmission over a communication link shared by multiple applications operating on a host computer. The apparatus incorporates multiple storage components, with each storage component configured to store descriptors of data having one of multiple priorities. Each descriptor identifies a location (e.g., in host computer memory) of a portion of data to be included in a packet transmitted over the communication link. The apparatus services each storage component in turn to retrieve one or more descriptors, identify their associated data, retrieve the data and prepare it for transmission. Each storage component has an associated weight, which may be proportional to the priority of data represented by descriptors stored in the component. A storage component's weight may indicate a portion of the transmission bandwidth or a maximum amount of data that may be scheduled for transmission each time the component is serviced.

Abstract: A method and apparatus for efficiently executing a read request issued from a host computer when write requests are cached in a cache memory.

Abstract: The present invention provides a method and system to select a valid entry in a deterministic pseudo-random approach. The method may randomly select one of numerous valid entries in order to ensure that no specific entry or set of entries is consistently ignored. Moreover, the method may be deterministic in order that the selection technique could be precisely controlled for purposes such as testing and predetermined selection.

Abstract: A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding request table is implemented as a memory module for storing identifying information associated with commands received from multiple host devices, and a free pointers queue is maintained to track slots available in the outstanding request table. A command tracker state machine decodes incoming requests from hosts, monitors the execution by these commands by the ATA device, and updates the memory module to reflect completion of commands. Also disclosed is a storage system including an adapter of the present invention and ATA storage devices.

Abstract: A method of handling memory read return data from different time domains includes determining a number of distinct memory device ranks. A time domain for each of the distinct memory device ranks is determined. A transaction is scheduled based on the time domain for each of the distinct memory device ranks so that at least one of data collisions and out-of-order data returns are prevented.

Abstract: In a write process through channels Ch1, Ch2, and Ch3, the deadline of each channel is set based on the transfer rate variable by the ratio of dummy packets to valid packets, and deadline information is written with write data on a disk. In a read process through a channel Ch4, the deadline is set according to the deadline information read with read data from the disk. Then, data is sequentially processed in order from the data having the earliest deadline. Considering the difference in transfer rate between outer and inner zones on the disk, a write zone is determined. When data is simultaneously recorded through the channels Ch1 and Ch2 on an ASMO in a groove-land record system, the data is sequentially recorded through the channel Ch1 on the groove and through the channel Ch2 on the land.

Abstract: A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from enhancing the response to SNOOP requests. To accomplish this, the system memory bus is provided separate and independent paths to the level two cache and tag memories. Therefore, SNOOP requests are permitted to directly access the tag memories without reference to the cache memory. Secondly, the SNOOP requests are given a higher priority than operations associated with local processor data requests. Though this may slow down the local processor, the remote processors have less wait time for SNOOP operations improving overall system performance.

Abstract: Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media stream based on a sampling rate of the media stream. The mode of operation may be a wideband mode and/or a narrowband mode. Depending on the determined mode, the adaptive multimode media queue may be partitioned into a low band media queue and a high band media queue. A wideband media stream split into a high band and a low band is buffered into the adaptive multimode media queue wherein the high band is stored in the high band media queue, and the low band is stored in the low band media queue. The high band media queue and low band media queue may be a contiguous memory block within the adaptive multimode media queue. The received media stream, which may have different sampled data rates may be buffered within the partitioned adaptive multimode media queue.