Abstract: The using circumstances of a control object device are detected, and controlling of the control object device is carried out on the basis of the detected result. Thereby, where control equipment in conformity to a fixed standard, control equipment not in conformity to a fixed standard, and a control object device are mixed in a network, there can be avoided inconvenience in which the respective control equipment control the control object devices simultaneously.

Abstract: Method and apparatus for transferring data between a host device and a data storage device having a first memory space and a second memory space. The first memory space employs a first command queue and a second command queue. The host issues access commands to store and retrieve data. The device stores commands in the first command queue and moves the commands to the second command queue. Write commands are removed from the first command queue and a message is sent to the host device to signal that the command has completed. Read and write commands are sorted at the second command queue for execution in an efficient order. Host transfer resources and disc transfer resources are utilized in such a way as to allow independent operation and to allow transfers using both sets of resources at once. More queue space is available for commands at the first command queue.

Abstract: The present invention is in the field of memory. More particularly, embodiments of the present invention can enhance an interface of a memory device by processing more than one request at a time.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.

Abstract: Methods and associated structure for improving storage system performance by reducing latency associated with communication medium transactions internal to a storage subsystem. In one aspect of the present invention, an I/O control element associated with a storage system transmits prefetch read requests to an associated storage element of the storage system in response to receipt of a host system request. This allows the storage element to commence data transfer to the I/O element in advance of the I/O element returning the data to the host system. Subsequent transfers of data from the storage element to the I/O element then overlap the transfer of data from the I/O element to the host.

Abstract: The present invention provides an apparatus and system for buffering data in a communication network with an arranged priority which enables traffic shaping. A cell buffer unit (600) is arranged with a plurality of queues (614) configured to store PDUs on-chip and off-chip. There are associated queues both on-chip and off-chip for each priority queue. A cell buffer controller (620) forwards PDUs to a predetermined priority queue and manages the transfer of PDUs off-chip when a priority queue on-chip is fully occupied. The controller (620) also manages the transfer of PDUs from the off-chip queue when the on-chip priority queue becomes less than fully occupied.

Abstract: A data transfer device which set an address of page as transfer destination and transfer data to the page. In the data transfer device to which the present invention is applied, an address and page length of a page are acquired on the basis of an address of a page table specified by a read command. Then, transfer information including the address of transfer source, transfer data length and address of transfer destination of data is set according to page element of page as transfer destination page. Then, it is judged whether the transfer destination page and other page form a continuous area. And if it is judged that the continuous area is formed, transfer information will be changed. Data transfer is effected on the basis of changed transfer information. That reduces the need to set the other area at the transfer destination and thus the transfer efficiency improves.

Abstract: The invention describes a system for and a method of creating and using dependencies to determine the order of servicing transaction requests in a multiple queue environment. When more than one outstanding transaction affects the same memory location, dependencies are established to ensure the correct sequencing of the competing transactions. In a preferred embodiment the dependency is configured to ensure that, as each request is inserted, other outstanding requests are checked to determine if the same memory location is accessed. If the same memory location is affected, a dependency is created which ensures the youngest queue entry which is present at the time the check is made occurs before the present outstanding request.

Abstract: A data transfer technique between a source port and a destination port of a transfer controller with plural ports. In response to a data transfer request (401), the transfer controller queries the destination port to determine if it can receive data of a predetermined size (402). If the destination port is not capable of receiving data, the transfer controller waits until said destination port is capable of receiving data (412). If the destination port is capable of receiving data, the destination port allocates a write reservation station to the data (403). Then the transfer controller reads data of the predetermined size from the source port (404) and transfers this read data to the destination port (405). The destination port forwards this data to an attached application unit, which may be memory or a peripheral, and then disallocates the write reservation station freeing space for further data transfer (406).

Abstract: A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per memory. The buses are interconnected by at least one bridge. A processor is connected to a bus, and the data processing device comprises at least one memory table specifying with which memory an exchange of a data item between a processor and the memory system must be effected.

Abstract: A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, a portion (42a) of the memory is connected directly to one of the requestors, such, as a host processor (10), so that high bandwidth transfers can be performed. A portion (42b) that is not selected to be in HOM mode can be accessed by other requestors or shut down to save power. The size (S1) of the portion of memory selected for HOM mode is selected to match the requirements of a given application and can be changed by writing a size value to a register.

Abstract: A method and apparatus for reordering memory requests for page coherency. Various data streams are frequently found in separate areas of physical memory (i.e. each data stream is found in a separate memory “page”). Because these requests from different streams become intermixed, a certain amount of latency results from the resulting page “breaks.” These page breaks occur when consecutive requests are from different data streams, requiring accesses to different memory pages. When several separate streams of data are requested by a client, page coherency between requests diminishes. A reordering device regains lost page coherency, thereby reducing the amount of latency and increasing overall system performance.

Abstract: Optimal command nodes are selected in a computing device having multiple command node queues by a method which identifies a command node in a first queue and determines if the identified command node collides with a command node in a second queue. If a collision between the identified command node and a command node in the second queue is determined, the collision is corrected and the identified command node then may be moved into the second queue. The second queue is then sorted according to a predetermined routine to select the optimal command node.

Abstract: An apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system. The apparatus includes a data buffer and a control unit. The data buffer includes a first plurality of storage locations each corresponding to one of a plurality of tag values. The data buffer may receive a plurality of data packets associated with the graphics transactions. The data buffer may also store the data packets in the storage locations according to tag values. The control unit includes a storage unit having a second plurality of locations. Each of the locations in the storage unit corresponds to one of the tag values and may provide an indication of whether a given data packet has been stored in the data buffer. The control unit may further determine an order in which the plurality of data packets is read from the data buffer.

Abstract: A clustered computer system includes a shared data storage system, preferably a virtual shared disk (VSD) memory system, to which the computers in the cluster write data and from which the computers read data, using data access requests. The data access requests can be associated with deadlines, and individual storage devices in the shared storage system satisfy competing requests based on the deadlines of the requests. The deadlines can be updated and requests can be killed, to facilitate real time data access for, e.g., multimedia applications such as video on demand.

Abstract: A computer system may include several client devices, a data network configured to transmit data packets between the client devices, a coherency mode storage unit configured to store an indication to control whether a given address packet is transmitted through the address network in a point-to-point mode or a broadcast mode, and an address network configured to transmit address packets between the client devices. The address network includes several address switches and implements a broadcast virtual network that transmits broadcast mode packets and a non-broadcast virtual network that transmits point-to-point mode packets. A first address switch is configured to select an address packet to output during each of several arbitration cycles and to prioritize selection of address packets in the broadcast virtual network over selection of address packets in the non-broadcast virtual network during a first portion of the arbitration cycles.

Abstract: A functional system comprises a set of functions (F) requiring access to a collective resource (RSRC). Such a system can be, for example, a data processing system comprising a plurality of processors requiring access to a collective memory. For reasons of cost it is desirable to guarantee a certain minimum access for one or more functions while a certain degree of flexibility as regards the access is maintained. For this purpose, the system comprises an interface (INT) adapted to implement an access scheme (AS) characterized by a plurality of states (S) passed through in a predetermined manner. A state (S) forms a possibility of access of a given length and defines an order of priority in accordance with which a function (F) can access the collective resource (RSRC).

Abstract: A system and methods are provided for resolving resource conflicts related to processing multiple media streams on a single media device. An audio/video (A/V) server is used to interconnect a plurality of media devices. A first multimedia program is routed from a first source device to a first destination device. The A/V server detects a conflict when a second source device attempts to route a second multimedia program to the first destination device. To resolve the conflict, the A/V server determines suitable media devices to process the second multimedia program. The A/V server may send the second program to a second destination device to process the second program in the same manner as the first destination device. Alternatively, the A/V server may send the second program to a destination device capable of recording the second program.

Abstract: A hardware command queue for mass storage systems having a memory device. A plurality of entries are defined in the memory device, at least some of which are active entries. At least some of the active entries correspond to pending access commands and at least one entry is a head entry corresponding to an in-flight access command. A physical target location is stored in each active entry and a computed servo distance value is stored in each active entry. A link list including pointers defining an execution sequence is stored with the command queue.

Abstract: A method for enabling a Q_key that is tamper proof from applications on a distributed computer system to protect selected network operations is provided. Applications and an operating system (OS) execute on the end nodes and each may access various network resources. In the invention, the network resources are configured for selective access by particular applications or OS. In a preferred embodiment, a control bit of a Q_key, which allows applications to authenticate their use of particular communication resources, i.e., the send and receive queues, is reserved and utilized to signal whether a particular application is allowed access to the resources. Setting the control bit to 0 allows the Q_key to be set by an application directly. When the control bit is set to 1, the Q_key cannot be set by an application and can only be set using a privileged operation performed only by the OS.

Abstract: Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media stream based on a sampling rate of the media stream. The mode of operation may be a wideband mode and/or a narrowband mode. Depending on the determined mode, the adaptive multimode media queue may be partitioned into a low band media queue and a high band media queue. A wideband media stream split into a high band and a low band is buffered into the adaptive multimode media queue wherein the high band is stored in the high band media queue, and the low band is stored in the low band media queue. The high band media queue and low band media queue may be a contiguous memory block within the adaptive multimode media queue. The received media stream, which may have different sampled data rates may be buffered within the partitioned adaptive multimode media queue.

Abstract: A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

Abstract: A method and system for detecting viruses on handheld computers. The handheld computer is in communication with a computer system having a virus detection program. The method includes reading data from the handheld computer and writing the data at least temporarily to a database on the computer system. The data is scanned for viruses with the virus detection program. The method further includes updating data on the handheld computer based on results of the scanning.

Abstract: A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation of transactions or of an input-output interface for transactions.

Abstract: In a first form, a method for managing requests in a disk array having a number of disks includes associating priorities with respective requests. A new request is processed, which includes determining a maximum priority for at least certain ones of requests received and comparing the priority of the new request to the maximum priority. Responsive to the comparison, a selection is made between i) categorizing the new request as a foreground disk operation and ii) categorizing the new request as a background disk operation. A selection is also made between i) working the new request on at least one of the disks and ii) placing the new request in a queue.

Abstract: A method and system of memory management incorporates multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data. A tree memory controller controls data read and write accesses to each of the banks in each of the channels. A bank queue for each bank in each channel keeps track of bank availability. When read or write requests are received at the tree memory controller, the controller checks the availability of each bank in a channel, identifies a first available bank, and executes the read request from the first available bank. In response to a write request, the controller blocks all read requests once it has confirmed that data to be written is complete for the selected memory word length. As soon as each bank queue for read requests is empty, the controller initiates burst mode transfer of the completed data word to all banks concurrently.

Abstract: An apparatus for reordering packet transactions within a peripheral interface circuit. The apparatus includes a source tagging unit and a control unit. The source tagging unit may be configured to generate a plurality of tag values each corresponding to one of a plurality of packet commands. The control unit may include a first storage unit including a first plurality of locations and a second storage unit including a second plurality of locations. Each of the locations corresponds to one of the plurality of tag values. Each of the first plurality of locations may provide an indication of whether a given tag value corresponds to a first packet command in a given data stream. A first given location of the second plurality of locations corresponds to the tag value indicated by the first storage unit and stores a tag value of a second packet command in the given data stream.

Abstract: A unique system and method for ordering commands to reduce disc access latency while giving preference to pending commands. The method and system involves giving preference to pending commands in a set of priority queues. The method and system involve identifying a pending command and processing other non-pending commands in route to the pending command if performance will not be penalized in doing so. The method and system include a list of command node references referring to a list of sorted command nodes that are to be scheduled for processing.

Abstract: A starvation avoidance mechanism for an input/output node of a computer system. A scheduler unit includes a first buffer circuit and a second buffer circuit. The first buffer circuit includes a first plurality of buffers for storing selected control commands received from a first source and the second buffer circuit includes a second plurality of buffers for storing selected control commands received from a second source. The scheduler further includes an arbitration circuit coupled to the first buffer circuit and to the second buffer circuit. The arbitration circuit may be configured to arbitrate between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit. The outcome of selected arbitration cycles may be dependent upon a number of times in which a control command from a given one of the buffers is blocked due to an unavailable destination.

Abstract: For using a plurality of files contained in one logical device with a plurality of processing systems, sharing of a data storage unit among the plurality of processing systems is realized without need for a host processing system to check use states of the files in a server storage unit. Information concerning extent (extent range) of an input/output processing request issued by a host processor is stored in a control memory incorporated in a control unit for allowing the control unit to make decision as to overlap of the extents of the input/output processings to thereby effectuate exclusive control on an extent-by-extent basis.

Abstract: Systems and methods for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir for reducing or eliminating device buffers is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given cycle to ensure that all devices will be serviced within a programmable time period. The data reservoir contains the data buffers for each channel of each device. A memory interface ensures that sufficient data for each channel is present in the data reservoir by making requests to a system's memory based on an analysis of each channel. Analysis factors include how much data is remaining in the data reservoir, how long will that data last, and how long until the channel will be analyzed again. Based on this analysis, a request is either made to the system's main memory, or the channel waits until it is evaluated again in the future.

Abstract: An integrated circuit architecture for multimedia processing. A single integrated circuit (IC) operates as a system or subsystem, and is adaptable to processing a variety of multimedia algorithms, whether proprietary or open. Hard macros, either analog or digital, can be incorporated. The IC can also contain audio/video CODECs to suit different standards, as well as other peripheral devices which may be required for multimedia applications. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

Abstract: A sectioned ordered queue in an information handling system comprises a plurality of queue sections arranged in order from a first queue section to a last queue section. Each queue section contains one or more queue entries that correspond to available ranges of real storage locations and are arranged in order from a first queue entry to a last queue entry. Each queue section and each queue entry in the queue sections having a weight factor defined for it. Each queue entry has an effective weight factor formed by combining the weight factor defined for the queue section with the weight factor defined for the queue entry. A new entry is added to the last queue section to indicate a newly available corresponding storage location, and one or more queue entries are deleted from the first section of the queue to indicate that the corresponding storage locations are no longer available.

Abstract: A method and apparatus for a mutiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of mutiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).

Abstract: In a method for adaptive arbitration of requests for accessing a memory unit in a multi-stage pipeline engine that includes a plurality of request queues corresponding to the stages of the pipeline engine, each of the request queues is assigned to one of a high-priority group and a low-priority group in accordance with an operating state of the memory unit. The request queues in the high-priority group are then processed prior to the request queues in the low-priority group.

Abstract: In the disclosed data transfer request processing scheme, data transfer requests with deadlines for completing requested data transfers are classified into first class data transfer requests and second class data transfer requests. Then, the processing of first class data transfer requests is scheduled according to a first scheduling policy in which a completion of data transfers requested by the data transfer requests within the deadlines specified for the data transfer requests is a primary key factor in determining an order of processing, while the processing of second class data transfer requests is scheduled according to a second scheduling policy in which a reduction of amounts of the mechanical actions required in carrying out data transfers requested by the data transfer requests is a primary key factor in determining an order of processing.

Abstract: An input/output control apparatus controls input/output requests from a host unit to a plurality of subordinate unit. A priority order managing section in the input/output control apparatus controls a priority order of the input/output requests based on priority orders of the input/output requests given by the host unit, for each of the subordinate units.

Abstract: A system and method that uses a pluggable preprocessor for monitoring a running job data stream that looks for header information to determine the appropriate queue for the job data stream. The data stream is then routed to the appropriate queue. The header information typically comprises a job name, an owner, and routing information. Thus, a print job will appear in the appropriate queue immediately while it is still being spooled. A job scheduler can trigger processing of the job when the processor is available and the job is ready for processing. This facilitates the handling of many jobs simultaneously segregated into their respective priority queues as soon as the clients send the jobs. Processing may then be serialized based on the processor load and job scheduling logic.

Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.

Abstract: A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.

Abstract: An apparatus comprising one or more storage elements. The one or more storage elements may be configured to switch an input/output between a first domain and a second domain in response to one or more control signals.

Abstract: Within one embodiment of the present invention, arbitration software operating on a computer is able to determine whether communication software utilizes the same serial communication (COM) port of the computer as a HotSync Manager. If they do use the same serial COM port, the present embodiment arbitration software shuts down the HotSync Manager, if its running, thereby enabling the serial COM port to be utilized for other purposes (e.g., wireless modem communication). However, if the present embodiment arbitration software detects a HotSync Request received via the serial COM port, it runs the HotSync Manager enabling a HotSync process to occur between (for example) a personal digital assistant (PDA) and the computer. Once the present embodiment arbitration software detects the completion of the HotSync process, it shuts down the HotSync Manager until it detects the next HotSync Request.

Abstract: Security systems for computers connected to networks transmitting packets are disclosed. One disclosed system includes a security agent and a local security device featuring a network hardware connector, a computer hardware connector, a flash memory and a microprocessor to perform a software instruction. The security agent closes the security device by altering a setting of a bit of the flash memory. Further disclosed is a firewall on a single chip for providing security to a network transmitting packets. The firewall includes a network hardware connector, a memory for storing a rule and a software instruction for examining each packet and a microprocessor. Preferably the rule is configurable by a user and the memory includes at least one displayable Web and Web server functionally for serving a Web page and accepting a command from a user such that said at least one rule is determined by the command.

Abstract: A data storage system includes one or more data storage devices, one or more bridges that are each coupled to a different associated data storage device and a bus interface that is connectable to up to four host data processors through an IEEE 1394a type of serial bus. Each bridge operates as an interface for the associated data storage device and allows each of the up to four hosts to log in to the associated data storage device simultaneously. Conflicting accesses to the associated storage device of a bridge are queued and processed by the bridge in the order they are received. In the preferred embodiment the data storage devices are ATA/ATAPI type hard disk drives.

Abstract: A system and method are provided for hard disk drive command queue ordering with locational uncertainty of commands. For each command in the hard disk drive command queue, an expected access time is calculated utilizing a probability distribution for a currently executing command and a probability distribution for a candidate command. A command in the hard disk drive command queue having a minimum calculated expected access time is identified. Then the identified command having a minimum calculated expected access time is executed. The probability distribution for a currently executing command represents an ending location distribution for the currently executing command. The probability distribution for a candidate command represents a starting location distribution for the candidate command.

Abstract: A buffer circuit for rotating outstanding transactions. A buffer circuit includes a buffer and a command update circuit. The buffer may be configured to store packet commands that belong to a respective virtual channel of a plurality of virtual channels. The packets may be stored in the buffer to await transmission upon a peripheral bus. Once a given packet is selected for transmission, a peripheral bus cycle corresponding to the given packet command may be generated upon the peripheral bus. The command update circuit may be configured to generate a modified packet command in response to receiving a partial completion indication associated with the peripheral bus cycle. The command update circuit may also be configured to cause the modified packet command to be stored within the buffer.

Abstract: A buffer circuit for a peripheral interface circuit in an I/O node of a computer system. A buffer circuit includes a first buffer and a second buffer. The first buffer may be configured to store a plurality of selected packet commands within a plurality of storage locations. The second buffer is coupled to the first buffer and may be configured to store a plurality of index values. Each index value corresponds to one of the storage locations in the first buffer. The buffer circuit further includes a write logic circuit that is coupled between the first buffer and the second buffer. The write logic circuit may be configured to successively read each of the plurality of index values from the second buffer and to cause a selected packet command to be stored in each storage location corresponding to each of the plurality of index values within the first buffer.

Abstract: A data transfer unit is provided which reliably receives the expedited command when the expedited command has arrived, and changes over the reception to receiving a general purpose command when no expedited command is arriving. The data transfer unit contains a data module having at least a command module, and first and second interfaces and first and second host control units. An expedited command output at an indefinite period from the first host control unit is fed to the data module through the first interface. The first interface is turned off and the second interface is turned on at all times when a general purpose command output at a predetermined period from the second host control unit is fed to the command module through the second interface. The first interface is turned on and the second interface is turned off by interface change-over signals of an active level fed to the data module just before the first host control unit produces the expedited command.

Abstract: An interface is disclosed for driving a printer to print highly secure vouchers and less secure coupons. The printer can reside, for example, in a wagering terminal (e.g., slot machine), ticket machine, point-of-sale terminal or the like. A first driver receives, e.g., from a local controller, data indicative of voucher information to be printed. A second driver receives, e.g., from a central system controller, data indicative of coupon information to be printed. A processor responsive to the first and second drivers generates printer commands in a standard printer format so that the same printer can be used to print vouchers and coupons. Coupons do not have to be processed by the secure (and usually proprietary) hardware and/or software provided by the terminal manufacturer for printing vouchers.

Abstract: Disclosed is a method, system, program, and data structure for queuing requests. Each request is associated with one of a plurality of priority levels. A queue is generated including a plurality of entries. Each entry corresponds to a priority level and a plurality of requests can be queued at one entry. When a new request having an associated priority is received to enqueue on the queue, a determination is made of an entry pointed to by a pointer. The priority associated with the new request is adjusted by a value such that the adjusted priority is associated with an entry different from the entry pointed to by the pointer. The new request is queued at one entry associated with the adjusted priority.