Abstract: This invention discloses a data access device for using in computer of power off status, which comprises a power multiplexer, a DC to DC converter, a serial bus signal to storage interface signal controller, a data storage interface signal multiplexer, and a controller. Therefore, if controller detects an external device wants to access data storage device of computer at power off, it will control power multiplexer to retrieve the standby power of the power device and process power transformation to provide a required power for driving the storage device, and by using serial bus signal to storage interface signal controller, external device can access the data from storage device at power off.

Abstract: A media sharing apparatus includes a plurality of connecting ports for connecting with a plurality of computing devices. A KVM switch connecting with a drive is coupled to the media sharing apparatus. A system firmware has an emulating function for emulating said drive to said computing devices and has a command program and an access program of this drive.

Abstract: A bidirectional repeater and data multiplexer for serial data has A-side 12C port devices A1-A4 coupled to comparators 302-308 and pull-downs to ground 316-322. Comparator outputs are coupled responsive to select lines S1-S4 of N:1 Select 310 to terminal A1 of bidirectional control 210 to control pull-down to non-zero low voltage Vp 206 at B-side device B. An inverting comparator 208 coupled to terminal B1 of bidirectional control 210 responds to input threshold voltage Vt less than low voltage Vp, to prevent data lockup due to data flowback to devices A1-A4. Output data from comparator 208 is coupled responsive to select lines S1-S4 of 1:N Select 312 to control pull-downs 316-322. This selectively repeats routing of device A1-A4 data to device B. Data from device B is selectively routed to pull-downs of devices A1-A4.

Abstract: A computer server system comprises multiple computer server units, each computer server comprising a server processing system. Each computer server comprises a local subsystem access module which is standardized for the multiple computer servers and which provides virtual control function for a single instantiation of a hardware resource of the computer server system, wherein the hardware resource is shared between each of the computer servers.

Abstract: Single and dual ported devices are interfaced to a system via a 2:2 multiplexing device. The multiplexing device is coupled to two system ports and two device ports. The multiplexing device includes an active multiplexer coupled to the two system ports and a multiplexed port. The multiplexing device also includes bypass circuitry coupled to the two system ports and two bypass ports. In operation, when the multiplexing device is coupled via one of the device ports to a single ported device such as a single ported disk drive, the active multiplexer is activated and the bypass circuitry is deactivated and the multiplexed port is coupled to the device port. When the multiplexing device is coupled via both device ports to a dual ported device, the active multiplexer is deactivated and the bypass circuitry is activated and the bypass ports are coupled to the two device ports.

Abstract: The present invention relates to a module with isolated analogue inputs for programmable controller, the said module comprising several input pathways that are each isolated with the aid of at least one optical isolation static relay (1a-4b) controlled selectively with the aid of control means (6), the said module being characterized in that it comprises a multiplexer (5) furnished with several channels (5a-5h) each controlled to open or to close, a channel of the multiplexer (5) being placed in series with an isolated input pathway (1-4) of the module.

Abstract: A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability.

Abstract: The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by t

Abstract: The invention relates to a system-on-chip apparatus (1), comprising at least two electronic components (2, 3) serving for special purpose functions and a system bus (7) and at least one random access memory (9) that is integrated into the first electronic component (2), located in common on one substrate (8), wherein the system bus (7) connects the electronic components (2, 3) and wherein the random access memory (9) of the first electronic component (2) is time shareable to the second electronic component (3) via said system bus (7), and to a method for operating such a system-on-chip apparatus (1).

Abstract: A bidirectional repeater and data multiplexer for serial data has A-side I2C port devices A1-A4 coupled to comparators 302-308 and pulldowns to ground 316-322. Comparator outputs are coupled responsive to select lines S1-S4 of N:l Select 310 to terminal A1 of bidirectional control 210 to control pulldown to non-zero low voltage Vp 206 at B-side device B. An inverting comparator 208 coupled to terminal B1 of bidirectional control 210 responds to input threshold voltage Vt less than low voltage Vp, to prevent data lockup due to data flowback to devices A1-A4. Output data from comparator 208 is coupled responsive to select lines S1-S4 of 1:N Select 312 to control pulldowns 316-322. This selectively repeats routing of device A1-A4 data to device B. Data from device B is selectively routed to pulldowns of devices A1-A4.

Abstract: A method and computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.

Abstract: Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on a signal path by a transmitting component. The one or more null frames transmitted prior to the sync frame results in a settling of the signal path prior to reception of the sync frame, thereby lessening or removing the effects of previously sent data on the sync frame.

Abstract: A design structure comprising a schematic structure of an apparatus configured to implement commands in an input/output (IO) hub comprising a programmable command generator having an input coupled to an external interface and an output providing commands. The programmable command generator selectively couples commands in a path between a front end of the IO hub and an IO hub logic address and command routing output.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.

Abstract: A multi-media KVM switch is for providing an output signal to drive a user-interface output device. The multi-media KVM switch comprises an embedded multi-media system, an arbiter and a multiplexer. The embedded multi-media system is enabled as receiving an enabling signal and providing a first device signal. The arbiter is for determining an operational state of at least a computer system in response to a second device signal,outputted by the at least computer system. The arbiter provides the enabling signal to enable the embedded multi-media system when the at least a computer system is in a standby or an off state, and the arbiter is further for providing a selection signal. The multiplexer is for receiving the first and the second device signals, and outputting one of the first and the second device signals as the output signal to the user-interface output device.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: Mechanisms for configuring an integrated circuit to select one of multiple external device interfaces at a time to use during communication with external devices. The integrated circuit includes a control mechanism, a selection mechanism, and a plurality of external device interfaces. The plurality of device interfaces allow the integrated circuit to communicate with various external devices that support different communication protocols. The control mechanism is configured to designate the selection of one of the plurality of device interfaces for use in communicating with an external device. The control mechanism makes use of the selection mechanism to select the designated device interface to communicate with using the communication protocol supported by the selected interface. The communication may be receiving data from the interface or providing data to the interface. Non-selected interfaces are put in an inactive state.

Abstract: A architecture for a multifunction peripheral to service a plurality of clients simultaneously. A shared memory receives data from the plurality of clients. A channel multiplexer selects data to be routed to a peripheral, a SCSI emulator is used to logically select the peripheral. The data is then forwarded from the multiplexer via the SCSI emulator to a PCI bus, the PCI bus being physically connected with the peripheral's engine. When data needs to be sent from a peripheral to a client, it is forwarded from the PCI bridge to the SCSI emulator and routed via a demultiplexer to the shared memory wherein it is retrieved by the appropriate client. The multifunction peripheral can be interrupted while performing a first task using a first peripheral, switch to a second task needing a second peripheral, and return to the first task when completed.

Abstract: Protocol multiplexer is configured to receive multiple communication links, each link operating with one of a plurality of communication protocols. Protocol handler converts the received data and frames the data according to the communication protocol in use for a particular communication link. Port multiplexer separates the received frames into data frames and control frames. The data frames being multiplexed onto a single data bus and the control frames being multiplexed onto a single control bus to increase performance of the protocol multiplexer.

Abstract: A technique for improving the signal/register density for fixed address space devices is disclosed.

Abstract: A control circuit receives an external control signal in synchronism with an internal clock and generates an address signal and internal control signals. A data multiplexer has a plurality of input parallel lines and a plurality of output parallel lines and is switched to one of a first output state and a second output state in accordance with the internal control signal. In the first state, the data multiplexer outputs parallel data, which is input to the plurality of input parallel lines and read out from the memory core unit, to the plurality of output parallel lines corresponding to the plurality of input parallel lines. In the second state, the data multiplexer selects 1-bit data of the parallel data input to the plurality of input parallel lines and outputs the 1-bit data to the plurality of output parallel lines. A conversion circuit converts the parallel data into serial data.

Abstract: A display controller is provided. The display controller is configured to provide an indirect addressing mode to access a memory location within the display controller. The display controller includes a first pin configured to enable access to one of a register of the display controller or a memory region of the display controller based upon a logical level of a first signal received by the first pin. A second pin is included. The second pin is configured to define the access to the register or the memory region as one of address information or data based upon a logical level of a second signal received by the second pin. The display controller includes an extra pin mode module configured to enable the first signal to select the data to access memory without accessing a register block. A device and methods for implementing an indirect addressing mode is also provided.

Abstract: Digital circuits and methods for designing digital circuits are presented. In an embodiment, a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected. A clocking rate (C) is selected for the digital circuit such that a product (P), P being equal to B times C, is equal to at least 1 gigabit per second. An initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P is formed. This initial circuit includes a feedback loop having N+1 delays. N is a whole number greater than zero. The initial circuit is unfolded by a factor of B to form B parallel processing pipelines for the bits of the bit-stream. An N-step look-ahead network is formed to provide inputs to the B parallel processing pipelines. The unfolded circuit is retimed to achieve the selected clocking rate (C).

Abstract: A programming path selection apparatus for programming path selection is disclosed. The apparatus for selecting a programming path to one of a plurality of target modules for programming data. The programming path selection apparatus comprising: a multiplexer, coupled to a data programming apparatus and the target modules, for receiving a first control signal to select one of the programming paths as a desired programming path; and a micro processor, coupled to the multiplexer, for generating the first control signal to control the multiplexer.

Abstract: A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.

Abstract: A switch control system has a switch device for selecting a real input device or an emulation input device, an instruction detecting device electrically connected to a computer system and the switch device for detecting signals transmitted to the switch device, and a control device electrically connected to the switch device and the instruction detecting device for receiving a detecting signal from the instruction detecting device and for outputting a control signal to trigger the switch device and to control the selection of the switch device.

Abstract: A processor includes a core for providing speed reduction in communications between a transmission media and a processor having an upper link layer in a parallel-serial architecture. The core includes a lower logic layer, serial lanes connecting the logic layer to the transmission media, at least one selector connected to the serial lanes for supporting at least two differing data widths. The logic layer controls the selector, and multiple buffers are interposed in the serial lanes. The selector enables the speed reductions is the upper link layer of the processor. The processor is particularly applicable to interface components used in InfiniBand-type hardware.

Abstract: A circuit structure and signal encoding method for a serial ATA external physical layer is provided. The circuit structure and signal encoding method thereof is capable of reducing the number of interface signals of a serial ATA external physical layer, essentially comprising a decoder/encoder, a serializer/deserializer, a phase locked loop, at least one transmitter, at least one receiver, and at least one OOB signal detector, encoding various control signals and various status signals, required for the connection between the decoder/encoder and a storage medium controller, into data signals using signals other than a data conversion requirement of 8 bits and 10 bits, by the decoder/encoder, in order for greatly reducing the number of interface signals required for the connection between the external physical layer and a main control chip.

Abstract: An intelligent, modular server management system for coupling a series of remotely located computers to one or more user stations allowing for selective access of the remotely located computers. A centralized computer matrix switching system is provided to enable a computer user station to access and operate a remotely located computer in a stable environment and transmit analog signals through the switching system over an extended range. The centralized computer matrix switching system receives the input from the computer user station or the remotely located computer, including the keyboard, video monitor and mouse signals, and transmits the signals as though the computer user station was directly coupled to the remotely located computer.

Abstract: A method and apparatus are described for flow control for digital signal processing to support data stream operations. According to an embodiment of the invention, a method comprises setting a buffer number to an initial value; receiving a first data packet for processing during a first part of a first time frame, the data packet having a first data size; increasing the buffer number by an amount of data that can be passed to a coder; comparing the buffer number to a minimum amount of data for the coder; and setting a second data size to be received based on the comparison between the buffer number and the minimum amount of data for the coder.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer.

Abstract: A system and method for efficient transfer and buffering of captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to access the data event buffer to process the captured data events without the DMA transfer operation being stopped. In response to the region being filled, the DMA transfer engine may perform the DMA transfer operation to a different region of the data event buffer without the DMA transfer operation being stopped.

Abstract: A system and method for real-time processing of nondeterministic captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to retrieve captured data events from the data event buffer and to display the retrieved data events substantially in real time with respect to the occurrence of the corresponding captured data events on the nondeterministic data bus.

Abstract: Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer register to the FIFO. Each pointer register is associated with a primary shadow register and a secondary shadow register. The primary shadow register is located in the same sub-assembly as the pointer register with which it is associated, and episodically receives a copy of this pointer register. The secondary shadow register is located in the other sub-assembly, and episodically receives a copy of the primary shadow register. Thus, each system has its own pointer register, its associated primary shadow register, and the secondary shadow register associated with the pointer register of the other system.

Abstract: The present invention, a multiprocessor chip pervasive command interface, collects different types of pervasive commands into individual queues for each command type. As permitted by various grouping rules, valid commands are grouped together into one single command and placed on a functional interchip communications bus. This grouping of commands maximizes pervasive command bandwidth while the use of the functional bus minimizes the number of interchip connections.

Abstract: A system and method for configuring expandable buses wherein a host supports a plurality of expandable buses are provided. A plurality of devices are arranged to form a plurality of groups. Each group forms a chain of devices on an expandable bus. Each chain includes an input connector. The chains are configured such that connecting an expandable bus of the host to the input connector for a particular chain causes that particular chain to be directly connected to that particular expandable bus of the host. The absence of connecting any expandable bus of the host to the input connector for a particular chain causes that particular chain to be directly connected to a different chain so as to be indirectly connected to one of the expandable buses of the host. In another embodiment, the connections to an expandible bus of the host must be consistent with a predetermined connection logic.

Abstract: A method and apparatus for correcting internally defective devices by routing signals on an I/O line to a spare internal network. Such devices enable a system designer to substitute good internal networks, e.g., memory arrays, for failing internal networks without loss of functionality at the I/O level. A device includes a plurality of I/O lines, a plurality of internal networks, a plurality of multiplexers for routing signals from the individual I/O lines to the individual internal networks, and a multiplex controller for controlling the signal routing. Routing can be performed using multiplexers that operatively interconnect any I/O line with any internal network, multiplexers that shift signals on an I/O line to and adjacent internal network, and/or multiplexers that can shift signals on an I/O through a multiplexer to any other multiplexer, and then to any internal network.

Abstract: The present invention allows a user to customize the configuration sequence of a configurable system on a chip (CSoC), thereby adding considerable flexibility to the configuration process. The present invention also provides certain features, transparent to the user, which optimize system resources and ensure the correct initialization of the CSoC. The CSoC leverages an on-chip central processing unit (CPU) to control the configuration process of the configurable system logic (CSL). Advantageously, the CSL configuration memory cells as well as other programmable locations in the CSoC are addressable as part of a system bus address space. The system bus is a multi-use structure that can be used for both configuring and reading of memory cells. In this manner, the CSoC optimizes system resources.

Abstract: A serial ATA control circuit is provided. The control circuit includes a plurality of serial ATA controllers, a plurality of port controlling circuits, a plurality of switch devices, and a switch controller. Each of the serial ATA controllers has a memory accessing controller and two transceivers. The serial ATA control circuit is connected to at least one serial ATA device through the port controlling circuits. The a plurality of port controlling circuits are connected to corresponding serial ATA controllers through the plurality of switch devices controlled by the switch controller. The connection path between each port controlling circuit and corresponding serial ATA controller is selected by the switch controller to achieve optimal data transfer rate.

Abstract: The present invention is directed to a method and system for providing, a host input/output (I/O) module, a controller and application specific integrated circuit (ASIC) for utilization in transparent switched fabric data storage transport. The system implements I/O modules capable of translating between communication protocols for providing common message passing multi-channel data transport for data storage while providing apparent I/O circuit exclusivity to controllers. Implementing the system of the present invention allows for a common data transport system permitting component scalability and virtualization.

Abstract: A bus that may be used in an integrated circuit chip. The bus generally comprises a master interface, a slave interface, and a control logic. The master interface may be configured to (i) receive an early command signal having a predetermined timing relationship to a first clock edge and (ii) present a bus wait signal proximate a second clock edge. The slave interface may be configured to (i) present a command signal a delay after the first clock edge and (ii) receive a slave wait signal. The control logic may be configured to (i) register the early command signal to generate the command signal and (ii) convert the slave wait signal into the bus wait signal.

Abstract: An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N output signals. Only one data input of the enable register receives an enable signal. In this way, the propagation time at the input of the buffer register is reduced.

Abstract: The present invention discloses an integrated PCI interface card and the bus system thereof. The integrated PCI interface card of the present invention includes at least two bus masters, a control unit and one multiplexer. The control unit is used in generating the bus request and bus acknowledge signals of the at least two bus masters. The multiplexer is used in selecting an unused address line to be the identification selection signal of one of the at least two bus masters.

Abstract: A new method and framework for implementing network protocol processing utilizing a combination of application threads and a dedicated thread to process IO completions in a completion queue that automatically detects and adjusts thread priorities to alleviate manual intervention. According to the present invention, as data transfer operations are completed by the network interface, completion information identifying the data transfer operations is posted on the completion queue. The completion information is read and processed by a combination of application and dedicated threads running in the system. A method monitors performance of the system to detect whether poor processor utilization or excessive context switches occurs, in which case a different thread is used to process the completion information.

Abstract: A crossbar circuit (30, 40, 50, 60, 70, 80, 90, 100) having programmable repeater structures adapted to allow configuration of the crossbar with inputs at multiple sides of the crossbar die. A plurality of repeaters (62) are arranged in different repeater structures such that the repeater arrangement can be connected to inputs at different locations as a function of the corresponding input as it is physically positioned around the periphery of the crossbar. A pseudo code is provided allowing the repeater structures to be custom configured to corresponding inputs as a function of the desired crossbar as it is designed to be utilized in a particular large integrated circuit, such as a VLSI chip.

Abstract: Embodiments are provided in which a method is described for transferring data in a digital system comprising a first bus, a second bus, and a bridge coupling the first and second buses. During system initialization, an initialization program collects system information of the digital system. Then, based on the system information of the digital system, the initialization program determines a buffered packet size and configures the bridge with the buffered packet size. After system initialization, the bridge transfers data from the first bus to the second bus via the bridge according to the buffered packet size.

Abstract: A system and method for configuring expandable buses wherein a host supports a plurality of expandable buses are provided. A plurality of devices are arranged to form a plurality of groups. Each group forms a chain of devices on an expandable bus. Each chain includes an input connector. The chains are configured such that connecting an expandable bus of the host to the input connector for a particular chain causes that particular chain to be directly connected to that particular expandable bus of the host. The absence of connecting any expandable bus of the host to the input connector for a particular chain causes that particular chain to be directly connected to a different chain so as to be indirectly connected to one of the expandable buses of the host.

Abstract: The present invention provides a transmission interface conversion device, which can first convert the communication signal of a master equipment controller and then connect to a plurality of slave devices through a pair of transmission lines so as to perform data transmission and power supply synchronously. The transmission interface conversion device includes: a conversion interface, formed by at least one repeater circuit, which transmits data by half-duplex; a signal inspector, which inspects whether a signal has been transmitted to the conversion interface; a control unit, to determine the orientation and the operation method of the repeater circuit by using the signal that has been inspected by the signal inspector; and a voltage adjustor, to supply needed electric power to all the above-mentioned circuits. The invention has features of being installed and maintained easily as well as being able to reduce the cost of cabling.

Abstract: A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component to the apparatus for storing information utilizing the clock of the first component, a second component operated in response to the timing of a second clock, apparatus for utilizing the clock of the second component to transfer information from the apparatus for storing information in a condition in which it is synchronized for use by the second component whereby the information may be immediately utilized by the second component without the need for storage by the second component.