Abstract: A sensor concentrating system centralizes communication between multiple parameter sensing devices and an application host. As a peripheral device, the sensor concentrating unit establishes a temporal correspondence between range data acquired from multiple optical range sensors with position data acquired from a shaft encoder. The parameter data are read and sampled according to a user specified criteria such as the time division multiplexing technique. The sampled data is correlated with a data tag generated by the sensor concentrating unit. The correlated data is packeted transmitted from the sensor concentrating unit to a downstream application host for subsequent analysis. The sensor concentrating unit also provides operating parameters for individual parameter sensing devices.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.

Abstract: A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to the shared bus in response to an owner signal. A set of peripheral-share registers where a first member of the set includes an entry associated with each of the plurality of peripheral units and holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.

Abstract: Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially.

Abstract: An image processing apparatus, method and computer readable recording medium provided with a primary memory device and a secondary memory device both having image data memorized therein, in which said image data are input to said primary memory device, and including an external input data amount acquisition device acquiring the amount of said image data input to said primary memory device; an internal output data amount acquisition device acquiring the amount of said image data output from said primary memory device and input to said secondary memory device; a first difference data amount calculation device subtracting the amount of the data acquired by said internal output data amount acquisition device from the amount of the data acquired by said external input data amount acquisition device, and calculating first difference data amount by the subtraction; a memory access control device practicing the inputting and outputting of said image data with time sharing in said primary memory device, comparing said

Abstract: An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the Nth layer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding one of the buffering devices for the Nth layer, respectively. (b) A buffering device for the N+1th layer is implemented at a location close to the middle place between two buffering devices for the Nth layer, and each one of the buffering devices for the Nth layer is electrically connected to the corresponding one of the buffering devices for the N+1th layer, respectively. Then, the number of the buffering devices for the N+1th layer is judged whether or not to be 1.

Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.

Abstract: A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.

Abstract: One embodiment comprises an apparatus for reordering requests for access to a subdivided resource. The apparatus includes a non-FIFO request buffer for temporarily storing the requests for access, a selector for selecting a next request from the request buffer, and a mechanism for outputting the next request to a controller for the resource. Another embodiment comprises a method for reordering requests for access to a subdivided resource. The method includes temporarily storing the requests for access, selecting a next request from among the stored requests in non-FIFO order, and outputting the next request to a controller for the resource.

Abstract: A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network.

Abstract: A configurable memory controller for an AMBA system is described. This configurable memory controller selects one of two possible modes of operation. The technique of configuring the memory controller provides fundamental memory control in the AMBA system while also allowing for a switching mechanism to select between the two modes, each of which entails its own set of special signal definitions. The configurable memory controller may be connected either on the AHB bus or directly connected to the ARM central processing unit core with a mechanism to switch between the two modes of operation.

Abstract: The present invention is a method and apparatus to self update a firmware device. A communication interface receives programming information. A parser coupled to the communication interface to parse the programming information into control commands and program data.

Abstract: A architecture for a multifunction peripheral to service a plurality of clients simultaneously. A shared memory receives data from the plurality of clients. A channel multiplexer selects data to be routed to a peripheral, a SCSI emulator is used to logically select the peripheral. The data is then forwarded from the multiplexer via the SCSI emulator to a PCI bus, the PCI bus being physically connected with the peripheral's engine. When data needs to be sent from a peripheral to a client, it is forwarded from the PCI bridge to the SCSI emulator and routed via a demultiplexer to the shared memory wherein it is retrieved by the appropriate client. The multifunction peripheral can be interrupted while performing a first task using a first peripheral, switch to a second task needing a second peripheral, and return to the first task when completed.

Abstract: The inventive control logic provides the selection signals for a bi-endian rotator MUX. The logic determines the starting point for the data transfer by determining which input register byte is going to Byte 0 of the output register. The control logic passes the starting point to single decoder. The decoded value is then sent to a plurality of MUXs, one for each of the output register bytes. Each of the MUXs is prewired to receive a portion of bits of the decoded value, and the portion is arranged in a particular order. The MUXs then send their respective outputs to the rotator MUX as selection control signals.

Abstract: A multiplexor is designed to receive data from a plurality of data sources. As the multiplexor receives data from data sources, its programmable logic device codes each stream of data with a header and a footer and a data stream segment between them having a prescribed number of characters. A message from any particular data source may be coded into a plurality of separate data stream segments. The multiplexor sequences to the next data source when a data stream having the prescribed number of bytes has been captured and returns to that data source only after data streams of the same prescribed number of characters have been captured from the other data sources in a sequential manner. Data so coded is forwarded to a storage device that may store the data on any suitable storage medium for later retrieval.

Abstract: A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to the shared bus in response to an owner signal. A set of peripheral-share registers where a first member of the set includes an entry associated with each of the plurality of peripheral units and holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.

Abstract: A cross connect with a cascadable architecture may selectively output a switched or an unswitched data stream from a transmission line. Two or more such cross connects may be cascaded by connecting their system side ports for bi-directional communication. Either of the cross connect connected directly to the transmission line or the cross connect connected indirectly to the transmission line through the other cross connect may switch the data stream from the transmission line for output to a system.

Abstract: A device and method for servicing data requests from a processor or other input/output interface in a multi-processor environment by accessing a full or partial cache line of data. A system data chip is used to access the cache line of data using a bit pattern supplied by a system address chip. This access and transmission of data to the processor or the input/output interface is controlled by a control/status unit in the system data chip based on the value of control valid signals which include a first valid (DxV) signal and a second valid (CxV) signal. Also, data may be stored and retrieved in a first data format (linear chunk order) or a second data format (critical chunk order). When control by the control/status unit is based on the DxV signal value, a read of a data chunk may occur immediately after a write to temporary storage if the data is in the same chunk order and a merge or combination operation is not taking place.

Abstract: A packet reformatter is disclosed that may store packet information received in one format and reformat the received packet information into a different format.

Abstract: A method and system for demultiplexing packets of a message is provided. The demultiplexing system receives packets of a message, identifies a sequence of message handlers for processing the message, identifies state information associated with the message for each message handler, and invokes the message handlers passing the message and the associated state information. The system identifies the message handlers based on the initial data type of the message and a target data type. The identified message handlers effect the conversion of the data to the target data type through various intermediate data types.

Abstract: A reconfigurable register array structure allows an agent to transmit data from a single channel or in bundled form from multiple channels. The structure makes economical use of valuable chip space by reducing the size of the overall register array system. A coalescing prestage is used to collect data from single channels or from multiple channels and to multiplex the data, based on a priority scheme, to supply the data to a primary stage of first-in-first-out register arrays. The coalescing prestage may include one or more first registers, a delay register, multiplexers to select outputs of the first registers, and multiplexers to select outputs of the delay register. Alternatively, the coalescing prestage may include one or more register array structures, each such structure having independent write ports, one for each channel. Data coalesced in the coalescing prestage is provided to a primary stage. The primary stage may include one or more logical register arrays configured as one physical array.

Abstract: A memory device is described which is fabricated as an integrated circuit and uses distributed bond pads for electrical connection to an external conductive lead. The distributed bond pads are attached to a external lead, thereby eliminating bus lines on the integrated circuit memory. Distributed buffer circuits are described which can be included with the distributed bond pads to increase data communication time between the memory device and an external processor.

Abstract: A microprocessor includes a first bus and a second bus capable of operating simultaneously, a single port memory divided into a plurality of banks, a bus switch circuit provided between the plurality of banks and the first and second buses, and a processor core connected to the first and second buses and the single port memory. The bus switch circuit may be controlled statically, independent of activities on the buses, or may be controlled dynamically according to the activities.

Abstract: The present invention provides an electronic switching device for a universal serial bus (USB) interface, which can connect several different electronic devices each having a universal serial bus (USB) interface when needed. By manually enabling a switch of the electronic switching device for a universal serial bus (USB) interface, a trigger signal generated from a trigger signal generator will be outputted to a control signal generator to generate a control signal for connecting related electronic devices. A delay signal generator can be added to avoid the intermediate devices being operated unintentionally.

Abstract: A point-of-sale system is disclosed which is freely configurable with a plurality of peripheral input devices. The system includes a general purpose computer having a communications port for receiving and/or transmitting data. An electronic interface is coupled to the communications port and readily connectable to the plurality of peripheral input devices for communicating data between the plurality of input devices and the computer. The plurality of peripheral input devices can be selectively connected and disconnected from the electronic interface, the electronic interface maintaining a continuous dialogue with the computer during the connection and disconnection of the input devices.

Abstract: A method and apparatus is provided for providing communication with input/output devices without being bound by the limitations of an existing input/output bus while still providing compatibility with software intended to communicate with input/output devices using the existing input/output bus. The software image of the input/output devices as being associated with the input/output bus is preserved, but a technique is provided to allow communication with the input/output devices to bypass the existing input/output bus. A translation lookaside buffer is utilized to remap accesses to an internal input/output device from virtual address space for input/output-bus-based input/output devices to physical address space for the internal input/output device. Circuitry for interfacing with the input/output devices separately from the existing input/output bus may be fabricated as a single integrated circuit device along with other system components, such as a central processing unit.

Abstract: The present invention provides an integrated parallel and serial programming interface that can be selected between either a parallel programming mode or a serial programming mode. The present invention provides a control logic circuit for selecting between the parallel and serial modes. The present invention also includes a parallel and serial detection circuit. The control logic sends a signal to an interface circuit that selects between a serial programming mode and a parallel programming mode based on the outputs of the parallel and serial detection circuits.

Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a read-back address signal or (ii) a data signal as an output signal in response to one or more first control signals. The second circuit may be configured to generate (i) the read-back address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signals. The third circuit may be configured to generate one or more I/O control signals in response to the cycle identification signal, where the one or more I/O control signals may determine the format of the output signal.

Abstract: A plurality of sensor portions detect a variety of physical characteristics of objects to be detected, which are being conveyed on a conveyance passage to asynchronously transmit electric signals indicating results of detection to a processing unit. The processing unit causes an A/D converter to A/D-convert the electric signals transmitted from the sensor portions. A mixer adds, to data, an identifier indicating the sensor portion from which data has been transmitted to sequentially output data for each of the sensor portions. A detection-result processing means receives data output from the mixer to identify the sensor portion from which data has been transmitted in accordance with the identifier contained in received data so as to perform a process for detecting the variety of the physical characteristics. The structure and circuit structure of the transmission passage in the detecting apparatus can be simplified.

Abstract: A first-in, first-out (FIFO) memory system (10) includes first and second FIFOs (A and B). First and second multiplexers (12, 14) each have two input terminals for receiving data. An output terminal of the first multiplexer (12) is coupled to the first FIFO (A) and an output terminal of the second multiplexer (14) is coupled to the second FIFO (B). In response to the data being one data type, write control logic (90, 95, 100) is used to cause the data to be alternately written to the first and second FIFOs (A, B). In response to the data being a second data type, write control logic (90, 95, 100) is used to cause the data to be simultaneously written to the first and second FIFOs (A, B).

Abstract: A system converts an input data stream in a first format (identified by a first stream code having at least two bits) into an output data stream in a second format. The system includes, among other things, a data sequencer for sequencing the input data stream and a counter. The sequencer includes a select input having a first number of selection input locations, a data input for receiving the digital data stream, and output for transmitting the output data stream. The counter includes the first number of selection outputs. A first logic element and a second logic element are coupled to a number of the selection inputs of the sequencer and a number of the selection outputs of the counter. The first and second logic elements control the data sequencer such that the input data stream in converted into the second format.

Abstract: A direct input/output port access device according to the invention which can control data accesses directly between an input port and an output port. The direct input/output port access device includes a local data bus which electrically connects the input port and the output port, an input/output port read/write controller and a data bus transceiver. In a direct input/output port access operating mode, the data bus transceiver is controlled by the input/output port read/write controller to electrically separate the local data bus from a system data bus. Simultaneously, the input/output port read/write controller generates can control data accesses directly between the input port and the output port according to read/write request status signals of the output port and the input port. At this time, a microprocessor can process other operations using the system data bus.

Abstract: A method and apparatus for allowing several applications to share a single video overlay resource via multiplexing are disclosed. The multiplexing is accomplished from the application end through a multiplexing abstraction layer provided to the developers of end applications as an application program interface. Through the application program interface, each application may, at any time, request, release, or modify the attributes of the video overlay device such as picture quality, tuning, source, etc. The application program interface provides all basic functionality of the hardware as accessible through other means including normal operating system support and device driver services.

Abstract: A method and apparatus for allowing several applications to share a single video overlay resource via multiplexing are disclosed. The multiplexing is accomplished from the application end through a multiplexing abstraction layer provided to the developers of end applications as an application program interface. Through the application program interface, each applications may, at any time, request, release, or modify the attributes of the video overlay device such as picture quality, tuning, source, etc. The application program interface provides all basic functionality of the hardware as accessible through other means including normal operating system support and device driver services.

Abstract: An information network 200 extends between a first information relaying apparatus 20 and a terminal 23, which are equipped with existing circuit multiplexing modules 39. Signals from the information relaying apparatus 20 pass through additional information relaying apparatuses 21, 22, which relay signals output from the information relaying apparatus 20. The information relaying apparatuses 21, 22 associate LAN lines between the information relaying apparatus 20 and the terminal 23 into separate groups and effectively monitor these LAN lines. If a failure is detected, then all LAN lines belonging to the group of the LAN line experiencing the failure are effectively shut down. As a result, circuit multiplexers 39 in the information relaying apparatus 20 are then instructed to use a different LAN line that is not experiencing failure so that communication can continue.

Abstract: A memory allocator employs a programmable and controllable switching circuit which switches multiple address buses and multiple data buses connected to the digital signal processing unit to differing banks of memory depending upon determined system requirement data, such as the amount of program memory and data memory necessary for a particular application. The memory space may be separate banks of memory incorporated into pools of memory if desired. The controllable switching circuit multiplexes the appropriate address bus and data bus to a given memory block or blocks which may be independent and can still be dedicated to specific application tasks. The memory banks are normal single address port and single data-port banks but are allowed to be connected to multiple data buses and address buses through the switching circuit. The switching circuit is sized to allow access to a subset of banks in a pool of banks associated with a given memory port. The digital signal processor is a multi-port device.

Abstract: A method and apparatus for providing modular I/O expansion. Apparatus are provided on a host computing device and an expansion unit to support multiple port types, and multiplexing apparatus are provided to support simultaneous I/O sessions between multiple applications on the host computing device and multiple I/O ports on the expansion unit over a single host I/O port. The expansion unit is equipped with one or more port interface modules that are each configured to support data transmission in accordance with one port type from a set of port types. Apparatus on the expansion unit perform multiplexing and demultiplexing of data transmitted between the host computing device and the port interface modules of the expansion unit. Port interface objects in the host computing device each support data transmission in accordance with one port type from the set of port types.

Abstract: A system for efficiently controlling the exchange of data between a host bus (190) and an input/output (I/O) register (125) of an elliptic curve (EC) processor (120) having a much wider datapath than that of the host device (100) . A spreading/despreading pattern is determined which spans multiple bit positions of the input/output register (125). In one embodiment, a full combinational circuit (300) is provided to connect a bit position of the host bus (190) to a bit position of the input/output register (125). In another embodiment, a combinational circuit (300) and an intermediate register (410) are provided. In still another embodiment, a spreading-by shifting system (500) is provided which comprises a plurality of subfield modules (520) into which data from the host bus (190) is shifted. The spreading/despreading pattern is achieved through multiplexers (540) connected between the subfield modules (520).

Abstract: A modem and associated method with both an RS-232 interface and a USB interface connects to a host. The modem detects which of the two interfaces is connected to the host and determines an appropriate data path. For connections to the USB interface, data is routed through a USB processor and over a serial link to the modem processor responsible for modem communications and the transfer of modem data to the POTS. The serial link between the USB processor and the modem processor is used to transfer both modem data and processor communications. A plurality of control lines are used to indicate the type of data being transferred over the serial link. For RS-232 connections, the modem data is transferred to the modem processor. Thus, one modem device may be used for either USB or RS-232 connections.

Abstract: A data corruption indicator circuit for providing error free data transfer between a first device and a second device, clocked by different clock signals, is implemented. The data corruption indicator circuit can allow for faster throughput than the described prior art and provides a circuitry for detecting corrupt data. The data corruption indicator circuit provides a clocked data ready signal that updates a status lip-flop and a delayed data ready signal that updates a plurality of data flip-flops and a potential corruption flip-flop. Additionally, the delayed data ready signal may be used as an interrupt signal to notify the second device that data is available for transfer. The delay between the clocked data ready signal and the delayed data ready signal is such that a hazard cannot exist for the data signal and the status signal simultaneously.

Abstract: A plurality of transmitters are multiplexed to a hub through clocked serial links. Timing problems that may arise when switching between links are eliminated with a system including a group serial receiver for each link for performing serial to parallel conversion of data sent over the serial link, outputing a group clock signal based on the serial clock signal, outputing parallel data clocked by the group clock signal, and determining a data enable signal from the serial link. A select signal for determining the serial link being read by the hub selects the corresponding group clock, parallel data, and data enable. A load control clocks the selected parallel data into a first-in, first-out buffer using the selected group clock when the selected data enable is asserted. When the selected data enable is not asserted, the load control is held in reset and, hence, is insensitive to irregularities in the selected clock signal due to switching between links. Data is clocked from the buffer by a local clock.

Abstract: An input/output data transfer system capable of integrating input/output data transfer on a plurality of input/output interface cables into data transfer on a single serial input/output interface cable for substantially reducing the number of input/output interface cables required for a host computer system. A multiplexer channel device is provided with a plurality of channels which serve as logical channels corresponding to conventional physical channel paths from a viewpoint of an operating system running on the host computer system. A multiplexer port device is provided with a plurality of input/output ports on a switching device or input/output device, each of these channels and ports shares a large-capacity input/output interface, and a channel path multiplexing function is performed for enabling frame-by-frame multiplexing and simultaneous input/output operations on plural channels.

Abstract: Enhanced is a data processing efficiency of a whole semiconductor integrated circuit. A multiplexer is provided on a main parallel data bus for transferring data between an internal device such as a CPU, a DRAM or the like and an external device. When the CPU cannot accept data from the external device, it sends a busy signal to an interface circuit. The interface circuit receives the busy signal and controls the multiplexer in such a manner that the data to be transmitted to the CPU are transferred to the DRAM. Thus, a data transfer rate of the semiconductor integrated circuit is enhanced.

Abstract: A method of operation of a synchronous memory device having at least one memory section which includes a plurality of memory locations. The method comprises receiving an external clock signal having a fixed frequency, receiving a read request, including addressing information, synchronously with respect to the external clock signal, initiating an internal memory addressing operation, in response to the read request, and outputting data onto the external bus synchronously with respect to the external clock signal. The synchronous memory device may include interface circuitry, coupled to an external bus, to receive a write request packet synchronously with respect to an external clock. The write request packet may include N bits of information and the external bus includes M number of signal lines wherein N is substantially greater than M.

Abstract: A method of operating a synchronous memory device, wherein the memory device includes a plurality of memory cells and a register for storing an identification value which identifies the memory device on a bus. Block size information is provided to the memory device, wherein the block size information specifies an amount of data to be output onto a bus in response to a read request. The read request is issued to the memory device, and includes identification information, wherein in response to the read request, the memory device determines whether the identification information corresponds to the identification value stored in the register. When the identification information corresponds to the identification value, the memory device outputs an amount of data corresponding to the block size information onto the bus synchronously with respect to at least a first external clock. The memory device may further include a programmable register.

Abstract: An apparatus for and a method of arbitrating a stream of access requests over multiple outputs. In one embodiment, the apparatus is implemented with D*[W+(N+1)log.sub.2 D] storage elements, where D is a maximum number of outstanding requests allowed by an issuing agent, N is a number of different request types, and W is a width of access requests measured in bits. The present embodiment comprises a main queue, an input address selection circuit coupled to the main queue for selecting storage locations to receive a stream of access requests, and a plurality of output address selection circuits coupled to the main queue for selecting storage locations to be read. Significantly, the input address selection circuit includes an input address list pointing to vacant storage locations in the main queue, and the input address list is updated each time an access request is stored in, or read out from, the main queue.

Abstract: The present invention is directed to a synchronous memory device having a memory cell array divided into a plurality of subarrays, including first and second subarrays each having a plurality of subarray sections. The memory device further includes a device identification register to store an identification code to identify the memory device. A first subarray section in the memory device includes a first internal I/O line to access data from a first memory cell location in the first subarray section and a second internal I/O line to access data from a second memory cell location in the first subarray section. A second subarray section in the memory device includes a first internal I/O line to access data from a third memory cell location in the second subarray section and a second internal I/O line to access data from a fourth memory cell location in the second subarray section.

Abstract: A high-performance network/bus multiplexer that exchanges data transfer commands and data between different communications mediums, such as the Fibre Channel and one or more SCSI buses. High-performance is achieved by avoiding transmitting read bus operations through bus bridges, and by limiting contention for buses by connecting Fibre Channel host adapters to a first internal bus and SCSI adapters to a second internal bus.

Abstract: A trackpad or other input/output device is detachable from a computer and adapted with a remote communication functionality using radio frequency (RF) or infrared (IR) technologies, thereby facilitating the performance of slide presentations and other graphic displays. A remote presentation capability allows a computer user to conveniently address a group from a position at a suitable location, such as a podium, that is removed from the computer system. A remote interface includes a trackpad or other input/output device and activation buttons. The input/output device is housed in a small removable enclosure which is adapted for docking into an aperture in the computer. The input/output device is rechargeable with a charger installed into the computer so that the input/output device is recharged during docking with the computer.

Abstract: When normal data is written to a desired address in a DRAM, a guarantee bit comparing/generating circuit sets the value of guarantee bit data stored at the address corresponding to the desired address in a DRAM as a value indicating that the normal data has been written. Since the guarantee bit data stored at each address in the DRAM always becomes "000" or "111" immediately after power is turned on, the above described value indicating that the normal data has been written is set as a value other than "000" and "111". Thereafter, if the value of the guarantee bit data stored at the address corresponding to the desired address in the DRAM indicates that the normal data has been written when the normal data is read from the desired address in the DRAM, the normal data read from the DRAM is output to a data bus. Otherwise, the fixed value "0" is output to the data bus as read data.