Queue Content Modification Patents (Class 710/54)
  • Patent number: 11934333
    Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: March 19, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Oren Duer, Dror Goldenberg
  • Patent number: 11892964
    Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: February 6, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Oren Duer, Dror Goldenberg
  • Patent number: 11727095
    Abstract: An authentication apparatus transmits code and challenge to a target, receives a response, and authenticates the target based on the response. The target receives the code and the challenge, generates a password for comparison by executing n times of repetitive computation by a recurrence relation or a recursive function using the code as an initial input, executes password authentication using a pre-stored password and the password for comparison. If the password authentication has succeeded, the target reads out an authentication seed corresponding to the number n that is the number of times of execution of the repetitive computation with which the password for comparison that matches a password has been obtained, and generates the response using the read-out authentication seed and the challenge received from the authentication apparatus, and transmits the response.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: August 15, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hisashi Enomoto
  • Patent number: 11720388
    Abstract: It is disclosed a resource sharing manager, RSM, operative to provide efficient utilization of central processing units, CPUs, within virtual servers, each virtual server having an operating system, OS. The RSM dynamically obtains (902) information about ownership and sharable status of said CPUs, and dynamically determines (904) which CPUs are sharable to which virtual servers. The RSM obtains (906) information about that one or more sharable CPUs are available; and obtains (908) information about that one or more virtual servers require more processing resources. The RSM also assigns (910) a first CPU of said sharable CPUs when available, to a first virtual server of said virtual servers. Information about ownership and sharable status of the first CPU, is hence provided to the OS of the first virtual server. Overhead is reduced by circumventing a hypervisor when sharing CPUs in virtual servers. An increase in efficiency of task execution is provided.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: August 8, 2023
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Amir Roozbeh, Mozhgan Mahloo, Joao Monteiro Soares, Daniel Turull
  • Patent number: 11537515
    Abstract: Provided herein may be a memory controller configured to control a memory device. The memory controller may include a map buffer, a descriptor queue, and a descriptor controller. The map buffer may sequentially store map segments of a plurality of map segments stored in the memory device. The descriptor queue may store descriptors corresponding to the respective map segments, based on a plurality of addresses of the map buffer. The descriptor controller may search for a target descriptor among the stored descriptors based on a logical address received from a host, and reorder the stored descriptors while searching for the target descriptor.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: December 27, 2022
    Assignee: SK hynix Inc.
    Inventor: Joung Young Lee
  • Patent number: 11513836
    Abstract: Dynamic scheduling is disclosed. A plurality of physical nodes is included in a computer system. Each node includes a plurality of processors. Each processor includes a plurality of hyperthreads. In response to receiving an indication of an event occurring, a search is performed for a queue in a set of queues on which to place a virtual processor that had been waiting on the event. Queues in the set of queues correspond to hyperthreads in a physical node in the plurality of physical nodes. The queues in the set of queues are visited according to a predetermined traversal order.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 29, 2022
    Assignee: TidalScale, Inc.
    Inventors: Isaac R. Nassi, Mark Hill, I-Chun Fang, Kleoni Ioannidou
  • Patent number: 11500639
    Abstract: An arithmetic processing apparatus includes a memory, a first processor coupled to the memory, and a second processor coupled to the memory. The first processor is configured to consecutively issue a plurality of load instructions for reading respective data with respect to the memory. The first processor is configured to determine whether an ordering property is guaranteed, based on values included in the data loaded from the memory. The second processor is configured to issue a store instruction during an execution of the plurality of load instructions with respect to the memory.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 15, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Hideyuki Takano
  • Patent number: 11307923
    Abstract: Example methods and systems for memory leak detection. One example may comprise: identifying a set of memory buffers that are available for storing packet information that requires processing by the network device; a first subset that includes one or more first memory buffers that are unallocated, and a second subset that includes one or more second memory buffers that are allocated and storing packet information that is being processed by the network device. The method may also comprise: performing a comparison between (a) the set of memory buffers and (b) the first subset and the second subset; and based on the comparison, identifying a third subset that includes one or more third memory buffers, being leaked memory buffers, that are storing packet information that is no longer being processed by the network device.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: April 19, 2022
    Assignee: VMWARE, INC.
    Inventors: Yong Wang, Xinhua Hong, Jia Yu, Eduard Serra Miralles
  • Patent number: 11269713
    Abstract: A data obtaining method and apparatus. The method comprises: determining address information of data to be obtained; judging whether a disk corresponding to the address information of the data to be obtained is a damaged disk or not; if the disk corresponding to the address information of the data to be obtained is not a damaged disk, obtaining the data to be obtained according to the address information of the data to be obtained to obtain current data; if the disk corresponding to the address information of the data to be obtained is a damaged disk, determining the address information of next data to be obtained, and returning to the step of judging whether a disk corresponding to the address information of the data to be obtained is a damaged disk or not.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: March 8, 2022
    Assignee: HANGZHOU HIKVISION DIGITAL TECHNOLOGY CO., LTD.
    Inventors: Yang Xiang, Jie Wang, Jie Yan, Qi Wu, Yongheng Yu, Ming Chen, Yang Luo
  • Patent number: 11221795
    Abstract: Methods, systems, and computer program products for queue management are provided. Aspects include receiving a first queue entry and storing the first queue entry in a queue at a first location, wherein the first queue entry includes a first target destination, receiving a second queue entry and storing the second queue entry in the queue at a second location, wherein the second queue entry includes a second target destination, tracking a relative age for each of the first queue entry and the second queue entry, transmitting the first queue entry to the first target destination based at least in part on the relative age for the first queue entry being greater than the relative age for the second queue entry, and receiving a third queue entry and storing the third queue entry in the queue at the first location.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary E. Strait, Matthias Klein, Alia Shah, Sajay Mathew Karottukottarathil Baby
  • Patent number: 11086801
    Abstract: A resource request is received by a network device from a virtual machine running on a host. The resource request includes a requested resource size. The network device allocates resources of the network device in response to the resource request. A resource response is sent by the network device to the virtual machine that generated the resource request. The resource response includes a location of the allocated resource.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: August 10, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Georgy Machulsky, Nafea Bshara, Netanel Israel Belgazal, Evgeny Schmeilin, Said Bshara, Alexander Matushevsky
  • Patent number: 10990443
    Abstract: A method for utilization profiling of thread specific execution units and scheduling software on a multi-core processor is provided. To perform the method, the multi-core processor profiles a workload received for execution by a core of the multi-core processor and logs an execution unit sensitivity to an operating system with respect to the workload. Further, the multi-core processor utilizes the execution unit sensitivity for subsequent workload scheduling to minimize sharing of hardware threads on the same core between workloads with similar execution unit sensitivities.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: April 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rahul Rao, Venkatesh Sainath, Vaidyanathan Srinivasan
  • Patent number: 10977433
    Abstract: Implementations generally relate to a method of adding asynchronous validation and conversion capabilities to web components by adding an attribute to an existing web component accessed through, for example, a GUI interface. Such attribute will specify what type of validation or formatting conversion is expected. The web component may provide feedback on errors or changes in an interactive fashion for the user based on web service data. Feedback may be provided to the user asynchronously, without waiting for all user inputs to be validated or converted before displaying the errors or changes to the user. The web component remains completely interactive to the user even while validation or conversion is in progress on the server. Furthermore, the web component will handle multiple user inputs and only display the validation or conversion results from the last user input.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: April 13, 2021
    Assignee: Oracle International Corporation
    Inventor: Jeanne Waldman
  • Patent number: 10937484
    Abstract: A system and method of avoiding loss of memory trace data, including monitoring a first-in-first-out (FIFO) buffer to determine if the FIFO buffer has overflowed due to memory access, determining whether an overflow of the FIFO buffer is acceptable, changing an operating mode of a target system if overflow of the FIFO buffer is unacceptable to avoid FIFO buffer overflow, and collecting memory trace data on the memory accesses.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Seiji Munetoh, Nobuyuki Ohba
  • Patent number: 10841390
    Abstract: A system and method for synchronizing publication and subscription of message queues are provided. The method includes: providing a message broker cluster including a plurality of message brokers each having a buffer queue and a data queue; as any one of the message brokers requests a synchronization requirement, selecting, by an orchestration server, one of the message brokers in the message broker cluster to perform data synchronization; setting a data read-lock to the data queue of the selected message broker sequentially to write data contents in the buffer queues of all of the plurality of message brokers into the data queue of the selected message broker; and copying the complete data contents in the data queue of the selected message broker to the data queues of the other message brokers, allowing the data contents in the data queues of each of the message brokers to be consistent.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: November 17, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Lun Chen, Hung-Wei Lin, Li-Ting Huang
  • Patent number: 10623423
    Abstract: Systems and methods include implementing a review queue interface that includes: a review queue comprising a listing of distinct review items; a current state for each of distinct review items; a listing for each review item of the distinct review items of one or more client browsers that are interacting with each review item; identifying client browser activity of the one or more client browsers; computing a computed state for each of distinct review items based on the client browser activity; computing changes to the state of review items based on an assessment of the current state and the computed state for each of distinct review items; and automatically updating a state of one or more of the distinct review items within the review queue interface based on a difference between the current state and the computed state of the one or more of the distinct review items.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: April 14, 2020
    Assignee: Sift Science, Inc.
    Inventors: Fred Sadaghiani, Megan Mann, Aleksandr Lopatin, Noah Grant
  • Patent number: 10581905
    Abstract: The present invention relates to a solution to improve the security of applications. Particularly, the invention relates to the control of the whole lifecycle of data traffic between a client and a server applying also internal data flow system within the server only for editable data. The invention presents a method for detection of manipulation of data (29) by a client (11, 15, 25) that performs a request to a server (13, 17, 27) and detection of vulnerabilities within source code. The invention also presents an application and a system for the detection of manipulation in applications. As a particular example, the invention presents a method for detection of manipulation of web pages in HTTP.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 3, 2020
    Assignee: HDIV SECURITY, S.L.
    Inventor: Roberto Velasco Sarasola
  • Patent number: 10539996
    Abstract: The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off and a Memory Management Unit (MMU) to translate virtual addresses to physical addresses and generate exceptions to process accesses to virtual addresses without a corresponding physical address. The architecture can implement a demand paging scheme whereby a MMU fault from an access to code/data not within the embedded memory causes the processor to fetch the code/data from an off-chip secondary memory. To minimize page faults, the architecture stores WiFi client code/data within the embedded processor's memory that is repeatedly accessed with a short periodicity or where there is an intolerance for delays of accessing the code/data.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 21, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Sandip HomChaudhuri, Douglas Dahlby, Murali Krishna, Harinder Singh, Ravi Konda, BalaSubrahmanyam Chintamneedi
  • Patent number: 10514997
    Abstract: Systems and methods associated with a multi-producer single consumer lock-free queue capable of accumulating traces is described herein. In a non-limiting embodiment, data is determined to be allocated, and a first head/tail pair indicating a location along a queue is received, the location indicating where a data bucket is able to be placed. A first data bucket to use for storing the data is determined, and the data is stored using the first data bucket. The first data bucket is then placed on the queue, and a first instruction to decrement a first reference count for the first head/tail pair is generated.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: December 24, 2019
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventor: Ronald Landheer
  • Patent number: 10353737
    Abstract: Examples of the present disclosure relate to systems and methods for fast and secure request forwarding. A server application may receive an indication that there is a request in a queue available for processing. The server application may peek at the request, thereby accessing at least a portion of the request without removing the request from the queue. Based on the portion of the request, a determination may be made about whether the server application should process the request directly or transfer the request to a different module. If it is determined that the request should be processed directly, the entire request may be received from the queue and processed accordingly. However, if it is determined that the request should be forwarded, the request may be transferred to a secondary queue. A different module may then receive the request from the secondary queue and process the request accordingly.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: July 16, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Ivan D. Pashov
  • Patent number: 10303383
    Abstract: A computer-implemented method of resizing a data structure includes storing a first hash index comprising x elements, wherein x is a positive integer greater than two, determining that the first hash index needs to expand, allocating a second hash index, wherein the second index contains at least x+1 elements, attempting, by a first thread, to advance a first pointer from the first hash index to the second hash index, attempting, by a second thread, to advance the first pointer from the first hash index to the second hash index, where only one of the first thread or the second thread will advance the first pointer based on an atomic operation.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: May 28, 2019
    Assignee: TRAVELPORT, LP
    Inventor: Bryan Karr
  • Patent number: 10198362
    Abstract: Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: February 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Senior, Christopher Edward Koob, Gurvinder Singh Chhabra, Andres Alejandro Oportus Valenzuela, Nieyan Geng, Raghuveer Raghavendra, Christopher Porter, Anand Janakiraman
  • Patent number: 10146932
    Abstract: In some implementations, after one or more users have each been granted a respective access token allowing access to a resource device, revocation data is received by the resource device. The revocation data indicates that the previously granted access to the resource device should be revoked. For example, the revocation data may indicate (i) a user, role, or permission level for which access is revoked and (ii) a duration that access to the resource device was allowed. After receiving the revocation data, the resource device receives token data derived from an access token that allows access to the resource device. The resource device determines that the access token relies on authorization of the user, role, or permission level indicated by the revocation data, and in response, the resource device denies access.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: December 4, 2018
    Assignee: Google LLC
    Inventors: Arnar Birgisson, Yevgeniy Gutnik
  • Patent number: 10055482
    Abstract: A system, a method, and a medium are provided to use Freebase as a source of structured data to construct a knowledge database with Resource Description Framework (RDF) triples and determine encoded entities responsive to structured queries.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: August 21, 2018
    Assignee: NTT DOCOMO Inc.
    Inventors: Hongfeng Yin, Pero Subasic
  • Patent number: 10027654
    Abstract: The invention relates to an authentication method for authenticating a client device having an authentication token generated by means of a pseudo-homomorphic function and based on a secret element (PIN) known only by the client device, to a server, comprising: the generation (A1), by the client device, of proof of knowledge of the secret element based on a proof generation key masked with a first mask data item, said masked proof generation key being dependent on said secret element, the transmission to the server by the client device, of said generated proof of knowledge of the secret element (A2) and of the authentication token (J) masked using the mask data item (A3), the verification of the validity of the masked authentication token (A4) and of the validity of the proof of knowledge by the server (A6) by a zero-knowledge proof, proving the knowledge of said secret element by the client device without revealing it.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: July 17, 2018
    Assignee: MORPHO
    Inventors: Julien Bringer, Herve Chabanne, Olivier Cipiere, Rodolphe Hugel, Roch Lescuyer
  • Patent number: 9729392
    Abstract: A message manager is capable of analyzing a number of inputs to dynamically adjust rules used to delete messages as well as determine what kinds of messages are likely candidates to be deleted due to their being stale. If a message is determined to be a likely candidate for deletion, the message manager may query the user if they want to delete all messages with similar characteristics, e.g., sender, title, dates sent, time sent, recipients, content, context, and the like. If the user selects “yes” then the message manager may automatically update its deletion rules and further delete all messages in accordance with the user's selection.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: August 8, 2017
    Assignee: Avaya Inc.
    Inventor: Mehmet C. Balasaygun
  • Patent number: 9697136
    Abstract: A data processing system utilizing a descriptor ring to facilitate communication between one or more general purpose processors and one or more devices employs a system memory management unit for managing access by the devices to a main memory. The system memory management unit uses address translation data for translating memory addresses generated by the devices into addresses supplied to the main memory. Prefetching circuitry within the system memory management unit serves to detect pointers read from the descriptor ring and to prefetch address translation data into the translation lookaside buffer of the system memory management unit.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: July 4, 2017
    Assignee: ARM Limited
    Inventors: Ali Ghassan Saidi, Anirruddha Nagendran Udipi, Matthew Lucien Evans, Geoffrey Blake, Robert Gwilym Dimond
  • Patent number: 9600200
    Abstract: Exemplary methods for caching data in a cache device include determining characteristics of a plurality of file extents associated with a plurality of files stored in a random access memory (RAM) device. In one embodiment, the methods include deferring caching of the stored plurality of file extents in a cache device until a predetermined condition has occurred. According to one embodiment, the methods include, in response to determining the predetermined condition has occurred, packing a first portion of the plurality of file extents into a first cache unit based on the characteristics of the file extents, wherein file extents of the first cache unit are likely to be accessed within a predetermined period of time and evicted together from the cache device. The methods further include caching the first cache unit in the cache device and removing the cached file extents from the RAM device.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: March 21, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Grant Wallace, Philip Shilane
  • Patent number: 9535756
    Abstract: Techniques are provided for latency-hiding context management for concurrent distributed tasks. A plurality of task objects is processed, including a first task object corresponding to a first task that includes access to first data residing on a remote machine. A first access request is added to a request buffer. A first task reference identifying the first task object is added to a companion buffer. A request message including the request buffer is sent to the remote machine. A response message is received, including first response data responsive to the first access request. For each response of one or more responses of the response message, the response is read from the response message, a next task reference is read from the companion buffer, and a next task corresponding to the next task reference is continued based on the response. The first task is identified and continued.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 3, 2017
    Assignee: Oracle International Corporation
    Inventors: Siegfried Depner, Jan Van Der Lugt, Sungpack Hong, Hassan Chafi
  • Patent number: 9507533
    Abstract: A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: November 29, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Tal Sharifie, Shay Benisty, Yair Baram
  • Patent number: 9465701
    Abstract: A relay device for dividing a storage device into a plurality of unit areas, assigning an unused unit area from among the plurality of unit areas to received channel-specified data, and performing at least one of adjustment of a transmission timing of the data and conversion of the data by using the assigned unit area, is disclosed. The relay device includes an error detector configured to detect an error where the unit area from which the data is to be read is not specified; and an error control configured to recognize a channel of data stored in the unit area that is not specified due to the error detected by the error detector as a target channel, and to invalidate an assignment of the unit area to the recognized target channel.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: October 11, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Makoto Shimizu, Hidenori Sugai
  • Patent number: 9396101
    Abstract: A computer implemented program product and data processing system for receiving data to a targeted logical partition. A computer locates buffer element in reliance on a connection status bit array. The computer copies control information to the targeted logical partition's local storage. The computer updates a targeted logical partition's local producer cursor based on the control information. The computer copies data to an application receive buffer. The computer determines that an application completes a receive operation. Responsive to a determination that the application completed the receive operation, the computer a targeted logical partition's local consumer cursor to match the targeted logical partition's producer cursor.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: July 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael G. Fitzpatrick, Michael J. Fox, Maurice Isrel, Jr., Constantinos Kassimis, Donald W. Schmidt, Benjamin P. Segal, Jerry W. Stevens, Todd E. Valler
  • Patent number: 9396146
    Abstract: A system-on-chip including an ingress arbiter module to receive a plurality of service requests from a plurality of devices located upstream to access a resource located downstream. Each of the service requests includes a quality of service value and a first timing budget value specified by the respective device to indicate an amount of time in which the respective service request is to be serviced by the resource. The ingress arbiter module selects a first service request based on the quality of service values, the first timing budget values, and a time delay associated with arbitrating the plurality of service requests and outputting the first service request downstream. A timing budget generator module generates a second timing budget value for the first service request based on the first timing budget value associated with the first service request, and the time delay.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: July 19, 2016
    Assignee: Marvell International LTD.
    Inventors: Pantas Sutardja, Jun Zhu, Joseph Jun Cao
  • Patent number: 9335977
    Abstract: System and method for optimizing a data flow diagram based on access pattern information are described. Access pattern information for a data flow diagram may be received. The data flow diagram may include a plurality of interconnected actors, e.g., functional blocks, visually indicating functionality of the data flow diagram. The access pattern information may include one or more of: input pattern information specifying cycles on which tokens are consumed by at least one of the actors, or output pattern information specifying cycles on which tokens are produced by at least one of the actors. A program that implements the functionality of the data flow diagram may be generated based at least in part on the access pattern information.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: May 10, 2016
    Assignee: National Instruments Corporation
    Inventors: Guoqiang Wang, Kaushik Ravindran, Rhishikesh Limaye, Guang Yang, Arkadeb Ghosal, Hugo A. Andrade, John R. Allen, Jacob Kornerup, Ian C. Wong, Jeffrey N. Correll, Michael J. Trimborn
  • Patent number: 9274746
    Abstract: A multi-modal user interface is described that hides response latency delays. A graphical user interface (GUI) supports different user input modalities including low delay inputs which respond to user inputs without significant delay, and high latency inputs which have a significant response latency after receiving a user input before providing a corresponding completed response. The GUI accepts user inputs in a sequence of mixed input modalities independently of response latencies without waiting for responses to high latency inputs, and responds to each user input in the sequence as if each preceding user input in the sequence had been performed without response latencies.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: March 1, 2016
    Assignee: Nuance Communications, Inc.
    Inventors: Andreas Neubacher, Miklós Pápai, Attila Muszta, Herwig Häle, Christina Drexel
  • Patent number: 9246836
    Abstract: A query inserter receives data elements having individual priority types for placement in a queue, and utilizes the priority types of the received data elements to determine placement in the queue relative to an initial location established when a first data element is placed in an empty queue in order to manage the queue with a combination of first-in first-out and last-in first-out queue functionality.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: January 26, 2016
    Assignee: Sybase, Inc.
    Inventor: Shubhra Sankar Biswas
  • Patent number: 9246555
    Abstract: A Near Field Communications (NFC) tag includes a housing and a magnet carried by the housing and configured to be magnetically sensed by a magnetic sensor carried by a communications device to activate an NFC circuit within the communications device to communicate using an NFC communications protocol. A data store stores data regarding a function of the communications device to be magnetically coupled by the magnet. The data store is configured to be read by the communications device using an NFC communications protocol after the NFC circuit had been activated.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: January 26, 2016
    Assignee: BLACKBERRY LIMITED
    Inventors: Jason Tyler Griffin, Steven Henry Fyke
  • Patent number: 9195618
    Abstract: A system for selecting memory requests. The system includes arbiters and a time ordered list scheduler. Each arbiter selects a memory request for transmission from at least one client. The scheduler is operable to receive and store memory requests from the arbiters and selects a selected memory request for forwarding to a memory system. The scheduler includes a list structure operable to store memory requests received from the arbiters in a fashion to preserve relative time of arrival of the memory requests. The scheduler includes scanners that are prioritized with respect to one another. Scanners are operable to simultaneously scan contents of the list structure from the oldest to newest requests and determine whether a memory request match is found based on associated programmable rules to locate a memory request candidate. A memory request candidate of a highest priority scanner is selected by the scheduler as the selected memory request.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: November 24, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Roger Eckert
  • Patent number: 9069447
    Abstract: A mobile terminal includes a controller, a touch screen, a memory configured to store a first list of at least one e-book of a first user and first reading progress information for each of the at least one e-book of the first user, and a communication module configured to receive e-book information including a second list of at least one e-book of a second user and second reading progress information for each of the at least one e-book of the second user. The controller is configured to display at least one icon on the touch screen, each of the at least one icon representing one of the at least one e-book in the first list or one of the at least one e-book in the second list, and display the first and second reading progress information corresponding to at least one e-book included in both the first and second lists.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: June 30, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Miyoung Kim, Yoomee Song, Younghoon Song, Minjeong Lee
  • Patent number: 9069566
    Abstract: Method and system for implementing a multiple writer single reader queue in a lock free and a contention free manner. The method includes receiving a plurality of payloads from a plurality of users, assigning each payload to a writer thread, creating a corresponding writer queue by each the writer threads, enqueuing queue entries into the writer queues maintained exclusively by the each of the writer threads and dequeuing sequentially the queue entries by a reader thread. Further, the method includes adding and removing one or more writer threads in real time. The system includes an electronic device for displaying a plurality of payloads. The system also includes a processor, a memory that stores instructions and a communication interface in electronic communication with the electronic device and the processor.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: June 30, 2015
    Assignee: Hudku Technosoft Private Limited
    Inventors: Arun Kumar, Mehar Vln Simhadri
  • Patent number: 9021228
    Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On
  • Patent number: 9015375
    Abstract: A buffer controller includes a first write pointer generation module for generating a first write pointer that points to a first sequence of write locations in a buffer memory, that directs an input module to store a sequence of samples of a real-time signal in a buffer memory. A read pointer generation module generates a plurality of read pointers for a corresponding plurality of output modules, wherein each of the plurality of read pointers points to a sequence of read locations in the buffer memory, in a buffer order, that contain the sequence of samples.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: April 21, 2015
    Assignee: SIGMATEL, Inc.
    Inventors: Roderick Holley, II, Raymond L. Vargas, John Gregory Ferrara
  • Patent number: 9015379
    Abstract: A method of controlling the data communication in a communications network having a central data server provided data through multiple data queues. The data arriving at the central data server may be stored in each of the multiple data queues. The data in the multiple data queues may then be supplied to the central data server based on a predetermined schedule.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: April 21, 2015
    Assignee: GE Aviation Systems, LLC
    Inventor: Pavlo Bobrek
  • Publication number: 20150106537
    Abstract: A method of controlling the data communication in a communications network having a central data server provided data through multiple data queues. The data arriving at the central data server may be stored in each of the multiple data queues. The data in the multiple data queues may then be supplied to the central data server based on a predetermined schedule.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: GE Aviation Systems LLC
    Inventor: Pavlo Bobrek
  • Patent number: 9002533
    Abstract: A message generation module generates a message that is to be transmitted to a serial data bus of the vehicle once per first predetermined period. A queue manager module resets a timer value when the message is added to a transmit queue and selectively adds the message to the transmit queue when: a number of messages in the transmit queue is less than a first predetermined value; the timer value is greater than the first predetermined period; and one of (i) the first predetermined period is less than a second predetermined period and (ii) the first predetermined period is greater than the second predetermined period and the number of messages in the transmit queue is less than a second predetermined value. The second predetermined value is less than the first predetermined value. A communication control module selectively transmits messages from the transmit queue to the serial data bus.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 7, 2015
    Assignee: GM Global Technology Operations
    Inventors: Matthew Leonard Kaufer, Patrick L. Risse, Thomas A. Crites
  • Patent number: 9003084
    Abstract: Systems and techniques are disclosed that include in one aspect a computer implemented method storing a received stream of data elements in a buffer, applying a boundary condition to the data elements stored in the buffer after receiving each individual data element of the stream of data elements, and producing one or more data elements from the buffer based on the boundary condition as an output stream of data elements sorted according to a predetermined order.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: April 7, 2015
    Assignee: Ab Initio Technology LLC
    Inventors: Craig W. Stanfill, Carl Richard Feynman
  • Publication number: 20150089096
    Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Applicant: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Publication number: 20150089095
    Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Applicant: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Publication number: 20150081932
    Abstract: According to one general aspect, an apparatus may include a source unit, a destination unit, and a plurality of interconnect wires. The source unit may be configured to store, at least temporarily, data, wherein the data is written to a storage structure in a plurality of data structures. The destination unit may be configured to receive at least a portion of the data from the source unit. The plurality of interconnect wires may be configured to transmit, the at least a portion of the data between the source unit and the destination unit. The source unit may include a transmission management unit configured to re-order the data to a re-ordered format, and wherein the re-ordered format is configured to reduce power incurred during the transmission of the at least a portion of the data across the plurality of interconnect wires.
    Type: Application
    Filed: February 11, 2014
    Publication date: March 19, 2015
    Inventors: Karthik RAMANI, Santhosh PILLAI, John BROTHERS, Santosh ABRAHAM
  • Patent number: 8984173
    Abstract: Mechanisms are provided for providing an early warning of an error state of a remote direct memory access (RDMA) resource to a userspace application. The mechanisms detect, using kernelspace logic, an error event having occurred, and perform a write operation to write an error state value to a userspace shared memory state data structure indicating the RDMA resource to be in an error state. The mechanisms detect, using userspace logic, the RDMA resource being in an error state by reading the error state value from the userspace shared memory state data structure in response to a userspace application attempting to perform a RDMA operation using the RDMA resource. In addition, the mechanisms initiate, by the userspace application, an operation to tear down the RDMA resource in response to detecting the RDMA resource being in the error state.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Omar Cardona, Matthew R. Ochs, Vikramjit Sethi