Abstract: A mechanism is disclosed for performing I/O operations using queue banks within a data processing system that supports multiple processing partitions. A queue bank is a re-useable area of memory allocated for performing I/O operations. All memory locking and address-translation functions are generally performed only once for a queue bank to reduce system overhead. After a queue bank has been used to perform an I/O operation, some processing is performed to make it available for re-use. This processing determines whether the queue bank contains memory that is being removed from a current processing partition. If so, a delay is imposed so that the queue bank is not made available for immediate re-use. This creates a window of time wherein all queue banks that contain the affected memory are inactive, thereby allowing the affected memory to be removed from the partition without halting on-going I/O activity.

Abstract: A low latency peripheral device sharing system has a host computer with an operating system, a kernel memory buffer, applications, device specific drivers, and a peripheral server driver. The server driver intercepts function calls invoking the local serial ports, and passes standard serial data from the application to a local area network. A device server on the local area network reads the data using a hybrid read block (semi-blocking read), and writes the data to the FIFO registers of the serial device and the remaining data to a queue for the serial device. Finally, the device server times the serial data and returns an intercharacter interval timer flag to the host computer to terminate a read operation.

Abstract: A method and system for processing out of order frames received by a host bus adapter is provided. The method includes, determining if a current frame is out of order; determining if a frame is within a range of transfer for an Exchange; and creating (or appending if not the first out-of-order frame) an out of order list if the current frame is a first out of order frame. The method also includes, determining if an entry in an out of order list has a relative offset value of zero; determining if at least one entry has a relative offset value equal to a total transfer length of an Exchange; and determining if every non-zero starting relative offset has a matching entry. The method also scans an out of order list and combines a last entry with an entry whose starting point matches the end point of the last entry.

Abstract: A system for processing multiple potentially related requests is provided. The system includes a pending request queue, a related request queue, an in-process queue, and an adapter. The pending request queue receives requests from at least one application. The in-process queue receives a first request from the pending request queue when no other requests are present in the in-process queue related to the first request. The related request queue receives the first request from the pending request queue when other requests are present in the in-process queue related to the first request. The adapter monitors the pending request queue, related request queue, and in-process queue. The adapter also communicates information related to the requests from the pending request queue to the related request and in-process queues as appropriate. The adapter also communicates information related to the requests from the in-process queue to a processor for processing the requests.

Abstract: Embodiments of the present invention provide a media drive that is intended for reduction in power consumption required for serial communications to/from a host, and a power saving method thereof. In one embodiment, a HDD includes: a cache; a host interface for transferring, to a host, transfer data read out from the cache; a host interface manager that controls the execution of commands so as to generate a transfer unnecessary period during which a command and transfer data need not be exchanged with the host; and a MPU that brings a serial communication part of the host interface into a power save mode during the transfer unnecessary period. The host interface manager determines the optimum data transfer timing of transferring data from the cache to the host on the basis of a transfer rate at which data is transferred to the host, and a read rate at which data is read out from a disk into the cache.

Abstract: A technique includes identifying an address of a head end of a queue and monitoring a coherent interconnect to identify a data transfer that is communicated by a producer, which targets the address. The technique includes storing the data of the data transfer in the queue and selectively storing at least a portion of the data in a head-of-queue cache memory based at least in part on whether the monitoring identifies the address. At least a portion of the data is selectively retrieved from the head-of-queue cache memory instead of from the queue for transmission to a consumer.

Abstract: A method of ordering a job queue includes providing a marking system that includes a first marking engine and a storage device storing first and second print jobs in queue. The first marking engine includes first and second metrics. The method includes determining a present state value of the first and second metrics for the first marking engine, and estimating an incremental depletion value of the first and second metrics of the first and second print jobs. The method further includes comparing the incremental depletion value of the first and second metrics, respectively, with the present state value of the first and second metrics for the first marking engine. The method also includes ordering the first and second print jobs in the storage device based at least partially on the comparison. A system is also discussed.

Abstract: A base address sorting device in a switching device is disclosed that includes an array of base address registers in which each base address register contains a base address, an address shifting device; and a control logic element electrically coupled to the array of base address registers and operable, upon receiving a configuration command comprising a new base address, to implement a method for reconfiguring the contents of the array of base address registers. The method includes determining an insertion point base address register in the array of base address registers into which to write the new base address, shifting the contents of one or more base address registers array to other base address registers to preserve the sorted order, and shifting the contents of the configuration command into the insertion point base address register. The inserting results in preserving the pre-determined order of the register array content.

Abstract: A data storage system is provided with command queue controller circuitry for positionally pushing pending access commands from a command queue to a selected target zone of a storage space. A method is provided for dividing a storage space into a plurality of LBA zones, selecting a target zone in relation to a number of pending access commands for each of the plurality of LBA zones, and pushing access commands to the target zone.

Abstract: Methods, systems, and media for enhancing persistence of a message are disclosed. Embodiments include hardware and/or software for storing of a message in an inbound queue, copying the message to a working queue prior to removing the message from the inbound queue, processing the message base upon the copy in the working queue, and storing a committed reply for the message in an outbound queue. Embodiments may also include a queue manager to persist the message and the committed reply after receipt of the message, to close or substantially close gaps in persistence. Several embodiments include a dispatcher that browses the inbound queue to listen for receipt of messages to process, copy the message to the working queue, and assign the message to a thread to perform processing associated with the message. Further embodiments include persistence functionality in middleware, alleviating the burden of persisting messages from applications like upperware.

Abstract: A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.

Abstract: A system for managing inbound messages in a server complex including one or more message consumers. The system includes a server configured to receive the inbound messages from a first peripheral device and to transmit messages to one or more of the plurality of message consumers. The system also includes an inbound message queue coupled to the server, the inbound message queue configured to store inbound message until an age of any message stored on the inbound message queue exceeds a predetermined threshold.

Abstract: Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.

Abstract: An audio system communicates with an aggregate device that includes multiple audio devices. When providing audio data for playback, the system compensates for presentation latency differences between the various audio devices. In addition, the system adjusts for device clock drift by selecting a master device and resampling the audio data provided to the other devices based on the difference between the device clock of the master device and the device clocks of the other devices.

Abstract: Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: A centralized queue for a network printing system is provided for allowing clients of a network printer to make job requests and enter a spot in a job queue without transmitting the actual print job data to the network. More particularly, an imaging device protocol (IDP) is provided which operates independently of the network layers below and only requires that a transport protocol/port be bidirectional. A wide variety of heterogenous network protocols may be supported by IDP for placing all of the incoming print job information in a print queue regardless of the protocol. Print job information from both IDP and non-IDP protocol/ports may be placed in the print queue by emulating IDP on the non-IDP protocol/ports. As a result, job information for all of the print jobs attempting to access a busy printer may be stored in the print queue so that the print jobs can be printed by the printer with a fair arbitration once the network printer becomes available.

Abstract: Systems and methods for enforcing in-order execution of commands sent from a master device to a slave device, where it is not necessary to provide a data buffer to store data associated with commands that are delayed to enforce in-order execution. In one embodiment, when a slave receives an execution synchronization command from a master, it determines whether its command queue contains unissued commands associated with master. If the command queue contains unissued commands, the slave issues a retry responsive to the execution synchronization command. If the command queue does not contain unissued commands, the slave issues an acknowledgment responsive to the execution synchronization command. The master will retry the execution synchronization command until the previous commands have been completed. Because the slave does not queue up any commands that would be delayed by the execution synchronization command, it does not have to provide space to store any associated data.

Abstract: In one embodiment, a data element is passed between a first block and a second block of a block diagram during execution of the block diagram. The first block and the second block negotiate use of a particular input/output (I/O) type from a plurality of available I/O types. The particular I/O type is used with at least one I/O buffer employed in passing the data element between the first block and the second block. The first block may produce a signal representing the data element. The signal is received at the I/O buffer and the data element stored according to the particular I/O type. Subsequently, the data element may be read from the I/O buffer by the second block, which performs an operation, the result of which is used when the block diagram is executing.

Abstract: In one embodiment, an apparatus comprises a queue, write control logic coupled to the queue and operable in a write clock domain, and a first-in, first-out buffer (FIFO) coupled to the write control logic. The queue is configured to store a plurality of data items, wherein each data item has a type which is one of a plurality of types of data items that can be stored in the queue. The write control logic is configured to maintain write pointers that identify entries in the queue for each of the plurality of types. The write control logic is configured to update the write pointer corresponding to an input type for an input data item written to the queue. Additionally, the write control logic is configured to enqueue a write event in the FIFO to transport the enqueue event to a read clock domain different from the write clock domain.

Abstract: A system and method of transferring characters from a first device through a buffer memory to a second device. A descriptor is read and a buffer address and a buffer length are extracted from the descriptor, wherein the buffer address and buffer length define a buffer of data stored in the first device. The data stored in the buffer is transferred from the buffer to the buffer memory, and from there to the second device. A check is made to determine if the descriptor should be closed and, if the descriptor should be closed, an indication is made that the descriptor is closed.

Abstract: A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read value and next read value to a capture latch based on an instruction completion signal. The capture latch can directly drive the checkpoint register circuitry in the recovery unit of the microprocessor. If the queue is empty, a pair of multiplexers connected to the input of the register queue array are used to pass the input data value. The instruction completion signal may indicate whether all instructions in an instruction group have successfully completed.

Abstract: A storage subsystem includes a variable-size write buffer that temporarily stores write data received from a host system. The storage subsystem is capable of adjusting the size of the write buffer so as to vary both the performance (e.g., sustained write speed) of the storage subsystem and a risk of data loss. In one embodiment, the storage subsystem implements a command set that enables the host system to directly control the size of the write buffer. The storage subsystem may additionally or alternatively be capable of adjusting the size of the write buffer based on monitored operating conditions, such as the temperature, the stability/consistency of a power signal received from the host system, and/or the elapsed time since the storage subsystem was last powered up.

Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.

Abstract: Method and system for processing direct memory access (DMA) requests in a peripheral device is provided. The method includes generating a DMA request to transfer information to/from a host system, wherein a size of data transfer is specified in the DMA request and is based on a minimum data transfer size; and submitting the DMA request to an arbitration module to gain access to a bus for transferring the information and while the arbitration module arbitrates between pending DMA requests, the DMA module monitors status from plural buffer slots and before the DMA request is granted, the DMA module modifies the size of data transfer based on available buffer slots.

Abstract: A system for monitoring EF-on-EF jitter in a network node having an EP output queue into which EF packets are entered comprises a first counter that counts the packets entering the queue and also a second counter that counts the packets entering the queue when the queue depth is greater than an operator-determined maximum depth, whereby the operator can compare the two counts to determine the proportion of packets that might be subject to jitter corresponding to the maximum depth. Preferably, the system also includes a third counter that counts the number of packets entering the queue when the queue depth exceeds an alarm depth greater than the maximum depth.

Abstract: The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory addresses that are ordered into a sequence in accordance with the group of buffers. In this way, these embodiments enable a device (e.g., a processor) to directly and sequentially access all of the scattered physical memory locations of a fragmented data item, such as a packet, without having to perform any memory segmentation or paging processes. In some embodiments, these accesses include both read and write accesses to the scattered data storage locations.

Abstract: A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a certain amount of required buffer space for each data stream to be handled without an interruption in recording or playing back the data stream. The method further involves reallocating the amount of required buffer space for each stream including any additional stream when one or more additional streams are to be added to the total number of streams being handled. The method also involves reallocating the amount of required buffer space for each stream including those streams that remain after any of the data streams being handled are terminated.

Abstract: A method and system for providing delay bound and prioritized packet dropping are disclosed. The system limits the size of a queue configured to deliver packets in FIFO order by a threshold based on a specified delay bound. Received packets are queued if the threshold is not exceeded. If the threshold is exceeded, a packet having a precedence level less than that of the precedence level of the received packet is dropped. If all packets in the queue have a precedence level greater than that of the packet received, then the received packet is dropped if the threshold is exceeded.

Abstract: A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.

Abstract: Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, demand evaluation of values, parallel access of multiple threads to a list, synchronized and unsynchronized access to a data buffer, use of forwarding to avoid checking for an end of a buffer, use of sentinel word to detect access past a data structure, concurrent access to a word of memory using different synchronization access modes, and use of trapping to detect access to restricted memory.

Abstract: Events generated by a user of a pointing device are received into an event buffer and eventually removed from the event buffer by a receiving process such as an interface driver associated with an operating system. Information regarding the pointing device events residing within the event buffer is collected and used by a feedback module to improve the computing experience. Feedback regarding the collected information may include visual feedback, audible feedback, tactile feedback, or the like. The present invention improves user interaction with a computing system by providing additional information regarding the status of pointing device events and processes.

Abstract: A stream data buffer device suitable for a client program comprises a buffer having N numbered sub-buffers, a buffer agent having a sub-buffer table recording a state of a corresponding sub-buffer, wherein the state comprising a first state and a second state, and a FIFO queue to record numbers of the sub-buffers having the fist state. When client program receives and stores stream data to stream data buffer, client program requests for a first sub-buffer having second state to store, and after storage, buffer agent changes the state of first sub-buffer to first state and transmits the number of the first sub-buffer to the FIFO queue. When a number of a second sub-buffer having the first state is available, the client program pops the number of second sub-buffer out of FIFO queue and accesses the data thereof, and the buffer agent changes the state of second sub-buffer to second state.

Abstract: A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: Example embodiments of an IOMMU with translation request management and methods for managing translation requests are generally described herein. Other example embodiments may be described and claimed. In some example embodiments, the IOMMU comprises one or more reorder buffers. Each reorder buffer may be associated with one I/O device and may be used to queue pending translation requests for the associated I/O device. A translation request received from a requesting I/O device may be stored in a reorder buffer associated with the requesting I/O device when the translation request is unable to be serviced or when there are one or more pending translation requests in the reorder buffer.

Abstract: A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read value and next read value to a capture latch based on an instruction completion signal. The capture latch can directly drive the checkpoint register circuitry in the recovery unit of the microprocessor. If the queue is empty, a pair of multiplexers connected to the input of the register queue array are used to pass the input data value. The instruction completion signal may indicate whether all instructions in an instruction group have successfully completed.

Abstract: In a multi-queue memory system, a plurality of read count pointers (one for each queue) are stored in a read address file, and used to generate empty flags. A read count pointer associated with a first queue is retrieved from the read address file, and it is determined whether the first queue should be available for a re-read operation. If so, the retrieved read count pointer is stored as a first read mark value. The read count pointer is incremented in response to each read operation performed from the first queue, thereby creating an adjusted read count pointer. If a re-read operation is to be performed from the first queue, the first read mark value is stored in the read address file. Otherwise, the adjusted first read count pointer is stored in the read address file. Similar operations are performed on the write side of the multi-queue memory system.

Abstract: A variable latency elastic buffer comprises a plurality of memory locations in which to hold data. A write and read pointer may point to respective write and read addresses of the plurality of locations in which to write and read data. A controller may hold or increment the address of the read pointer upon determining that the amount of data within the buffer differs from a nominal fill level. In a particular embodiment, initialization circuitry may be operable to initialize the read and write addresses of the respective pointers responsive to an initialization request. The read and write addresses may differ from one another by an offset value equal to a value programmed for the nominal value.

Abstract: A mechanism is presented for processing conditional payment requests in an electronic financial transaction system. In particular, the mechanism provides for the handling of concurrent conditional payment events. The status of a payment condition may be categorized into three categories, and a priority assigned relative to the category. In this way, concurrent events may be prioritized according to their respective categories. Events may then be executed in order of assigned priority.

Abstract: Systems and methods that provide receive queue provisioning are provided. In one embodiment, a communications system may include, for example, a first queue pair (QP), a second QP and a general pool. The first QP may be associated with a first connection and may include, for example, a first send queue (SQ). The second QP may be associated with a second connection and may include, for example, a second SQ. The general pool may include, for example, a shared receive queue (SRQ) that may be shared, for example, by the first QP and the second QP.

Abstract: An apparatus, program product and method of processing access requests for a direct access storage device utilize a “fair elevator” algorithm to schedule access requests from a plurality of requesters desiring access to a direct access storage device (DASD). In particular, a fair elevator algorithm arbitrates requests by taking into account both the requesters with which various requests are associated, as well as the relative positions of the data to be accessed on the DASD. By sorting access requests based upon both requester identity and DASD position, both multitasking performance and DASD throughput are improved in a balanced manner, thus improving overall system performance.

Abstract: Method and apparatus to support efficient check-point and role-back operations for flow-controlled queues in network devices. The method and apparatus employ queue descriptors to manage transfer of data from corresponding queues in memory into a switch fabric. In one embodiment, each queue descriptor includes an enqueue pointer identifying a tail cell of a segment of data scheduled to be transferred from the queue, a schedule pointer identifying a head cell of the segment of data, and a commit pointer identifying a most recent cell in the segment of data to be successfully transmitted into the switch fabric. In another embodiment, the queue descriptor further includes a scheduler sequence number; and a committed sequence number that are employed in connection with transfers of data from queues containing multiple segments. The various pointers and sequence numbers are employed to facilitate efficient check-point and roll-back operations relating to unsuccessful transmissions into the switch fabric.

Abstract: A processor includes a processor core with a core interface unit that includes an age queue and a request queue. The core interface unit receives load requests from the processor core. The request queue stores the requests in respective slots of the request queue. The age queue stores ID tags in respective age queue slots. Each ID tag in the age queue corresponds to a respective address of a load instruction in the request queue. In one embodiment, ID tags propagate through the age queue at a fixed rate of two at a time from a tail of the age queue to a head of the age queue. Arbitration control circuitry generates an enable bit vector that identifies the oldest ID tag in the age queue corresponding to the oldest load request in the request queue. The arbitration circuitry selects the identified oldest instruction in the request queue as the next to dispatch. In one embodiment, the core interface unit exhibits an input frequency that is a multiple of an internal operating frequency of the core interface unit.

Abstract: A method, computer program product, and a data processing system for posting and retrieving WQEs to a shared receive queue in a manner that alleviates head-of-line blocking issues is provided. The present invention provides a shared receive queue and a posting routine for allowing non-sequential work request postings in the shared receive queue. Additionally, a fetch routine is provided for non-sequential fetching of work queue elements from the shared receive queue.

Abstract: A system for providing dynamic queue splitting to maximize throughput of queue entry processing while maintaining the order of queued operations on a per-destination basis. Multiple queues are dynamically created by splitting heavily loaded queues in two. As queues become dormant, they are re-combined. Queue splitting is initiated in response to a trigger condition, such as a queue exceeding a threshold length. When multiple queues are used, the queue in which to place a given operation is determined based on the destination for that operation. Each queue in the queue tree created by the disclosed system can store entries containing operations for multiple destinations, but the operations for a given destination are all always stored within the same queue. The queue into which an operation is to be stored may be determined as a function of the name of the operation destination.

Abstract: A buffer is provided with a leading pointer and a following pointer. A bitmap in which two bits are assigned to each block is updated to retain which states blocks are in, busy, write-completed, or read-completed. Under the constraint that the two pointers move in the same direction and do not pass each other: after the block designated by the leading pointer starts to be written, the leading pointer is moved to a next block only if the next block is in the read-completed state; and after the block designated by the following pointer starts to be read, the following pointer is moved to a next block only if the next block is in the write-completed state.

Abstract: A method, system, and computer program product in a data processing system are disclosed for dynamically selecting software butters for aggregation in order to optimize system performance. Data to be transferred to a device is received. The data is stored in a chain of software buffers. Current characteristics of the system are determined. Software buffers to be combined are then dynamically selected. This selection is made according to the characteristics of the system in order to maximize performance of the system.

Abstract: A bi-directional and full duplex facility for permitting both the IO processor and the Channel to write CCA messages on their respective queues at the same time. IOP messages to the channel are stored on the TO_CHN queue and Channel messages to the IOP on the TO_IOP queue. CCA Queues replace hardware CCAs due to increasing transmission capabilities of current IO processors and Channel processors. Even though the mechanism is similar, the present invention provides some benefits in the use of signaling. The IOP does not have to signal the Channel each time it puts something on its outbound queue. Each queue contains multiple slots. This allows the IOP and Channel to write multiple messages on the targeted queue without encountering a CCA busy signal. The actual queues are now structured in hardware system memory.

Abstract: Provided is a method, system, deployment and program for resource allocation unit queuing in which an allocation unit associated with a task is classified. An allocation unit freed as the task ends is queued for use by another task in a queue at a selected location within the queue in accordance with the classification of said allocation unit. In one embodiment, an allocation unit is queued at a first end of the queue if classified in a first class and is queued at a second end of the queue if classified in said second class. Other embodiments are described and claimed.

Abstract: A multiprocessor system (100) for sharing memory has a memory (102), and two or more processors (104). The processors are programmed to establish (202) memory buffer pools between the processors, and for each memory buffer pool, establish (204) an array of buffer pointers that point to corresponding memory buffers. The processors are further programmed to, for each array of buffer pointers, establish (206) a consumption pointer for the processor owning the memory buffer pool, and a release pointer for another processor sharing said memory buffer pool, each pointer initially pointing to a predetermined location of the array, and adjust (208-236) the consumption and release pointers according to buffers consumed and released.