Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

Abstract: A data processing apparatus may include: a data conversion unit configured to designate one-transfer data as one transfer unit and designate a predetermined number of transfer units as one conversion unit when a plurality of input data sequentially input is converted into transfer data of which the number of bits is the same as that of a data bus having a predetermined number of bits, and the transfer data is sequentially transferred, and arrange the input data in the transfer data within the conversion unit. The data conversion unit may include: a data generation unit, a first data arrangement change unit, and a first data selection unit configured to sequentially select the changed data in which the position of the input data is changed by the first data arrangement change unit and output the selected changed data as the transfer data in the data conversion unit.

Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.

Abstract: Buffer memory reservation techniques for use with NAND flash memory include dynamically reserving regions of the buffer memory, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.

Abstract: An external memory interface includes an input/output (IO) logic unit operable to convert a rate of data from a first rate corresponding to a memory controller/schedule unit to a second rate corresponding to an external memory device. The external memory interface also includes a latency adjustment unit, operating in a timing domain of the memory controller/schedule unit, operable to add between 1 to [(second rate/first rate)?1] cycles of latency of the second rate.

Abstract: Some embodiments provide a media-editing application that includes several background-rendering modules. These modules automatically render segments of a media presentation in the background of a system on which the media-editing application is being executed. By performing rendering in the background, the background-rendering modules produce rendered results for the segments. That is, the modules pre-generate playable media output data (e.g., composite video frames or audio samples) of the media presentation without interrupting other operations (e.g., editing operations, etc.) of the media-editing application. The background-rendering modules in some embodiments include a first background-rendering module and a second background-rendering module. The first background-rendering module determines a prioritized order in which the segments are to be rendered.

Abstract: An adaptive multi-thread buffer supports multiple writer process and reader processes simultaneously without blocking. Writer processes are assigned a reserved write slot using a writer index that is incremented for each write request. When a reserved write slot is not null, the buffer is resized to make room for new data. Reader processes are assigned a reserved read slot using a reader index that is incremented for each read request. When data is read out to the reader process, the read slot content is set to null. When a writer process attempts to write null data to a write slot, the buffer replaces the null write data with an empty value object so that content of the buffer is null only for empty slots. When an empty value object is read from a slot, the buffer replaces the content with null data to send to the reader process.

Abstract: Data-transfer transactions in the read and write directions may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions in the same direction back-to-back for each snapshot.

Abstract: Data-transfer transactions from multiple masters may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions from each master back-to-back.

Abstract: Embodiments relate to providing high throughput hardware acceleration. Aspects include initializing an accelerator control queue (ACQ) configured to provide location information on a plurality of pages of data identified as accelerator data. An originating location of each page of requested target data is determined. The originating location includes one of system memory and disk storage. Based on determining that the originating location is system memory, an entry is created in the ACQ mapping to a system memory source address for the target data. Based on determining that the originating location is disk storage, an entry is created in the ACQ mapping to a special pre-stage buffer source address of a special pre-stage buffer for the target data. Each page of the plurality of pages of target data is accessed by the accelerator from respective locations in said memory or said special pre-stage buffer, based on respective entries of the ACQ.

Abstract: In a system including a plurality of CPU units having a cache memory of different capacity each other and a system controller that connects to the plurality of CPUs and controls cache synchronization, the system controller includes a cache synchronization unit which monitors an address contention between a preceding request and a subsequent request and a setting unit which sets different monitoring range of the contention between the preceding request and the subsequent request for each capacity of the cache memory in each of the CPU units.

Abstract: A system and method for service aware virtualization is disclosed. The system comprises a plurality of virtual instances operating on virtualization software and a plurality of service manager modules operating on the virtualization software. Each service manager module is coupled to a separate virtual instance and configured to interface with an operation of guest software operating within the virtual instance on the virtualization software. A management interface coupled to the service manager modules interfaces with the plurality of virtual instances.

Abstract: Methods and systems for conducting a transaction between a virtual USB device driver and a USB device are provided. A virtual USB manager of a hypervisor receives a one or more data packets from a client. The virtual USB manager stores of the one or more data packets in a buffer. The virtual USB manager dequeues a data packet from the buffer. The virtual USB manager transmits the data packet to the virtual USB device driver for processing.

Abstract: An embodiment of the invention pertains to a method that includes an operating system, program components running on the operating system, and a file system associated with one or more files. Responsive to a write request sent from a specified program component to the operating system, in order to write specified data content to a given file, the method determines whether the write request meets a criterion, which is derived from the identity of at least one of the specified program component, and the given file. If the criterion is met, a message is immediately sent to release the specified program component from a wait state. Data portions of the specified data content are then selectively written to a storage buffer, and subsequently written from the buffer to the given file.

Abstract: An embodiment of the invention pertains to a method that includes an operating system, program components running on the operating system, and a file system associated with one or more files. Responsive to a write request sent from a specified program component to the operating system, in order to write specified data content to a given file, the method determines whether the write request meets a criterion, which is derived from the identity of at least one of the specified program component, and the given file. If the criterion is met, a message is immediately sent to release the specified program component from a wait state. Data portions of the specified data content are then selectively written to a storage buffer, and subsequently written from the buffer to the given file.

Abstract: A terminal data stream (TDS) is received and converted in a pixel-based representation. The pixel-based representation is stored in a frame buffer and a video signal based on the contents of the frame buffer is provided to a video multiplexor. The video multiplexor is also coupled to a video signal from a computer system, and the video multiplexor routes the video signal from the frame buffer to a display device.

Abstract: A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master. An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.

Abstract: Files on a secondary storage are accessed using alternative IO subroutines that buffer IO requests made by a user and mimic the IO subroutines provided by an operating system. The buffer used by the alternative IO subroutines is maintained by the user and not the operating system. User applications are not recompiled or relinked when using the alternative subroutines because the library that provides these subroutines intercepts requests for buffered IO made by user applications to the operating system's IO subroutines and replaces the requests with calls to the alternative IO subroutines that utilize the buffer maintained by the user.

Abstract: An interface device includes a request queue and a request queue manager. The request queue includes multiple elements configured to receive corresponding requests from at least one master device and to indicate whether the corresponding requests are included using corresponding occupying bits. The request queue manager is configured to manage the request queue at least based on the occupying bits.

Abstract: A method of dispatching and transmitting data stream, which is used for a memory storage apparatus having a non-volatile memory module and a smart card chip, is provided. The method includes configuring a plurality of logical block addresses, and a plurality of specific logical block addresses are used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory. The method also includes, when a logical block address corresponding to a read command from a host system belongs to one of the specific logical block addresses and the buffer memory stores a response data unit, transmitting the response data unit stored in the buffer memory to the host system. Accordingly, the method can make the host system to correctly receive the response data unit from the smart card chip.

Abstract: In one example, multimedia content is requested from a plurality of storage modules. Each storage module retrieves the requested parts, which are typically stored on a plurality of storage devices at each storage module. Each storage module determines independently when to retrieve the requested parts of the data file from storage and transmits those parts from storage to a data queue. Based on a capacity of a delivery module and/or the data rate associated with the request, each storage module transmits the parts of the data file to the delivery module. The delivery module generates a sequenced data segment from the parts of the data file received from the plurality of storage modules and transmits the sequenced data segment to the requester.

Abstract: A system and corresponding method for selectively communicating data between a first device and a second device is provided. An indication of a configuration of the second device is received by the first device. A selection signal is generated based on the configuration. Universal Serial Bus (USB) protocol data, uncompressed high definition media data, or a combination thereof may be caused to be selectively supplied to the second device by the first device based on the selection signal. The first device may be configured to transmit, on a DisplayPort link to the second device, a data flow comprising both USB protocol data and uncompressed high definition media data signals. The devices may be configured such that the USB protocol data is transferred from the second device to the first device during a video blanking period associated with the uncompressed high definition media data signals.

Abstract: Embodiments of a bridge circuit and system are disclosed that may allow for converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The bridge circuit may be configured to receive transactions over the first bus and store parameters associated with the received transactions. The bridge circuit may be further configured to modify the received transaction, convert the modified transaction to the second communication protocol, and transmit the converted transaction over the second bus.

Abstract: According to one embodiment, an interface control apparatus includes an interface, and a controller. The interface is configured to transmit information between a host and a data storage apparatus. The controller is configured to fetch request information making a processing request for the data storage apparatus, from an element being a storage unit of a queue provided on the host through the interface. The controller is configured to execute read request processing of fetching first request information divided into a plurality of elements and stored, with priority over second request information which is different from the first request information, when the request information is fetched.

Abstract: A first device of a Multimedia Over Coax Alliance (MoCA) network may communicate with a second device of the MoCA network to control power-save operation of the second MoCA device. The first device may control the power-save operation of the second MoCA device based on an amount of data stored in a buffer, wherein the data stored in the buffer is destined for the second device. The buffer may be in a third device which sends the data to the second device, and/or the buffer may be in the first device. The first device may be operable to buffer data destined for the second device while the second device is in a power-saving state.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: A gasket of a data processing device controls the number of released storage locations of a buffer where read and write access requests are stored so that more read access requests can be stored without a corresponding increase in the amount of space at the buffer to store write access requests. An interface of the gasket accepts new access requests from one or more requesting modules only when a number of released storage locations at a buffer associated with the interface (referred to as an outbound buffer) is above a threshold number. As long as the number of stored access requests at the outbound buffer are less than a threshold amount, a buffer location can be immediately released. In addition, the gasket is configured to issue read access requests from the outbound buffer without regard to whether the inbound buffer has space available.

Abstract: Systems and methods are disclosed to schedule jobs in a cloud computing infrastructure by receiving in a first queue jobs with deadlines or constraints specified in a hard service level agreement (SLA); receiving in a second queue jobs with a penalty cost metric specified in a soft SLA; and minimizing both constraint violation count and total penalty cost in the cloud computing infrastructure by identifying jobs with deadlines in the first queue and delaying jobs in the first queue within a predetermined slack range in favor of jobs in the second queue to improve the penalty cost metric.

Abstract: An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed.

Abstract: A tape drive, tape drive recording system, and method are provided for improving tape speed selection during data transfer. The tape drive includes a buffer, a tape for recording the data to be temporarily stored in the buffer, and a read head. The tape drive further includes a reading controller that initially sets a tape speed such that a drive transfer rate matches a host transfer rate as closely as possible and that drives the tape at the tape speed. To address backhitching caused by one or more host transfer halts, the reading controller subsequently adjusts the tape speed such that the drive transfer rate is lower than the host transfer rate by recalculating the host transfer rate in consideration of the host transfer and the host transfer halt and setting the tape speed such that the drive transfer rate matches the recalculated host transfer rate as closely as possible.

Abstract: An asymmetrical processing multi-core system used in a network device is provided. A sub processing core within the asymmetrical processing multi-core system facilitates a main processing core of the asymmetrical processing multi-core system in processing tasks, thereby improving an overall performance of the entire network device and causing the network device to operate more facilely. Different from a conventional processing method, the asymmetrical processing multi-core system does not require moving or copying a large amount of processed packet data, and thus a large amount of memory bandwidth is saved and the power consumption is reduced.

Abstract: Certain embodiments of the present invention provide for a system and method for preserving bandwidth in data networks. The method includes determining whether to perform functional redundancy processing for a current data set. Determining whether to perform functional redundancy processing for a current data set may be conducted according to redundancy rules. In performing functional redundancy processing, the method includes receiving a first data set and a second data set and storing the first data set in a queue. The method may also include determining whether the content of the first data set is functionally redundant to the content of said second data set. If the contents of the first data set are functionally redundant to the contents of the second data set, the method includes transmitting the first data set and dropping the second data set. Functionally redundant messages are dropped prior to transmission, optimizing bandwidth.

Abstract: A queue number acquiring unit acquires a command queuing number that is the upper limit of the number of process-waiting instructions that can be stored in each of storages that make up a virtual disk for each storage. A minimum queue number selecting unit selects the minimum value of the command queuing numbers of the storages that make up the virtual disk as a minimum queue number. A queue number setting unit sets the selected minimum queue number as the command queuing number of the virtual disk that includes the storage device of which the command queuing number is selected as the minimum queue number for each virtual disk.

Abstract: Various embodiments relate to systems and methods for simultaneously switching input image streams to output devices, while providing optional image processing functions on the image streams. Certain embodiments may provide vision systems and methods suitable for use in vehicles, particularly windowless vehicles, such as armored ground vehicles, submerged watercraft, and spacecraft. Some embodiments may enable sharing of image streams (e.g., with one or more other vehicles), generation of panoramic views (e.g., from various camera feeds), intelligent encoding of image streams, and implementation of security features based on image streams.

Abstract: A method for operating a peripheral device includes receiving at the peripheral device service orders, which are identified with respective service instances and are submitted to the peripheral device over the bus by software applications running on a host processor, which write copies of the service orders to a memory. The received service orders are queued for execution by the peripheral device. When one or more of the service orders have been dropped from the queue prior to execution, a recovery of a selected service instance is initiated by submitting a read request from the peripheral device to the memory over the bus to receive a copy of any unexecuted service order associated with the service instance.

Abstract: A method for managing a queue, such as for example a FIFO queue, and executing a look-ahead function on the data contained in the queue includes associating to the data in the queue respective state variables (C1, C2, . . . CK), the value of each of which represents the number of times a datum is present in the queue. The look-ahead function is then executed on the respective state variables, preferentially using a number of state variables (C1, C2, . . . CK) equal to the number of different values that may be assumed by the data in the queue. The look-ahead function can involve identification of the presence of a given datum in the queue and is, in that case, executed by verifying whether among the state variables (C1, C2, . . . CK) there exists a corresponding state variable with non-nil value.

Abstract: Techniques are described for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information is stored in coalescing memory buffers. To this end, the write operations may be reduced, utilizing the difference information.

Abstract: Described herein are systems and methods for improving concurrency of a request manager for use in an application server or other environment. A request manager receives a request, and upon receiving the request the request manager associates a token with the request. A reference to the request is enqueued in each of a plurality of queues, wherein each queue stores a local copy of the token. A first reference to the request is dequeued from a particular queue, wherein when the first reference to the request is dequeued, the token is modified to create a modified token. Thereafter the request is processed. When other references to the request are dequeued from other queues, the other references to the request are discarded.

Abstract: In an information processor system including a memory device (MEM0), a memory control device (SL0) capable of controlling an operation of the memory device, and a plurality of bus masters (MS0 to MS3) capable of giving access to the memory device through the memory control device, the memory control device includes a control circuit (SDCON) capable of giving a notice of information about a time that a data transfer from the memory device can be started to the bus master related to an access request. The bus master can cause the time information thus given to be a judgment factor as to whether an access request is given to the memory device or not. Consequently, each of the bus masters can avoid the generation of a useless access request and a data transfer to the masters to be accessed can be carried out smoothly.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: Methods for controlling read data buffering are disclosed. In one of the methods core operations are performed in response to a receipt of a read command from a master controller and an internal or external communication buffer of a data storage node is selected to forward information to the master controller. The data storage node is selected based upon constraints and contents of one or more communication buffers. Information is forwarded from the selected internal or external communication buffer to the master controller.

Abstract: A method, apparatus, and machine readable storage medium is disclosed for establishing a test protocol processor which intercepts success path protocol messages at a network element port buffer and substitutes a failure path message to simulate the introduction of unexpected protocol messages into the protocol message flow from an external source to the network element under test. The disclosed self disrupting network element is particularly useful for providing a means to perform in situ field testing of a network element.

Abstract: One embodiment of the present disclosure sets forth an effective way to maintain fairness and order in the scheduling of common resource access requests related to replay operations. Specifically, a streaming multiprocessor (SM) includes a total order queue (TOQ) configured to schedule the access requests over one or more execution cycles. Access requests are allowed to make forward progress when needed common resources have been allocated to the request. Where multiple access requests require the same common resource, priority is given to the older access request. Access requests may be placed in a sleep state pending availability of certain common resources. Deadlock may be avoided by allowing an older access request to steal resources from a younger resource request. One advantage of the disclosed technique is that older common resource access requests are not repeatedly blocked from making forward progress by newer access requests.

Abstract: A system for managing inbound messages in a server complex including one or more message consumers. The system includes a server configured to receive the inbound messages from a first peripheral device and to transmit messages to one or more of the plurality of message consumers. The system also includes an inbound message queue coupled to the server, the inbound message queue configured to store inbound message until an age of any message stored on the inbound message queue exceeds a predetermined threshold.

Abstract: The present invention provides methods and devices for providing a first wagering game (such as a bingo game) that presents a changing pool of displayed game outcomes for a second wagering game (such as a Class III game), preferably on a network of gaming machines. Some implementations of the invention provide a bingo game that presents a changing pool of displayed game outcomes for a slot game or a poker game. In some preferred implementations, game outcomes are generated, e.g., by individual gaming machines, on an ongoing basis and stored in memory. Each of the game outcomes corresponds with a bingo outcome. Preferably, the game outcomes are sorted and stored according to payout amounts for various bingo outcomes. In some implementations, the game outcomes are stored in the form of random number generating (“RNG”) seeds, but in other implementations the game outcomes are stored in a variety of other forms.

Abstract: Examples are disclosed for establishing a window for a queue structure maintained in a cache for a processing element for a network device. The processing element may be configured to operate in cooperation with an input/output device such as a network interface card. In some of these examples, the window may include portions of the queue structure having identifiers to active allocated buffers maintained in memory for the network device. The active allocated buffers may be configured to maintain or store data received or to be forwarded by the input/output device. For these examples, the window may be adjusted based on information gathered while the identifiers are read from or written to the portions of the queue structure.

Abstract: An A/D converter that is attached to a programmable controller (PLC) and sequentially converts an analog value inputted from outside into a digital value. The A/D converter includes: a shared memory that can read-access from a CPU unit that controls the entire PLC and includes a log storage area with a ring buffer configuration for sequentially logging the digital value and a parameter storage area for storing a head pointer serving as a parameter indicating a position where a next log data is stored; and a logging executing unit that writes a digital value in an address indicated by the head pointer in the log storage area as log data and updates the head pointer.

Abstract: Serial communications circuitry is provided that has bonded first-in-first-out (FIFO) buffer circuitry. The circuitry may include state machine and barrel shifter circuitry that conveys data between the bonded FIFO circuitry and a bonded serial communications path. The bonded FIFO circuitry and the bonded lane may increase the efficiency of the serial communications circuitry by reducing the number of empty data bytes buffered in the FIFO circuitry and conveyed over the serial communications path.

Abstract: Herein described are at least a system and a method for regulating data flow in a data pipeline that may be used in a video processing system. The system comprises a processor, one or more data buffers, and one or more processing stations. The one or more data buffers may be used to buffer corresponding processing stations. Each of the one or more processing stations may comprise a switching circuitry that is used to inhibit data transmission when a hold signal is received from the processor. The processor may send the signal in response to a feedback control signal generated by the one or more processing stations. The method may comprise determining if the processing time of a processing station exceeds a specified time. The method further comprises generating a feedback control signal to a processor if the specified time is exceeded.

Abstract: A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer.