Abstract: A method of processing data input to a first-in first-out memory is disclosed. The method comprises steps of receiving input data words from a pipeline stage at an input of the first-in first-out memory; receiving data valid bits associated with the pipeline stage; generating a count associated with the data valid bits; and coupling the count to the first-in first-out memory. The step of generating a count associated with the data valid bits may comprise encoding the data valid bits to generate a valid data word representing the number of pipeline stages having valid data. The method of further comprises a step of generating an almost full signal based upon the count, and in particular generating an almost full signal when a read pointer incremented by the count of valid bits in the pipeline stages equals a write pointer. A circuit for processing data is also disclosed.

Abstract: A storage subsystem includes a variable-size write buffer that temporarily stores write data received from a host system. The storage subsystem is capable of adjusting the size of the write buffer so as to vary both the performance (e.g., sustained write speed) of the storage subsystem and a risk of data loss. In one embodiment, the storage subsystem implements a command set that enables the host system to directly control the size of the write buffer. The storage subsystem may additionally or alternatively be capable of adjusting the size of the write buffer based on monitored operating conditions, such as the temperature, the stability/consistency of a power signal received from the host system, and/or the elapsed time since the storage subsystem was last powered up.

Abstract: Measuring transit time across an asynchronous first-in-first-out (FIFO) memory can include sampling an indication of a value of a read pointer of the FIFO memory at a sampling frequency that exceeds a frequency of a read clock and a write clock of the FIFO memory. An indication of a value of a write pointer of the FIFO memory can be sampled at the sampling frequency. For each sampling period, a measure of occupancy of the FIFO memory can be calculated according to a sampled pair including the indication of the value of the read pointer and the indication of the value of the write pointer. The measure of occupancy can be averaged over a predetermined number of cycles of the sampling frequency. The averaged measure of occupancy can be output as an indication of transit time across the FIFO memory.

Abstract: A system for monitoring EF-on-EF jitter in a network node having an EP output queue into which EF packets are entered comprises a first counter that counts the packets entering the queue and also a second counter that counts the packets entering the queue when the queue depth is greater than an operator-determined maximum depth, whereby the operator can compare the two counts to determine the proportion of packets that might be subject to jitter corresponding to the maximum depth. Preferably, the system also includes a third counter that counts the number of packets entering the queue when the queue depth exceeds an alarm depth greater than the maximum depth.

Abstract: In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct receipt of the predetermined data pattern in a buffer of the second agent, determining in a state machine of the first agent an updated load position within a window of the predetermined data pattern at which the buffer can realize the correct receipt, and transmitting the updated load position to the second agent to enable the second agent to capture incoming data from the first agent at the updated load position. Other embodiments are described and claimed.

Abstract: A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a certain amount of required buffer space for each data stream to be handled without an interruption in recording or playing back the data stream. The method further involves reallocating the amount of required buffer space for each stream including any additional stream when one or more additional streams are to be added to the total number of streams being handled. The method also involves reallocating the amount of required buffer space for each stream including those streams that remain after any of the data streams being handled are terminated.

Abstract: A method and system for providing delay bound and prioritized packet dropping are disclosed. The system limits the size of a queue configured to deliver packets in FIFO order by a threshold based on a specified delay bound. Received packets are queued if the threshold is not exceeded. If the threshold is exceeded, a packet having a precedence level less than that of the precedence level of the received packet is dropped. If all packets in the queue have a precedence level greater than that of the packet received, then the received packet is dropped if the threshold is exceeded.

Abstract: A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.

Abstract: In one embodiment of the present invention, a method includes invalidating an entry of a filter coupled to a pipeline resource if an update to the entry occurs during a first context; and flushing a portion of the pipeline resource corresponding to an address space including the entry.

Abstract: In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space may have entries that include data values associated with the address space identifier.

Abstract: A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A data communication unit comprises a host processor operably coupled to a communication controller having a plurality of buffers comprising a plurality of data elements. The plurality of data elements comprise a lock data element for access by the host processor to acquire sole use of a respective buffer of the plurality of buffers and a commit data element for access by the host processor once sole use of the respective buffer has been acquired wherein use of the lock data element enables the host processor to un-commit a transmit buffer that has previously been committed for transmission by the communication controller.

Abstract: A content-transmitting apparatus transmits reproduction control information including order of reproduction, reproducing section, and reproduction date information of contents which transmitted in the past. In a content-receiving apparatus, when a transmission destination chooses a specific television channel using a receiving side input unit, a receiving side control unit reproduces contents according to the reproduction control information. When the transmission source controls contents including the contents which transmitted in the past to the transmission destination, the transmission destination can view and listen to the contents that the transmission source intends to reproduce, with easiness just like changing television channels.

Abstract: A bridge capable of preventing data inconsistency is provided, in which a first master device outputs a flush request, a buffering unit buffers data or instructions, and a flush request control circuit records a buffer write pointer of the buffer according to the flush request and outputs a flush acknowledgement signal to the first master device in response of that a buffer read pointer of the buffering unit is identical to the recorded buffer write pointer.

Abstract: A multiprocessor system (100) for sharing memory has a memory (102), and two or more processors (104). The processors are programmed to establish (202) memory buffer pools between the processors, and for each memory buffer pool, establish (204) an array of buffer pointers that point to corresponding memory buffers. The processors are further programmed to, for each array of buffer pointers, establish (206) a consumption pointer for the processor owning the memory buffer pool, and a release pointer for another processor sharing said memory buffer pool, each pointer initially pointing to a predetermined location of the array, and adjust (208-236) the consumption and release pointers according to buffers consumed and released.

Abstract: A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is delimited by only a tail pointer stored in a tail pointer list. Following dequeuing the string for processing, a pointer to the one command block of the string that was in the common queue is included in a string head pointer list. The tail pointer to the string is not changed in the tail pointer list following dequeuing of the string. This allows any new SCBs to be appended to the end of the string, while the string is being processed. This allows streaming of new SCBs to an I/O device that had previously been selected and is still connected to the host adapter.

Abstract: In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later time; (3) notifying second logic of the controller of the request; (4) determining at least one of whether the request is valid and enough buffers are available to complete the request; (5) programming a filtering pipe; and (6) responding to the first logic based on at least one of whether the request is valid and enough buffers are available to complete the request such that the first logic may employ the filtering pipe to complete the request. The first logic operates in a first clock domain and second logic operates in a second clock domain. Numerous other aspects are provided.

Abstract: Methods and apparatus for using a predetermined portion of main memory as extended disk buffer memory that is used as disk buffer memory for a disk drive. A controller causes data, such as prefetched data, to flow between disk electronics and the extended disk buffer memory. Data is stored in the extended disk buffer memory along with the logical block address associated with that data and with validation information. Valid data recalled from the extended disk buffer memory can be used directly by the processor without going to the disk drive. In some embodiments the extended disk buffer memory can provide all of the disk buffer memory, while in other embodiments the extended disk buffer memory is augmented by disk drive buffer memory.

Abstract: The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.

Abstract: Method and system for a dynamic FIFO flow control circuit. The dynamic FIFO flow control circuit detects one or more obsolete entries in a FIFO memory, retrieves the address of the next valid read pointer, and reads from the retrieved address during the next read operation.

Abstract: Disclosed is a method for minimizing the buffer size of an elasticity FIFO queue when synchronizing data between two clock domains. Data communication is typically sent by a transmitter device to a receiver device. The transmitted data signal includes an embedded clock signal and null data characters, as specified by the data communication signal protocol. A null character indicates an empty data frame and is included as part of most standard communication protocols. An embodiment skips one or more null characters from the elasticity FIFO queue during a single clock cycle when it is detected that the write pointer is catching up to the read pointer. By skipping multiple null characters during a single write cycle, the read pointer is moved ahead by one or more queue locations and the write pointer is insured to not catch up to the read pointer for a wider variation in frequencies between a transmitter and receiver than is normally possible.

Abstract: The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by t

Abstract: Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned by a DMA controller, for moving data between a data port and a corresponding memory buffer. A write command is placed on a memory exchange queue to change the owner to a different processor and the private index data is incremented. A public index is determined, which indicates a different buffer descriptor in which the owner is most recently changed to the processor and is known to be visible to the processor. In response to receiving a request from the processor for the most recent buffer descriptor changed to processor ownership, the public index data is sent to the processor. Based on the public index data, the processor exchanges data with buffer descriptors guaranteed to be owned by the processor.

Abstract: A method for allocating buffer capacity includes determining at least one characteristic of a first input/output (I/O) device that is coupled to a memory device interface, the memory device interface being configured to enable data transfers between the I/O device and a memory device, and buffering data corresponding to the first I/O device in a first portion of a buffer of the memory device interface, a size of the first portion being responsive to the at least one characteristic of the first I/O device.

Abstract: Multi-queue first-in first-out (FIFO) memory devices include multi-port register files that provide write count and read count flow-through when the write and read queues are equivalent. According to some of these embodiments, a multi-queue FIFO memory device includes a write flag counter register file that is configured to support flow-through of write counter updates to at least one read port of the write flag counter register file. This flow-through occurs when an active write queue and an active read queue within the FIFO memory device are the same. A read flag counter register file is also provided, which supports flow-through of read counter updates to at least one read port of the read flag counter register file when the active write queue and the active read queue are the same.

Abstract: A buffer architecture enables linked lists to be used to administer virtual output queue buffering. The buffer has three random access memories (RAMs). A data RAM holds data. A free RAM holds a linked list of entries defining free space in the data RAM. Destination RAM holds a linked list of entries defining data in the data RAM to be forwarded to a destination.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms for maintaining counters, such as in, but not limited to a packet switching system, and updating a secondary counter storage based on values of the counters and entries in an overflow buffer. Multiple counter values are stored in a counter bank. An indication of a particular counter of the multiple counters to update is received. A current value of the particular counter is updated in the counter bank, and if an overflow condition results, then an indication of the particular counter is added to an overflow buffer. Periodically each of the multiple counters is visited and corresponding values are updated in a secondary storage, and each entry is retrieved from the overflow buffer and a corresponding value is updated in the secondary storage.

Abstract: In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later time; (3) notifying second logic of the controller of the request; (4) determining at least one of whether the request is valid and enough buffers are available to complete the request; (5) programming a filtering pipe; and (6) responding to the first logic based on at least one of whether the request is valid and enough buffers are available to complete the request such that the first logic may employ the filtering pipe to complete the request. The first logic operates in a first clock domain and second logic operates in a second clock domain. Numerous other aspects are provided.

Abstract: A circuit for interfacing between a first component 11 operating at a first clock rate and a second component 12 operating at a second clock rate, wherein the second clock rate is higher than the first clock rate. The circuit comprises a first buffer 13 coupled to the first component 11; a second buffer 14 coupled to the second component 12; and a copy/access controller 15, 16, 17 connected to the first buffer 13, the second buffer 14, and the second component 12. The copy/access controller 15, 16, 17 is operable to copy data from the first buffer 13 to the second buffer 14 when the first buffer 13 is substantially full. It is also operable to prompt the second component 12 to access the second buffer 14 when the data is copied from the first buffer 13. The buffers can be random access memories or shift registers, and can be integrated onto the same semiconductor die as either the first or second component.

Abstract: A buffer includes an input unit that inputs data; an output unit that outputs the data; a plurality of registers that stores the data while sequentially shifting the data from the input unit to the output unit; an output-data selecting unit that selects desired data from among the data stored based on a predetermined priority, extract the desired data from a corresponding register, and outputs the desired data to the output unit; a detecting unit that detects an error in the desired data; a diagnostic-data writing unit that writes diagnostic data for diagnosing failure of the register in the register from which the desired data is extracted; and a diagnostic-data error detecting unit that detects an error in the diagnostic data.

Abstract: A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a register with a processor, continuously accessing data from the register with the processor if the data in the register is valid, enabling an identifier register with the processor if the data in the register is invalid, transmitting an interrupt signal to the processor, disabling the identifier register with the processor, and accessing the data from the register with the processor.

Abstract: A method of operating a circuit, comprising the steps of (A) buffering a read signal received within a plurality of first transfers to the circuit, (B) transmitting the read signal in a second transfer from the circuit, (C) buffering a first write signal received in a third transfer to the circuit and (D) transmitting the first write signal within a plurality of fourth transfers from the circuit.

Abstract: A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.

Abstract: A system is described for providing a patch mechanism within an input/output (I/O) controller, which can be used to workaround defects and conditions existing in the I/O controller. The system includes a patch module coupled to a completion queue included in the I/O controller. The patch module is used to sample incoming cycles received by the I/O controller and to determine if the captured incoming cycle matches one or more of preprogrammed trigger conditions. The patch module is capable of working around a captured non-posted request cycle by controlling header information loaded into the completion queue and by instructing the completion queue whether or not to discard a completion received from a designated end-device.

Abstract: Techniques for verifying input/output (I/O) command data are provided. Information about the contents of the data are specified in the I/O command. After an application issues the I/O command, a subsequent component, such as a controller, uses the information to verify the contents of the data before the I/O command is performed.

Abstract: A process and software for aggressive capture of digital recording on computers, for the purpose of reducing audio latency, which includes periodic frequent polling of a recording buffer containing audio recording data and a known value, reading out data values that do not match the previously written known value, and writing over the data with the known value.

Abstract: A method and apparatus for protecting against a buffer over flow attack. In one variation, an executable software program is divided into an executable image, a data image, and an execution history image. The operating system processes an executable statement in the executable image. Other statements are processed in the data image. In a second variation, the execution history image is made use of in addition to the tasks of the first variation. Each statement is classified as either mutable or immutable. The usage of statements is recorded in the execution history image. If a mutable statement has over-written an immutable statement memory location, then the program is terminated. Optionally, the entire program is re-mapped using the execution history image such that immutable statements cannot over-write mutable statements.

Abstract: An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.

Abstract: Multiple non-blocking FIFO queues are concurrently maintained using atomic compare-and-swap (CAS) operations. In accordance with the invention, each queue provides direct access to the nodes stored therein to an application or thread, so that each thread may enqueue and dequeue nodes that it may choose. The prior art merely provided access to the values stored in the node. In order to avoid anomalies, the queue is never allowed to become empty by requiring the presence of at least a dummy node in the queue. The ABA problem is solved by requiring that the next pointer of the tail node in each queue point to a “magic number” unique to the particular queue, such as the pointer to the queue head or the address of the queue head, for example. This obviates any need to maintain a separate count for each node.

Abstract: A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

Abstract: A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability.

Abstract: Synchronized data is written to magnetic tape while reducing the number of backhitches. A controller detects a pattern of synchronizing events for received data records to be written to tape; writes each transaction of data records to the magnetic; tape; accumulates the synchronized transactions in a buffer; and subsequently recursively writes the accumulated transactions of data records from the buffer to the magnetic tape in a sequence. A single backhitch may be employed to place the recursively written accumulated data records following the preceding data, maximizing performance and capacity.

Abstract: Buffer control means and output control means are included within a buffering apparatus. Data longer than the width of data bus is read by single access from buffer means. Rather than signal line control for each bus width, signal line control for each data group is performed by a method wherein address administration means holds address information in relationship with each group of a series of data written in the buffer means and data is output from the buffer means.

Abstract: A data transmission system where an image providing device and a printer are directly connected by a 1394 serial bus, a command is sent from the image providing device to the printer, then a response to the command is returned from the printer to the image providing device. Image data is sent from the image providing device to the printer based on information included in the response. The printer converts the image data outputted from the image providing device into print data. Thus, printing can be performed without a host computer by directly connecting the image providing device and the printer by the 1394 serial bus or the like.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer.

Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.

Abstract: A client driver requests data packet transfers from a peripheral device through a protocol stack and a host controller. The protocol stack receives the data transfer request and allocates the request into the host controller schedule. The host controller schedule requests the data of the peripheral device, and directs the received data into previously allocated buffers. The host controller then sends a signal to the client driver that the respective buffers are filled. The host controller can then deactivate the instructions in the host controller schedule until further notice so that the instructions do not need to be deleted from the schedule. The client driver extracts the data from the buffer, and sends a signal to the host controller that the buffer can be used again. The request in the host controller schedule can then be reactivated without having to necessarily re-insert new instructions into the host controller schedule.

Abstract: A method, apparatus, system, and signal-bearing medium that in various embodiments determine whether to execute a command in a queue or whether to wait until another command or commands completed. The determination is based on a combination of an in-use vector and a scorecard vector. The in-use vector indicates which slots in various queues contain commands. The scorecard vector indicates the dependencies between various queues. In this way, the scorecard vector, and the thus the queue dependencies can be set and modified after the logic that processes the commands has been designed.

Abstract: A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component to the apparatus for storing information utilizing the clock of the first component, a second component operated in response to the timing of a second clock, apparatus for utilizing the clock of the second component to transfer information from the apparatus for storing information in a condition in which it is synchronized for use by the second component whereby the information may be immediately utilized by the second component without the need for storage by the second component.