Abstract: In a high-performance data storage system, an enclosure contains a multiplicity of disk drives, each of which has two high-speed serial data ports. Respective data lines are provided which connect each of the data ports with a respective high-speed data multiplexer. Importantly, each of the multiplexers is also connected with each of two distinct I/O modules. Failure of either I/O module still permits the remaining I/O module to have serial high-speed connectivity with each of the multiplexers, and thus with each of the data ports on each disk drive. Finally, the overall function of the system may be selected as JBOD (Just a Bunch Of Drives), as SAN (Storage Area Network), or NAS (Network Attached Storage), without requiring any mechanical or electronic change other than the I/O modules.

Abstract: If a recording medium having a medium ID is used, a secure manager manages enciphering/decoding of a content with use of the medium ID for each recording medium. If a HDD having no medium ID is used, the secure manager obtains a device ID specific to a computer system through a BIOS and manages enciphering/decoding of a content to be recorded into the HDD, with use of the device ID. The device ID is stored in a safe area in the computer system. As a result, even if a content is recorded into an open recording medium such as a hard disk drive, the content can be protected from improper use so that utility and protection of digital contents can be improved.

Abstract: In a computer system, an agent, a DMA controller and a memory controller are provided, each in communication with a bus. The DMA controller and the memory controller also can communicate with each other via a second communication path. The computer system may include a memory provided in communication with the memory controller having a coherent memory space and a non-coherent memory space. The DMA controller transfers a portion of data from the coherent memory space with a portion of data from the non-coherent memory space with a single transaction on the external bus.

Abstract: The cache keeps regularly accessed disk I/O data within RAM that forms part of a computer systems main memory. The cache operates across a network of computers systems, maintaining cache coherency for the disk I/O devices that are shared by the multiple computer systems within that network. Read access for disk I/O data that is contained within the RAM is returned much faster than would occur if the disk I/O device was accessed directly. The data is held in one of three areas of the RAM for the cache, dependent on the size of the I/O access. The total RAM containing the three areas for the cache does not occupy a fixed amount of a computers main memory. The RAM for the cache grows to contain more disk I/O data on demand and shrinks when more of the main memory is required by the computer system for other uses.

Abstract: A barrier control scheme controls the order dependency of items in a multiple FIFO queue structure. The barrier control scheme includes a cycle ID generator, a barrier bit/barrier ID generator and a cycle ID and barrier ID comparator. Each incoming item to the FIFOs is assigned a cycle ID. If an incoming item of a first FIFO has order dependency on items of a second FIFO, a barrier bit is set and a barrier ID is determined and generated by the barrier bit/barrier ID generator. The barrier bit and barrier ID are inserted in the first FIFO along with other fields of the incoming item. When an item is to be consumed, the cycle ID and barrier ID comparator compares its barrier ID and the cycle IDs of items in the second FIFO. The item to be consumed is blocked until all items on which the item is dependent are consumed in the second FIFO.

Abstract: A mechanism that includes an apparatus and method for ensuring that all transactions within any flow control class completes is herein provided. The mechanism includes a plunge transaction that is inserted in each pending transaction queue and which is transmitted to a particular destination device. All prior transactions in a flow control class are deemed to be complete when the destination device receives the plunge transactions in the flow control class.

Abstract: In one embodiment of the present invention, an output device sends a spurious data sample in place of a first data sample to be sent from a queue if the queue is in a state of underflow during which the first data sample is not available to be sent. The buffer is to store data samples for an isochronous data transmission. Circuitry skips the first data sample when the first data sample becomes available in the queue so that synchronization for subsequent data samples sent from the queue is preserved. In another embodiment of the present invention, an input device advances an input buffer pointer to point to a next location in a memory in response to receiving a data sample at a queue during a state of overflow. The input buffer pointer indicates a location in the memory to which a next data sample is to be sent from the queue. The queue stores data samples for an isochronous data transmission. By advancing the input buffer pointer, synchronization for subsequent data samples is preserved.

Abstract: A method and apparatus is presented providing high-performance lossless data compression implemented in hardware for improving network communications. A compression module useful in a switching platform is also presented capable of compressing data stored in buffer memory. Instructions for a compression task are assigned to the compression module by a microprocessor writing a control block to a queue in stored local memory. The control block informs the compression module of the size and location of the unprocessed data, as well as a location in the buffer memory for storing the processed data and the maximum allowed size for the compressed data. Using this technique, the microprocessor can limit the compression of data to those data streams allowing compression, to those segments that are susceptible to compression, and to those segments that are large enough to show a transmission speed improvement via compression.

Abstract: A buffer for adapting data flows from input channels to output channels is provided. The buffer includes a DRAM organized in blocks and a memory controller for managing assignment of the blocks to the chains of linked blocks. The DRAM contains, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, and also contains a main queue of free blocks for listing unoccupied blocks. The memory controller includes a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment. According to one embodiment, when a level of the partial queue reaches a predetermined minimum limit the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit the cache memory is at least partially emptied by a burst into the main queue.

Abstract: A host controller, such as a host controller for a Universal Serial Bus, may process isochronous and interrupt transfers on a preferential basis. If time permits, bulk and control transfers may be executed. The bulk and control transfers may be executed in queues having a queue context made up of a queue head and one or more transfer descriptors. These queues may be processed one after another in a circular linked list. By uniquely marking an element in the circular linked list and determining the status of the transfer operation, the host controller can be avoid thrashing the bus when the reclaim list is empty.

Abstract: Deter the lowering of the efficiency of data exchange in a data processing device that conducts data communications by using a serial bus conforming to the IEEF 1394 Standards.

Abstract: A memory management technique for maintaining packet order in a packet processing system involves maintaining a START indicator and a VALID indicator for each memory block in a packet memory. Packets are written in a number of successive memory blocks, and the START indicator corresponding to the first memory block of the number of successive memory blocks is set to indicate that the packet is available for processing. The packets are processed by a packet processor. When the packet processor completes the processing of a particular packet, the VALID indicator corresponding to the first memory block associated with that packet is set to indicate that the packet is ready to be forwarded. The packet may become ready to be forwarded out of order.

Abstract: A queue having a ‘duplicate’ counter associated with each entry whereby duplicate data is not stored in the queue. Before data is placed in the queue, the queue is searched for an entry matching the data to be written. If a match is found, the duplicate counter associated with the entry is incremented. Further, if a match is found and the data stored therein is inconsistent with the current data, the contents of the queue are updated and the duplicate counter associated with the entry is reset to one. If a match is not found, the data is written to the queue and the duplicate counter associated with the entry is initialized to one.

Abstract: A network interface device and a method of transferring data between a host and a network medium employs transmit descriptors that do not contain transmit status information. Upon fetching a transmit data frame from a host system memory at a location pointed to by a transmit descriptor, the network interface device immediately generates an interrupt to the CPU to allow the CPU to re-use the buffers in which the data frame was stored. At the same time, the network interface device attempts transmissions of the data frame to the network medium. Transmit status information is kept in statistics counters on the network interface device.

Abstract: A method of deadlock-free, automatic configuration and reconfiguration of modules having a two- or multidimensional cell arrangement, in which a unit for controlling the configuration and reconfiguration manages a set of associated configurable elements, the set being a subset or the total set of all configurable elements, and the management takes place as follows: reconfiguration requests from the associated configurable elements are sent to the unit; the unit processes the requests; the unit processes the configuration data of the command sequence; and after the configuration data has been fully processed, new requests are accepted again, the configuration data still to be loaded of the existing previous requests being loaded from a buffer memory (FILMO) into the configurable elements until a new request occurs.

Abstract: The present invention relates to a queuing system, implemented in the memory of a computer by the execution of a program element. The queuing system includes a queue with a plurality of memory slots, a write pointer and a read pointer. The write pointer permits to enqueue data elements in successive memory slots of the queue. The read pointer permits to dequeue data elements from the queue memory slots for processing, where these data elements are potentially non-dequeuable. Upon identifying a non-dequeuable data element in a particular memory slot of the queue, the read pointer is capable to skip over the particular memory slot and move on to a successive memory slot.

Abstract: A main data memory is provided in a network device and includes a plurality of buffers for storing data packets. A plurality of descriptors, or pointers, point to the individual buffers. A status of the descriptors is stored in a descriptor reference memory. The status information includes whether the descriptors are in an active or free state, and an indication of copies of the descriptors in the transmit queues. A descriptor free pool includes a list of the descriptors in the free state.

Abstract: A command queue control device, when there is the command which is not completed in spite of a lapse of prescribed time period, is capable of facilitating the command processing of the disk device, even though delay occurs in the command processing of the disk device, by causing the disk device to facilitate acceleration of the command.

Abstract: In a computer system, an agent, a DMA controller and a memory controller are provided, each in communication with a bus. The DMA controller and the memory controller also can communicate with each other via a second communication path. The computer system may include a memory provided in communication with the memory controller having a coherent memory space and a non-coherent memory space. The DMA controller transfers a portion of data from the coherent memory space with a portion of data from the non-coherent memory space with a single transaction on the external bus.

Abstract: A need to store data between a producing stage and a consuming stage commonly arises in digital processing applications. However, factors such as fabrication process limitations and circuit area constraints may restrict the amount of available storage. A novel method and apparatus for data buffering are disclosed which use less data storage than would be required by double buffering techniques.

Abstract: To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

Abstract: The present invention protects against failures due to data unavailability in real-time data processing. The last state of data stored in an output buffer is computed, and a pointer is updated based on the last state of the data stored in the output buffer to point to a starting location of a buffer storing spurious data. In one embodiment, if the data stored in the output buffer is entirely consumed in real-time before new data is written, the pointer is used to begin consuming the spurious data in real-time.

Abstract: An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

Abstract: In accordance with the present invention, an FPGA input/output buffer including a tristate enable register is provided. A bus line provides the FPGA output through a tristate buffer to the pad or pin. A register controls the state of the tristate buffer. A register for providing an input signal from the pad or pin may also be provided. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the output control register and for loading data into the input register.

Abstract: A file control part 1 newly opens a file A in a file storage part 11 through a file accessing part 2, and secures a file data area having a certain size. An input/output control part 4 issues a request of writing into the file A to the file control part 1, and then writes data supplied from an input/output device 7 directly to a proper position of the data portion of the file A stored in a storage part 6 on the basis of information about the file A from the file control part 1. When the size of data to be written exceeds the file size previously secured, an input/output file managing part 8 requests again the file control part 1 to supplement a file data area having a certain size and makes it supplement the file data area.

Abstract: In a command processing system for processing a command sent from an external controller (111) to an equipment (100, 200) via a digital interface (112), a status/command storage unit (103) stores the last executed commands to inform the external controller (111) of contents thereof in response to the command. Meanwhile, a management information storage unit stores the management information just before and just after execution of the received command, wherein upon receipt of a command (Z) for inquiring contents of the previously executed commands, the commands (X, Y) stored in the status/command storage unit (103) are read out to produce a response data to the inquiring command. Thus, the user can easily know the content of the last control command provided for controlling equipment.

Abstract: An input/output (I/O) controller in an I/O system processes I/O requests from a host computer to a plurality of I/O devices. The I/O controller generates an interrupt to the host computer and reports a plurality of completed I/O requests from the I/O devices when at least one condition of the I/O system is met. A first condition of the I/O system comprises a predetermined ratio between the total number of unreported I/O completions by the I/O devices and the total number of remaining I/O requests from the host computer. A second condition comprises the expiration of a timer, which starts when the number of remaining I/O requests left to process for any individual I/O device reaches a predetermined minimum limit.

Abstract: To provide a programmable controller for enabling a device value to be set and changed, and also referenced, easily and accurately. A programmable controller has a main unit CPU, a storage section, a display CPU, a display section, and a key section. The state of the key section is stored in a key information buffer of the display CPU. A control section of the display CPU sets and changes the device value stored in the storage section through the main unit CPU and causes the display section to display the device value stored in the storage section based on key information in the key information buffer.

Abstract: A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A method in a computing system (100) includes the steps of enqueuing items in a functional queue prioritized according to sort criteria (132), modifying the sort criteria (132) while the functional queue contains the enqued items, and re-prioritizing the enqued items in the functional queue according to the modified sort criteria (132). The computing system (100) includes a set of functions (122) that operate on a queue data structure (130) to maintain enqued items prioritized in the queue data structure (130) after changes in the sort criteria (132). The set of functions (122) operate with an arbitrary number of sort criteria (132) and with arbitrary values for the sort criteria (132).

Abstract: A Graphics Engine (GE) FIFO interface architecture that allows the transfers of reduced address information from the GE to the frame buffer is provided. The FIFO interface architecture further allows the GE to be isolated from the Memory Interface Unit (MIU) or the Central Processor Interface Unit (CIF) such that the GE can operate at a different frequency from the MIU and the CPU. Address information is provided using two flag bits End of Line (EOL) and Add One (AO). In write mode, flag bits EOL and AO are used to determine the next address in the frame buffer where processed data from the GE is to be stored. In line draw mode, flag bits EOL and AO are used to determine the address in the frame buffer for data retrieval. Such data retrieval allows a rendered line to perform background and foreground color ROP in line draw commands. Flag bit EOL indicates whether the GE needs to skip to the next scan line (e.g., the end of the current scan line has been reached).

Abstract: An interface between a network communication card and an industrial controller allows rapid asynchronous buffering using two buffers and two associated registers for each data direction. A reading of the buffers is proceeded by an attempt to copy from the write designation register to the read designation register checking the equality of the register values and then reading from the buffer designated by their common value. Conclusion of the reading sets the write destination register to zero. Writing of the buffers is proceeded by a checking of the read designation register for zero value and then writing to other than the last buffer indicated by the write designation register. If the read designation register is non-zero, then the writing occurs to the opposite buffer of that in the read designation register. The write designation register is then updated to indicate the buffer written to.

Abstract: A programmable split-queue structure includes a first queue area for receiving entries, a second queue area for outputting entries input to said first queue area, and a queue overflow engine logically coupled to the first queue area and the second queue area. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using one of two transfer modes. The queue overflow engine selects the most appropriate transfer mode based on a prescribed threshold value that can be dynamically programmed. An overflow storage area having high capacity may be provided in an external memory in order to increase the overall capacity of the queue structure.

Abstract: The present invention discloses a method and apparatus for processing a packet of data received from a direct memory access (DMA) engine. In one embodiment, a counter generates a self-ID code and increments the self-ID code after a bus reset. A formatter is coupled to the counter to format a start-of-packet (SOP) message which contains a self-ID field. The SOP message corresponds to the packet and the self-ID field corresponds to the self-ID code. A first-in-first-out (FIFO) is coupled to the formatter to store the SOP message and the packet. A comparator is coupled to the FIFO to compare the self-ID field of the message read from the FIFO with the self-ID code. A control circuit, which is coupled to the FIFO, flushes the packet if the self-ID field of the message is different than the self-ID code.

Abstract: A data processing apparatus temporarily stores data to a cache write buffer and then stores the data in a cache storing device. The cache storage device performs a data storage operation with precedence over another operation even if a store instruction contends with a read instruction for accessing the cache storing device. A storage request low signal, sent from a cache write buffer controlling device to a cache controlling device, allows a read request to have precedence over a store instruction even when there is data stored in the cache write buffer waiting to be transferred to the cache storing device in response to the store instruction.

Abstract: A write combining buffer that supports snoop requests includes a first cache memory and a second cache memory. The apparatus also includes a write combining buffer, coupled to the first and second cache memories, to combine data from a plurality of store operations. Each of the plurality of store operations is to at least a part of a cache line, and the write combining buffer can be snooped in response to requests initiated external to the apparatus.

Abstract: A process and software for aggressive capture of digital recording on computers, for the purpose of reducing audio latency, which includes periodic frequent polling of a recording buffer containing audio recording data and a known value, reading out data values that do not match the previously written known value, and writing over the data with the known value.

Abstract: A method and apparatus for selectively using input/output (I/O) buffers as a retransmit vehicle in a client/server system. The decision whether to use an I/O buffer as a retransmit vehicle is based on a number of factors, including the packet size, the expected round-trip time (RTT) for an acknowledgment of the transmission, the number of I/O buffers currently allocated, and the number of I/O buffers remaining. If the decision is made not to use the I/O buffer as a retransmit vehicle, then the data is copied into a send buffer that is maintained by the system for the particular requester. Initially three threshold values, the round-trip time (RTT) threshold, the critical threshold, and the tight buffer threshold, are set. Connections having a longer round-trip time than a set round-trip time threshold or connections made when the number of I/O buffers remaining is below the critical threshold are not allowed to keep the I/O buffer as a retransmission vehicle.

Abstract: A bus bridge receives an inbound read request from a master. In response to the read request, the bridge transmits multiple (e.g., two) read request packets to fetch data. The fetched data is stored in the bridge when it returns. When the master returns for its data, the data from each packet is transferred to the master if the data is valid. By issuing two smaller read request packets in response to an inbound read request, inbound read latency is reduced. In addition, if only a single master is being serviced, the system speculatively prefetches data for the master when the master returns to receive its data. Also, if the master is disconnected before completing the data transfer, the data can be subsequently restreamed from the bridge if the data is still valid when the master reconnects.

Abstract: In the event that a host device does not have a transmitting FIFO and receiving FIFO independently, but shares one FIFO for both transmission and reception, and an error occurs at the destination of transmission, the host cannot receive error information unless the FIFO is emptied. Accordingly, the printer according to the present invention secures a stand-by area in the reception buffer that is the same capacity as the FIFO at the host. In the event that an error occurs, transmission of data from the host is stopped, and if there is no available area except for the stand-by area within the reception buffer, the stand-by area is released to empty the FIFO.

Abstract: An apparatus and method for restreaming data that has been queued in a bus bridging device. Data received via a first bus is stored in a first queue. A first portion of the data is output from the first queue onto a second bus while a second portion of the data remains in the first queue. In response to another data value being transferred from the first bus to the second bus before the second portion of the data is output to the second bus, the second portion of the data in the first queue is invalidated.

Abstract: A system and method for providing transaction indivisibility in a transaction processing system through the use of commonly-accessible modules for monitoring and maintaining proper source message sequencing is provided. A source message is transmitted from the host processing unit upon recovery of a failure of the host processing unit, where the source message includes information destined for the database, and an identifying sequence number. The identifying sequence number is compared to a stored sequence number, where the stored sequence number is associated with an immediately preceding source message received prior to the failure of the host processing unit. A source message indivisibility failure is indicated where the identifying sequence number is not consecutive with respect to the stored sequence number, while the source message is added to a message execution queue if the identifying sequence number is consecutive with respect to the stored sequence number.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The read and write controllers output status information corresponding to the reading or writing of a stored data frame in the receive buffer. The memory management unit includes a synchronization circuit, which arbitrates updates to the holding registers by the read and write controllers based on the asynchronously determined presence of at least one stored data frame.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values. The memory management unit also includes a descriptor management unit for controlling DMA transfers between the transmit and receive buffers and the system memory.

Abstract: A data recirculation apparatus for a data processing system includes at least one output buffer from which data are output onto an interconnect, a plurality of input storage areas from which data are selected for storage within the output buffer, and selection logic that selects data from the plurality of input storage areas for storage within the output buffer. In addition, the data recirculation apparatus includes buffer control logic that, in response to a determination that a particular datum has stalled in the output buffer, causes the particular datum to be removed from the output buffer and stored in one of the plurality of input storage areas. In one embodiment, the recirculated data has a dedicated input storage area.

Abstract: A buffer room logic buffers data transferred between a host and a data storage device with a data write verification capability and stores data on a predetermined recording medium. The buffer room logic has first and second buffer counters, first and second comparators, first and second switches, and a controller. The first and second buffer counters count pulses generated at the end of a data transfer from a host interface and at the end of a data write. The first comparator compares the value of the first buffer counter with the value of a maximum buffer counter indicating a maximum size of a buffer memory, and outputs a pulse to the host interface so as to stop data transfer from the host if the comparison results in a host-no-room condition.

Abstract: The circuit provides a scaleable buffer coupled between digital domains that require data buffering because they operate at different data transfer rates and/or because one or more of the digital domains uses data bursting. The scaleable buffer circuit does not have a large fixed throughput latency as is characteristic of a first-in-first-out buffer. The buffer includes serially coupled burst cells each having a sequential element, a controlled multiplexer and control logic for controlling the multiplexer and for generating output control signals. In one embodiment, the control circuit is a finite state machine. Each burst cell is capable of receiving data from an upstream burst cell or from the input data bus. Therefore, the buffer can be filled starting from its most downstream and vacant burst cell rather than always starting from the most upstream cell (as in a typical FIFO). This reduces the throughput latency of the buffer in cases when it is not always full.

Abstract: In a method and apparatus that ensures data consistency between an I/O channel and a processor, system software issues an instruction which causes the issuance of a transaction when notification of a DMA completion is received. The transaction instructs the I/O channel to enforce coherency and then responds back only after coherency has been ensured. Specifically, a DMA.sub.-- SYNC transaction is broadcast to all I/O channels in the system. Responsive thereto, each I/O channel writes back to memory any modified lines in its cache that might contain DMA data for a DMA sequence that was reported by the system as completed. The I/O channels have a reporting means to indicate when this transaction is completed, so that the DMA.sub.-- SYNC transaction does not have to complete in pipeline order. Thus, the I/O channel can issue new transactions before responding to the DMA.sub.-- SYNC transaction.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: A method and arrangement for a dma transfer mode having multiple transactions is provided. The invention generates a set of transaction entries for a DMA transfer each of which contains information related to the address and command instruction of a transaction. The transaction entries are stored in an address/cmd-output-FIFO. The invention negotiates for the control of the system bus. Upon gaining control of the bus, the commands and address relate to each transaction are sequentially place on the system bus. If the transaction is a read operation, data received back from the system bus is first stored in a data-in-FIFO before being sent to the desired destination. If the transaction is a write operation, the data to be transferred is first stored in a data-out-FIFO before being timely place on the system bus for transferring to the desired destination. In either case, the number of data words transferred is monitored to determine when a transaction is complete.