Abstract: An apparatus comprises a buffer comprising a plurality of entries, a plurality of age vectors, and a control circuit coupled to the buffer. Each of the age vectors corresponds to one or more of the entries. Responsive to data being provided to the buffer to be written to at least a first entry, the control circuit is configured to generate a first age vector. The first age vector corresponds to the first entry, and is indicative of which of the plurality of entries contain data that is older than the data being written to the first entry. The control circuit is configured to select an entry for reading responsive to the plurality of age vectors. The selected entry has an attribute used to select the selected entry, and other entries indicated as storing older data in the age vector corresponding to the selected entry do not have the attribute.

Abstract: A system and method for distributing a portion of the processing of a received packet among a plurality of service threads. When an ISR or similar process retrieves a packet from a communication interface via a receive descriptor ring, it places the packet on one of a plurality of service queues. Each queue has an associated service thread or process that initiates upper layer protocol processing for queued packets. The ISR may select a particular service queue based on the packet's communication flow or connection. Alternatively, the ISR may use a processor identifier provided by the communication interface to select a queue (e.g., in a multi-processor computer system). Or, other information provided by the interface may be used.

Abstract: Method and system for generating an optimized full signal in a FIFO device. In one embodiment of the present invention, the optimized full signal control circuit checks the storage capacity of the FIFO memory by aggregating the number of occupied word entries and the number of occupied pipelines.

Abstract: A circuit generally comprising a plurality of read input registers, a read output register, a write input register and a plurality of write output registers is generally disclosed. The read input registers may be configured to buffer a first read signal received within a plurality of first transfers. The read output register may be configured to transmit the first read signal in a second transfer. The write input register may be configured to buffer a first write signal received in a third transfer. The write output registers may be configured to transmit the first write signal within a plurality of fourth transfers.

Abstract: The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device includes an address storage area that is configured to store system addresses corresponding to data contemporaneously stored in the data storage area. The device further includes a first circuit configured to indicate validity status of data within the data storage area for immediate access from the I/O data bus. A similar, second circuit is also included and configured to indicate validity status of data within the data storage area for immediate access from the system data bus.

Abstract: A process and software for aggressive capture of digital recording on computers, for the purpose of reducing audio latency, which includes periodic frequent polling of a recording buffer containing audio recording data and a known value, reading out data values that do not match the previously written known value, and writing over the data with the known value.

Abstract: A disk input/output (I/O) system includes a controller, a cache, a disk I/O subsystem, and a command queue. The load on the queue is monitored and when it reaches a threshold, commands are designated cache only. Cache only commands are added to the queue only if they can be completed without accessing the disk I/O subsystem. If the disk I/O subsystem would be accessed in order to complete a cache only command, the command is returned to the operating system with an error. The operating system can then add the command to an operating system or back-up queue.

Abstract: In a limit cycle autotuning method, the first limit cycle of alternately outputting a heat-side manipulated variable set point and a cool-side manipulated variable set point is generated. The first control response corresponding to the first limit cycle is detected. The second limit cycle is generated by changing one of the heat-side manipulated variable set point and the cool-side manipulated variable set point on the basis of predetermined change instruction information for instructing which one of the heat-side manipulated variable set point and the cool-side manipulated variable set point is to be changed after the first limit cycle and a predetermined manipulated variable change ratio indicating the degree of the change. The second control response corresponding to the second limit cycle is detected. The control parameter for each of the heat mode and the cool mode is calculated on the basis of the detected first and second control responses. A heat/cool control apparatus is also disclosed.

Abstract: The present invention provides method, data transfer controller and system for asynchronously transferring data. The method allows to provide a buffer device. The method further allows to define in the buffer device a plurality of buffer segments. Respective ones of the buffer segments are filled with data from at least one data source device operating in a respective clock domain. Upon any respective buffer segment being filled up, the method allows to generate an indication of availability of the contents of the respective buffer segment to at least one data destination device operating in a respective clock domain. The clock domain of the at least one source device is distinct than the clock domain of the at least one destination device.

Abstract: A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a certain amount of required buffer space for each data stream to be handled without an interruption in recording or playing back the data stream. The method further involves reallocating the amount of required buffer space for each stream including any additional stream when one or more additional streams are to be added to the total number of streams being handled. The method also involves reallocating the amount of required buffer space for each stream including those streams that remain after any of the data streams being handled are terminated.

Abstract: The method and apparatus presented are targeted to improve the performance of moving data between memory portions connected by a system bus where writes have higher performance than reads, such as the PCI bus. Due to the PCI bus design, read requests from memories connected across the PCI bus take a significantly longer time to complete than performing a write operation under the same circumstances. The present invention uses the faster write operations across the PCI bus, and queue management techniques, to take advantage of the relative speed of writes in a PCI system. The overall result is significant performance enhancement, which is especially useful in service aware networks (SAN) where operation at wired-speed is of paramount importance.

Abstract: The present invention provides a method of transferring incoming multithreaded concurrent sets of data from a sending transport system to a requesting transport system which includes retrieving the sets of data from the sending transport system. A receiving queue is queried for a number of available data storage locations, and the sets of data being transferred to the receiving queue. The method further includes queuing the sets of data in the receiving queue, where each the set of data are divided into blocks of data. Then, determining a number of the data storage locations for storing the blocks of data. Next, the blocks of data are loaded into available data storage locations, and location indexes are provided for each of the blocks of data where the location indexes associate the block of data with a corresponding the storage location.

Abstract: A device for ensuring reliable data packet throughput in a redundant system includes a splitter that creates copies of a data packet and sends each copy to a separate intermediate source for processing, parallel buffers for receiving the processed packets from the intermediate sources, and a comparator for determining whether the data packets are equivalent.

Abstract: A method and apparatus for providing a plurality of aligned instructions from an instruction stream provided by a memory unit for execution within a pipelined microprocessor is described. The microprocessor comprises a prefetch buffer, whereby the prefetch buffer stores prefetched instructions and additional information about the validity and size of the prefetch buffer. The method and apparatus use the prefetch buffer to buffer a part of an instruction stream. The actually aligned instruction stream is issued from the prefetch buffer or directly by instructions fetched from the memory, or from a combination of prefetched instructions and actually fetched instructions.

Abstract: An apparatus for gathering queue performance data includes an event conditioning logic unit that receives a queue enter signal, a queue exit signal, and a queue not empty signal from a queue. The apparatus also includes a counter that may be both incremented and decremented. The event conditioning logic unit may be programmed to increment the counter upon occurrences of a predetermined combination of the queue signals. The event conditioning logic unit may also be programmed to decrement the counter upon occurrences of an additional predetermined combination of the queue signals.

Abstract: A queuing system utilizing dual first-in, first-out (FIFO) memories is provided. The present queuing system is configured to use a first FIFO memory to receive and transfer a plurality of frames to a second FIFO memory wherein the frames include encrypted frame contents. The first FIFO memory is configured to transfer an interrupt to an associated processor in response to completion of the receipt of a valid frame. Next, the processor is configured to reinitialize the first FIFO memory for receipt of a subsequent frame. Additionally, the second FIFO memory is suitably adapted to concurrently store a plurality of frames transferred from the first FIFO memory. Finally, the present system is configured to transfer one of the stored frames out of the second FIFO memory in response to the completion of a data processing operation (e.g. initialization of a decryption algorithm).

Abstract: The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded from the FIFO. Therefore, the pushed back data value will be the first data value unloaded from the FIFO on the following read cycle. Because the data value that should not have been unloaded is not lost, and is placed at the beginning of the data value sequence, the pushback FIFO enables speculative unloads of data values from the FIFO to be performed.

Abstract: A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is delimited by only a tail pointer stored in a tail pointer list. Following dequeuing the string for processing, a pointer to the one command block of the string that was in the common queue is included in a string head pointer list. The tail pointer to the string is not changed in the tail pointer list following dequeuing of the string. This allows any new SCBs to be appended to the end of the string, while the string is being processed. This allows streaming of new SCBs to an I/O device that had previously been selected and is still connected to the host adapter.

Abstract: A data processing apparatus improves speed and efficiency of transfer of bit data, especially, multivalue data bit plane. For this purpose, a memory 50 holds four 8-bit multivalue data per 1 word, and bit plane coding processing is made by 4×4 (=16) multivalue data (processing block). In a memory area 51, the most significant bit (bit 7) of respective multivalue data (data 0 to 15 in FIG. 5) is collected in the order of multivalue data, and stored in one position (hatched portions in FIG. 5). Similarly, bit 6 is collected from the respective multivalue data and stored in one position.

Abstract: A method for duplicating recording medium includes detecting a source recording medium and a plurality of target recording mediums. A source DMAC is configured for the source recording medium and a plurality of target DMACs for the target recording mediums. The data of a source recording medium is transmitted to a source FIFO buffer through the source DMAC. The data of the source FIFO buffer is transmitted to a plurality of target FIFO buffers through a multiplexer. The data of a plurality of target FIFO buffers is transmitted to a plurality of target recording mediums through a plurality of target DMACs.

Abstract: The present invention provides an apparatus and system for buffering data in a communication network with an arranged priority which enables traffic shaping. A cell buffer unit (600) is arranged with a plurality of queues (614) configured to store PDUs on-chip and off-chip. There are associated queues both on-chip and off-chip for each priority queue. A cell buffer controller (620) forwards PDUs to a predetermined priority queue and manages the transfer of PDUs off-chip when a priority queue on-chip is fully occupied. The controller (620) also manages the transfer of PDUs from the off-chip queue when the on-chip priority queue becomes less than fully occupied.

Abstract: A method and an apparatus for sharing a request queue between two or more destinations. The method and apparatus utilizes a common data table and a common age queue. The age queue is used to select the oldest request. The corresponding request from the common data table is then extracted and sent to the appropriate destination.

Abstract: Multiple non-blocking FIFO queues are concurrently maintained using atomic compare-and-swap (CAS) operations. In accordance with the invention, each queue provides direct access to the nodes stored therein to an application or thread, so that each thread may enqueue and dequeue nodes that it may choose. The prior art merely provided access to the values stored in the node. In order to avoid anomalies, the queue is never allowed to become empty by requiring the presence of at least a dummy node in the queue. The ABA problem is solved by requiring that the next pointer of the tail node in each queue point to a “magic number” unique to the particular queue, such as the pointer to the queue head or the address of the queue head, for example. This obviates any need to maintain a separate count for each node.

Abstract: A mechanism for executing requests in a system. More specifically, a technique for processing requests to a memory system is provided. A shift register may be used to store an index associated with requests, such as read and write requests, to a memory system. Each request is stored in a respective queue depending on the source of the request and the request type (e.g. read or write). Each request includes flags which may be set to determine the processing order of the requests, such that out-of-order processing is feasible. An index corresponding to each of the requests is stored in an index shifter to facilitate the out-of-order processing of the requests. Alternatively, a shift register may be used to store each of the requests. Rather than shifting the indices to facilitate the out-of-order processing of requests, depending on the state of the corresponding request flags, the entire entry may be shifted.

Abstract: A system and method are presented for indicating active tag bits within valid entries of a dual-clock FIFO data buffer, used to transfer data between two clock domains. Data (containing tag bits) are written to the FIFO and read from the FIFO using separate clocks. Data writes are synchronous with the first clock, while reads are synchronous with the second clock. A FIFO entry is “valid” after data has been written to it, and before it is read. The system disclosed herein identifies the valid FIFO entries and generates a set of logic outputs, synchronized to the second clock (i.e., the read clock). Each output corresponds to one of the tag bit positions, and is HIGH if the corresponding tag bit is HIGH in any of the valid entries. This creates a means of detecting active tag bits in the FIFO without having to actually read each entry. Since the tag bits convey important information about the source and nature of the data, this detection system may expedite the data transfer.

Abstract: An integrated data controller that utilizes a first-in first-out (FIFO) management system that compensates for the unpredictable nature of latency associated with requesting data from memory and enables the timing of data requests to be determined based on the number of pending requests and the amount of data currently residing in the buffer. The FIFO management system includes a FIFO controller and a FIFO buffer that monitor a credit value and a trigger value to determine when to make data request bursts upon a memory unit. The trigger value is an indication of whether there is a sufficient amount of free space for it to be beneficial to make a data request burst and the credit value is a number that indicates the number of a data blocks that should be requested in the data request burst.

Abstract: Synchronized data is written to magnetic tape while reducing the number of backhitches. A controller detects a pattern of synchronizing events for received data records to be written to tape; writes each transaction of data records to the magnetic tape; accumulates the synchronized transactions in a buffer; and subsequently recursively writes the accumulated transactions of data records from the buffer to the magnetic tape in a sequence. A single backhitch may be employed to place the recursively written accumulated data records following the preceding data, maximizing performance and capacity.

Abstract: A coherency resolution technique enables efficient resolution of data coherency for packet data associated with a service queue of an intermediate network node. The packet data is enqueued on a write buffer prior to being stored on an external packet memory of a packet memory system. The packet data may be interspersed among other packets of data from different service queues, wherein the packets are of differing sizes. In response to a read request for the packet data, a coherency operation is performed by coherency resolution logic on the data in the write buffer to determine if any of its enqueued data can be used to service the request.

Abstract: A method and system for writing data which includes the steps of: receiving a write command, storing associated data in a buffer memory, determining whether or not enough free space exists in the buffer memory to store a subsequent unit of write data, and sending a “command complete” signal to the external device, if it is determined that there exists enough free space to store a subsequent unit of write data. The disk drive unit includes: a random access recording medium, a command memory, a buffer memory, and a logic circuit for determining whether or not enough free space exists in the buffer memory to store a subsequent unit of write data, with a predetermined reference value representing the amount of free space occupied by a typical unit of write data.

Abstract: The systems and methods described herein relate to the robust delivery of data. A transmitter (e.g. a server or RF broadcaster) passes parameters to a receiver and/or client enabling operation of a generalized buffer model within the receiver that regulates the proper decoding of the elementary stream. An exemplary transmitter system is configured to perform a method for specifying buffer control parameters and transmitting them within an MPEG-2 Transport Stream to a receiver. The receiver is configured to implement the generalized buffer model according to the parameters received within the stream.

Abstract: A dual-edge FIFO interface having a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full, a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full, and a register block in communication with the host FIFO and the target FIFO, wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.

Abstract: When users simultaneously play the same game with interconnected game machines, processing delays would conventionally cause inconsistencies in game content between different game machines. To solve this problem, the game machines are not synchronized with one another, but each game machine outputs operation key status data representing the state of a set of number of operation controls to the other game machines in accordance with predetermined data communication timing. A received FIFO data buffer in each game machine, sequentially stores operation key status data received from the other game machines. Only valid operation control status data is transferred to an operation data buffer for use in game processing. Inconsistencies in game content between different game machines are prevented through software-based synchronization which does not require hardware-based synchronization.

Abstract: A control unit has a main microprocessor and processor interface to a bus transceiving unit, which has at least one transmit memory, one receive memory and one bus controller. Devices are provided by which the data content of the transmit memory and/or of the receive memory is reset to a defined status after each output and/or reading-in of the data stored in either memory, and before the main microprocessor outputs and/or reads in new data.

Abstract: An asynchronous FIFO circuit has a memory; asynchronous read and write for reading a predetermined amount of data from and reading the predetermined amount of data into the memory on a first-in-first-out basis; an error write counter of counting up by 1 if the predetermined amount of data written into the memory contains an error; an error read counter of counting up by 1 if the predetermined amount of data read from the memory contains an error; and a comparator for comparing a value of the error write counter with a value of the error read counter, the comparator outputting a logic level of 0 when the value of the error write counter is coincident with the value of the error read counter, and the comparator outputting a logic level of 1 if the former value is different from the latter value.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data between a host computer bus and a packet switched network. The network interface device includes a memory controller that determines whether a complete frame is stored in the random access memory and also determines an amount of data available to be read from the oldest received frame. A host CPU is able to access this information and determine whether to read the data or read the data at a later time.

Abstract: Provided is a method, system, and program for maintaining status information on data transmitted to an output device. Data is transmitted to an Input/Output (I/O) device. The I/O device stores the transmitted data in a computer readable medium memory. A determination is made as to whether a fixed amount of data exceeding a threshold was transmitted. An indication is made that transmitted data equivalent to the fixed amount was successfully outputted from the computer readable medium after determining that the fixed amount of data exceeding the threshold was transmitted.

Abstract: In order to enable interfacing of a microprocessor (1) with a peripheral (3) consisting of a device operating according to high-speed communication specifications (for example, IEEE 1394), it is envisaged that the interface (4) should contain a dedicated memory (40) designed to smooth the delays in communication between the main memory (2) and the peripheral (3). The memory (40) has a trigger (10) that is programmable via software to start a communication when a fraction of the memory (40) or the entire memory (40) is full. When a multiple packet starts to be transferred, a signal is generated to alert the microprocessor (1) of the fact that a transfer is almost completed.

Abstract: The present invention relates to a queuing system, implemented in the memory of a computer by the execution of a program element. The queuing system includes a queue with a plurality of memory slots, a write pointer and a read pointer. The write pointer permits to enqueue data elements in successive memory slots of the queue. The read pointer permits to dequeue data elements from the queue memory slots for processing, where these data elements are potentially non-dequeuable. Upon identifying a non-dequeuable data element in a particular memory slot of the queue, the read pointer is capable to skip over the particular memory slot and move on to a successive memory slot.

Abstract: The present invention is primarily directed to rail car communication system and in particular communication system used to transfer data and voice communications from one car to another. The present invention has particular applicability for use in subway cars. A communication system using an E1 protocol is provided with an interface device which translates data received from a hardware device having, inter alia, a microprocessor and a universal asynchronous receiver transmitter (UART) used for serial communications such as COM 1-4. The asynchronous UART data is interfaced with the E1 channel. UART data transfers are usually done on a byte (8 bits) by byte basis but the present invention uses E1 timing and bit by bit communications. Additionally, data is normally sent at the data rate of the E1 channel not some other unrelated speed such as those used by a UART during serial communications. Also, the data is usually sent synchronously, like the E1 channel, not asynchronously, as with a UART.

Abstract: Systems and methods for transferring data between a host device and a storage medium are provided. In one implementation, a system for transferring data between a host device and a storage medium includes a host interface that receives from a host device a command to transfer data between the host device and the storage medium, a buffer that temporarily stores data that is transferred between the host device and the storage medium, a first register that stores a value for tracking a number of data units that are transferred between the buffer and the storage medium, and a second register that stores a value for tracking a number of data units that are transferred between the host device and the buffer. A data unit is transferred between the buffer and the storage medium if the value in the first register is within a predetermined range. Similarly, a data unit is transferred between the buffer and the host device if the value in the second register is within a predetermined range.

Abstract: A system and method for scheduling packet output according to a quality of service (QoS) action specification. A system is provided with a calendar queue with a plurality of bandwidth timeslots, wherein the bandwidth timeslots are organized into groups. A look-up logic circuitry inspects a group of bandwidth timeslots substantially simultaneously and determines from the group a first unoccupied bandwidth timeslot in which a current packet can be scheduled. The look-up logic circuitry also determines a first occupied bandwidth timeslot that contains a next packet to be transmitted.

Abstract: A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors. Further presented is a method including determining whether a queue head has less than or equal to a predetermined packet size and whether a period is one of greater than and equal to a predetermined schedule window. The method includes storing contents of a current entry in a frame list in a next pointer in the queue head. Also replacing the current entry in the frame list with a pointer to a new queue head. Many queue heads are directly coupled to the frame list.

Abstract: A data storage device and method for improving the performance of data storage devices examines a command queue and performs data transfers to memory within the device before prior commands have completed. A process running in the idle loop of the controller in the storage device checks the queue for write requests and if a cache space within a dual-port cache to hold the transfer data is available, the data transfer portion of the transfer is completed, while the device is still waiting for completion of prior commands in the queue, and data transfers are completing from the cache to the physical media for the prior command.

Abstract: A device (e.g., a secondary cache device) manages descriptors which correspond to storage locations (e.g., cache blocks). The device includes memory and a control circuit coupled to the memory. The control circuit is configured to arrange the descriptors, which correspond to the storage locations, into multiple queues within the memory based on storage location access frequencies. The control circuit is further configured to determine whether an expiration timer for the particular descriptor has expired in response to a particular descriptor reaching a head of a particular queue. The control circuit is further configured to move the particular descriptor from the head of the particular queue to a different part of the multiple queues, wherein the different part is identified based on access frequency when the expiration timer for the particular descriptor has not expired, and not based on access frequency when the expiration timer for the particular descriptor has expired.

Abstract: A dynamic queuing system wherein a single memory is shared among a plurality of different queues. A single memory, termed a queue memory, is by ally shared by one or more queue. The queue memory is divided into a plurality of memory blocks that we initially empty. An empty list functions to track which memory blocks are empty and available for use in a queue. Each queue constructed utilizes one or more memory blocks. When a queue becomes full, an additional memory block is allocated to it. Conversely, as memory blocks of a queue are read, i.e. emptied, they are returned to the pool of empty memory blocks for use by other queued.

Abstract: The invention provides a method of providing commands to a command memory where a graphics processor will have commands available for execution as long as there are commands available. The command memory includes a first indicator to identify the command location most recently accessed by the graphics processor. A second indicator identifies the number of commands locations available to write commands based on the most recently accessed command location. As a result of the invention, the application processor only checks the availability of space to write commands after it has written enough commands to fill the command memory. On the graphics processor side, the command memory is never empty unless the graphics processor executes and consumes instructions faster than the instructions are written. It is also possible to associate a graphics mode with each address range. In this way, mode can be indicated without specifically sending mode information with each command.

Abstract: A method, an apparatus, and a computer program product for optimising a bus in a Processor Local Bus (PLB) system are disclosed. A master engine performs a transfer transaction of N bytes of data on the bus of the PLB system. A type of read or write data transfer to be performed by the master engine is determined to optimize operation of the bus in response to a transfer request received asynchronously from a device coupled to the bus. This involves a request type determination function. Data is asynchronously transferred using a FIFO between the device and the bus dependent upon the determined type of transfer.

Abstract: Multiple non-blocking FIFO queues are concurrently maintained using atomic compare-and-swap (CAS) operations. In accordance with the invention, each queue provides direct access to the nodes stored therein to an application or thread, so that each thread may enqueue and dequeue nodes that it may choose. The prior art merely provided access to the values stored in the node. In order to avoid anomalies, the queue is never allowed to become empty by requiring the presence of at least a dummy node in the queue. The ABA problem is solved by requiring that the next pointer of the tail node in each queue point to a “magic number” unique to the particular queue, such as the pointer to the queue head or the address of the queue head, for example. This obviates any need to maintain a separate count for each node.

Abstract: A method of validating data between a path generator and a path processor, comprising the steps of (A) transmitting validation data from said path generator to said path processor on a data path, (B) sequentially transmitting data on said data path, (C) determining if the transmitted data is valid in response to the validation data and (D) using the overhead data by the processor when the overhead data is validated by the validation data.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.