Abstract: Application protocol data units are conveyed in a universal serial bus so that a portable electronic object such as a smart card can be recognized by a terminal, such as a micro-computer, as being a peripheral. The header and the data field, when such a data field exists, of each command are encapsulated in data fields of data packets of respective downlink transactions. The data field, when such a data field exists, and the trailer of each response are encapsulated in the data packet data field of at least one uplink transaction. By means of this bus link, the data rate between the terminal and the electronic object is higher, and a plurality of portable electronic objects can be connected to the terminal.

Abstract: A system, apparatus, computer program product and method of performing functional validation testing in a system are provided. Generally, functional validation testing includes data acquisition and data validation testing. During the functional validation testing two devices may be exchanging data. The exchange of data by the two devices may be referred to as data acquisition. The data from one device and the data from the other device may be compared to each other. This may be referred to as data validation. When data is exchanged during data acquisition, it is also stored in appropriate locations in a pool of buffers in memory. During the data acquisition, checks are made to determine if the system is entering an idle cycle. If so, the data validation test is performed by using the data in the pool of buffers in memory.

Abstract: A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.

Abstract: A drive device and method of reading from or writing to a record carrier are provided, where data is input or output via an interface using a first format according to a first file system. In the drive device, the first format is mapped to a second format according to a second file system used on the record carrier. This allows using different storage technology with the same interface, such as using a hard-disc based Microdrive with a Compact Flash interface.

Abstract: A dongle module including a digital video differential signal input terminal, a keyboard control signal I/O terminal, a mouse control signal I/O terminal, a processing unit, a transforming unit, a synthesizer unit and a signal I/O terminal is provided. The digital video differential input terminal receives a digital video differential signal, which includes multiple differential data signals, a differential clock signal and multiple low-frequency signals. The processing unit processes the low-frequency signal, a keyboard control signal and a mouse control signal to obtain a digital hybrid data. The transforming unit transforms the digital hybrid data into a differential hybrid signal. The synthesizer unit receives and composes the differential clock signal and the differential hybrid signal into a differential synthesized signal. The signal I/O terminal receives and outputs the differential data signals and the differential synthesized signal.

Abstract: A serial transmission controller, a serial transmission decoder and a serial transmission method thereof are disclosed. First, a current address and an access address are compared to select one of a plurality of transmission address modes as an access address mode and then to produce corresponding address information. The transmission address modes use different bits to transmit the address information respectively. According to the access address mode, an access command is selected from a serial command set. Finally, the access command and the address information are transmitted to a serial interface serially. After the access command is encoded to different length of bits, the encoded access command is transmitted to the serial interface so as to reduce the transmission bits and improve the transmission efficiency.

Abstract: The present invention provides a storage device that enables identification data to be readily rewritten and ensures normal completion of a data writing operation in a short time period. In the storage device of the invention, an ID comparator determines whether or not identification data transmitted from a host computer coincides with identification data stored in a memory array. In the case of coincidence, the ID comparator sends an access enable signal EN to an operation code decoder. The operation code decoder analyzes a write/read command, switches over a direction of data transfer with regard to the memory array based on a result of the analysis, and requires an I/O controller to change a high impedance setting of a signal line connecting with a data terminal DT. This series of processing allows access to an address in the memory array specified by a count on an address counter.

Abstract: A data transmission interface system includes a first electronic component having a first pin, a second electronic component having a second pin electronically connected with the first pin via a wire. The first electronic component includes an encoding module for converting a command into a pulse code. The second electronic component includes a decoding module for converting the pulse code into the command. The first pin is capable of switching between a first state and a second state. The second pin is in the same state as the first pin. Switch of the first pin from the first state to the second state triggers a beginning of data transmission between the first electronic component and the second electronic component. A related method is also provided.

Abstract: A first virtual machine (VM) in a processing system may emulate a first server blade, and a second VM in the processing system may emulate a second server blade. The emulated server blades may be referred to as virtual server blades. A virtual machine monitor (VMM) in the processing system may provide a communication channel to at least one of the virtual server blades. Other embodiments are described and claimed.

Abstract: Methods and structure for enabling transparent coordination between multiple host systems sharing access to a common SATA storage device to improve bandwidth utilization therebetween in a manner transparent to each of the multiple host systems. The SAS protocol may be utilized by each of the host systems coupled to an SAS/SATA Converter. The storage device coupled to an output path of the SAS/SATA Converter is selectively coupled to one of the multiple host systems each coupled to an input signal path of the SAS/SATA Converter to the shared SATA storage device. Protocol conversion within the SAS/SATA Converter may convert between host SAS protocol exchanges and SATA protocol exchanges of the storage device. Other features within the SAS/SATA Converter may provide queuing or buffering of SAS protocol exchanges from a host system presently non-selected for coupling to the shared SATA storage device.

Abstract: Methods and associated structure to assure correct order in delivery of SATA frames over a SAS wide port. In one aspect hereof, new connection requests from a SATA device are rejected until prior frames residing in receive buffers of the SAS/SATA controller are properly processed. In another aspect, when a device is already connected to the controller, the SAS/SATA controller may prevent return of a receiver ready primitive in response to a transmitter ready primitive until previously received frames are removed from the receive buffers.

Abstract: A bus inversion apparatus includes exclusive-OR gates and an inversion detector. The exclusive-OR gates are coupled to an instant data bus and a last data bus. The data buses have a corresponding plurality of bits, where the exclusive-OR gates perform a bitwise comparison of the data buses, and provide an exclusive-OR bus. The states of the exclusive-OR bus indicate whether corresponding bits of the data buses are different. The inversion detector counts the number of the corresponding bits that are different, and indicates that the instant data bus should be inverted. The inversion detector has a plurality of left shift circuits, each configured to perform a logical left shift of input bits as directed by the states of shift bits, where outputs of the each of the plurality of left shift circuits indicate a number of a subgroup of the corresponding bits that are different.

Abstract: A combined digital versatile disc (DVD)/hard disk drive (HDD) system controls a HDD assembly and a DVD assembly comprises a DVD/HDD control module controls operation of the HDD assembly and the DVD assembly. Volatile memory communicates with the DVD/HDD control module and stores volatile data relating to the operation of the DVD assembly and the HDD assembly. Nonvolatile memory communicates with the DVD/HDD control module and stores nonvolatile data relating to the operation of the DVD assembly and the HDD assembly.

Abstract: A data output apparatus includes a reproducing unit for reproducing data from a recording medium, and output means which outputs the data reproduced from the recording medium. If the data output apparatus received a first command, the data output apparatus sets the output means to a state locked to one format; if the data output apparatus received a second command, the data output apparatus sets the output means to a state not locked to one format; and if the data output apparatus received a third command, the data output apparatus sets the format of the output means to a format designated by the third command, irrespective of whether the output means is in the state locked to one format.

Abstract: A keyboard-video-mouse (KVM) system is disclosed. The KVM system comprises a module, a KVM switch and a signal cable. The module transmits a single-ended video signal from a computer, converts a universal asynchronous receiver/transmitter (UART) signal to an input/output (IO) signal, and transmits the IO signal to the computer. The KVM switch receives the single-ended video signal from the module and outputs the UART signal to the module. The signal cable transmits the single-ended video signal from the module to the KVM switch and transmits the UART signal from the KVM switch to the first module.

Abstract: The storage device system comprises: a plurality of signal transmission paths connected respectively to a plurality of installed storage devices; a plurality of system side communications sections for transmitting and receiving signals respectively to and from the plurality of storage devices, via the plurality of signal transmission paths; and one or a plurality of signal correcting sections for inputting a signal exchanged between the plurality of storage devices and the plurality of system side communications sections, correcting the input signal on the basis of a previously established correction parameter, and outputting the corrected signal. The correction parameter is a value set on the basis of at least one of the length of the signal transmission path between the storage device and the system side communications section, the wavelength attribute of the signal input to the signal correcting section, and the storage device attribute relating to the storage device.

Abstract: A combined digital versatile disc (DVD)/hard disk drive (HDD) system controls a HDD assembly and a DVD assembly comprises a DVD/HDD control module controls operation of the HDD assembly and the DVD assembly. Volatile memory communicates with the DVD/HDD control module and stores volatile data relating to the operation of the DVD assembly and the HDD assembly. Nonvolatile memory communicates with the DVD/HDD control module and stores nonvolatile data relating to the operation of the DVD assembly and the HDD assembly.

Abstract: A combined digital versatile disc (DVD)/hard disk drive (HDD) system controls a HDD assembly and a DVD assembly comprises a DVD/HDD control module controls operation of the HDD assembly and the DVD assembly. Volatile memory communicates with the DVD/HDD control module and stores volatile data relating to the operation of the DVD assembly and the HDD assembly. Nonvolatile memory communicates with the DVD/HDD control module and stores nonvolatile data relating to the operation of the DVD assembly and the HDD assembly.

Abstract: A method for communicating video data between a first host and a second host. The method may comprise encoding a video signal producing an encoded video signal at the first host. The method may also comprise transmitting, by the first host, the encoded video signal to the second host. The encoding and transmitting may both be performed by a first single multimedia thread of execution associated with an operating system at the first host. Other embodiments are also disclosed.

Abstract: Provided is conduit configured such that a hypervisor does not need to include logic for communicating directly with an I/O storage device. A virtual Asynchronous Service Interface (VASI) is the interface between a Command/Response Queue (CRQ), which receives CRQ commands from the hypervisor, and a Common Data-Link Interface (CDLI) of a Forwarder. The Forwarder receives I/O commands in a format associated with the CDLI and converts the commands into a generic I/O format understood by a Virtual Block Storage Device (VBSD). The reformatted command is transmitted to the VBSD, which issues commands to the native I/O stack. The hypervisor sends a read or write (R/W) request Lo the VASI, which passes the request to the Forwarder. The Forwarder converts the request and transmits the converted request to the VBSD. The VBSD transmits the request to the block storage device and returns the response to the Forwarder. The Forwarder replies to the request from the VASI with the response from the ABSD.

Abstract: In a multimodal input method, input information input from at least two input sources is received, control of the recognition of input from a second input source is performed based on the number of inputs from a first input source, and a recognition result is output.

Abstract: A computing unit includes main memory, a processing module, a baseband processing module, a transmission section, and a control module. The control module includes inputs, outputs, and memory interfaces. The main memory is coupled to one of the memory interfaces. The processing module is coupled to one of the inputs and to one of the outputs. The baseband processing module is coupled to another one of the inputs and to another one of the outputs. The control module is operably coupled to receive a request via a input of the plurality of inputs and to interpret the request. The control module determines an address from the memory access request when the request is a memory access request. The control module then determines a memory interface based on the address and transmits a representation of the memory access request to the memory interface.

Abstract: A source unit is configured to receive its main power supply from pin 14 of a DVI-compliant cable connector. A display device is operable to connect its power supply to pin 14 of a DVI-compliant cable connector to accommodate the main power requirements of a source unit.

Abstract: An image data serial signal output from the parallel-serial converting circuit 21 is converted into a differential amplitude signal by the LVDS transmitter 22 in such a manner that the amplitude of the differential voltage of the image data parallel signal varies depending on the value of the synchronization code serial signal. Accordingly, the signal values of the synchronization code serial signal and the image data serial signal are simultaneously transmitted. On the reception side, the differential amplitude signal in which the amplitude of the differential voltage of the image data serial signal varies depending on the value of the synchronization code serial signal is received by the LVDS receiver 31. The signal values of the synchronization code serial signal and the image data serial signal are separated and output based on a predetermined comparison processing.

Abstract: An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.

Abstract: An input/output data rate synchronization system includes a first data buffer that receives input data at a first rate, that temporarily stores the input data, and that outputs the input data at a second rate. A data processing module receives the input data from the first data buffer and outputs processed data at a third rate. A second data buffer receives the processed data from the data processing module at the third rate, temporarily stores the processed data, and outputs the processed data at a fourth rate. The data processing module temporarily stops receiving the input data and generating the processed data when the second data buffer exceeds a first predetermined capacity. The data processing module increases the second rate when the first data buffer exceeds a second predetermined capacity and decreases the second rate when a difference between the second and first rates is greater than a predetermined rate.

Abstract: Disclosed is a method and apparatus for inputting characters as many as possible with a limited number of keys.

Abstract: Data objects are sent using a data carousel and forward error correction. This involves segregating a file into groups, wherein each group represents k data blocks. From the k data blocks of each group, n erasure-encoded blocks are calculated, where n>k. The n erasure-encoded blocks are sent in a round-robin fashion using IP multicast technology: the first erasure-encoded block for each group, then the second block of each group, and so on. At a receiver, the blocks are stored on disk as they are received. However, they are segregated by group as they are stored. When reception is complete, each group is read into RAM, decoded, and written back to disk. In another embodiment, the receiver segregates allocated disk space into areas corresponding to sets of groups. Received blocks are then segregated only by set as they are written to disk. One or more RAM buffers can be used in this embodiment. When reception is complete, each set is read into RAM, decoded, and then written back to disk.

Abstract: The present invention provides a storage device that enables identification data to be readily rewritten and ensures normal completion of a data writing operation in a short time period. In the storage device of the invention, an ID comparator determines whether or not identification data transmitted from a host computer coincides with identification data stored in a memory array. In the case of coincidence, the ID comparator sends an access enable signal EN to an operation code decoder. The operation code decoder analyzes a write/read command, switches over a direction of data transfer with regard to the memory array based on a result of the analysis, and requires an I/O controller to change a high impedance setting of a signal line connecting with a data terminal DT. This series of processing allows access to an address in the memory array specified by a count on an address counter.

Abstract: In one embodiment, a digital adapter comprises at least one data input port to receive a digital signal originating from a network attached storage device coupled to the digital adapter, at least one data output port to interface with a digital rendering device communicatively coupled to the digital adapter; and digital signal converter logic to convert the digital signal originating from the network attached storage device from a first signal format to a second signal format, different from the first signal format, and transmit the digital signal in the second signal format through the at least one data output port.

Abstract: An apparatus which includes a controller and a plurality of disk drives. The controller has a communication control unit for accepting a data input/output request, a disk controller unit for controlling a disk drive, and a cache memory for temporarily storing data transferred between the communication control unit and the disk controller unit. The plurality of disk drives has different communication interfaces and connected to the disk controller unit to communicate with the disk controller unit.

Abstract: A method and related apparatuses for data transmission between a host computer and one or a plurality of USB compliant peripheral devices over a data communications network is provided which operates in the presence of transmission delays greater than that normally allowed in the USB specification. The host computer is connected to a local extender device which, in turn, is connected to one or a plurality of remote extender devices through the data communications network. The remote extender devices are, in turn, connected to a plurality of conventional USB peripheral devices. Data between the host computer and peripheral devices is stored and processed in the local and remote extender devices in order to allow the host computer and the USB peripheral devices to operate with greater than normally allowed time delays. In particular, the invention is of most utility when the round-trip transmission delay between the host computer and the USB peripheral device exceeds 1 microsecond.

Abstract: A universal cable interface and associated system and method are provided for coupling a transmission medium to a processing device. The universal cable interface can selectively operate in a first (input) mode and a second (output) mode. The universal cable interface can also handle different types of data, such as standard definition video data and high definition video data. When operating in the first mode, the universal cable interface may receive serial data over the transmission medium and convert the serial data into a parallel format for transmission to the processing device. When operating in the second mode, the universal cable interface may receive parallel data from the processing device and convert the parallel data into a serial format for transmission over the transmission medium.

Abstract: An input signal from a set of user interface devices is captured, and the input signal is converted into a packet by a console processor. The packet is transferred to a remote processor, and the remote processor generates an update command according to the packet. The update command is transferred to the console processor, and an OSD image is generated according to the update command. The OSD image is overlapped onto a video signal from the computers, and the overlapped video signal is output to the set of the user interface devices.

Abstract: Provided are a method, system, and program for transferring data between an initiator node and target node. A request is received conforming to a first data transfer protocol at the initiator node to transmit to the target node. A reference to a memory location is obtained to use to transfer the request to the target node. At least one function is called that executes in a user address space of the initiator node, wherein the initiator node includes a kernel address space and the user address space. The at least one function executing in the user address space interfaces with an adaptor to transmit the request and reference to the memory location to the target node using a second data transfer protocol.

Abstract: A computer system providing endian information and a method of data transmission thereof are disclosed. The method of data transmission in the computer system of the present invention comprises: reading endian information stored in a base address register of peripheral devices; deciding whether the endian information of the computer system is identical with endian information of the peripheral devices; byte-swapping data of the peripheral devices when the endian information of the computer system is different from the endian information of the peripheral devices, and transmitting the byte-swapped data to a system bus of the computer system; and transmitting the data of the peripheral devices to the system bus when the endian information of the computer system is identical with the endian information of the peripheral devices.

Abstract: A USB device using one USB device controller to simulate multiple virtual USB devices with a virtual USB hub is described. The USB device controller is assigned a USB address and communicates with the USB host under the control of an MCU and its firmware. The USB device also includes a CPLD (or FPGA or ASIC) and an analog switch for filtering the USB packets from the host and replacing the address in the packet by a fixed address before sending the packet to the USB device controller. The address in the original packet is stored in the CPLD and accessible by the MCU. The MCU controls the USB device controller to simulate one or more USB hubs and multiple USB devices.

Abstract: A linked list is implemented in hardware. Various registers within the linked list are writeable until a control register is written, rendering the registers read-only. A computer peripheral includes the hardware linked list to provide a list of capabilities to a querying device. The linked list can be built, modified, or disabled by low level software, and then locked so that it appears as read-only to higher level software such as an operating system or device driver.

Abstract: Aspects of the subject matter described herein relate to generating and propagating commands. In aspects, elements of a graphical user interface may include an input binding which associates a gesture with a command. When a gesture is received, the command is generated depending on which element has focus. In addition, elements of the graphic user interface may also define methods to call when commands are received. When an event or a command is received, a hierarchical data structure of elements representable on the graphical user interface may be traversed to respond to the event or command.

Abstract: Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

Abstract: A peripheral connectable to a processing device includes a housing and network interface circuitry at least partially enclosed within the housing, the network interface circuitry being utilizable by the processing device to establish a connection between the processing device and a network. The peripheral further includes peripheral circuitry disposed within the housing and adapted to perform at least a portion of at least one of an input function and an output function for the processing device in a manner unrelated to utilization of the network interface circuitry by the processing device. In an illustrative embodiment, the network interface circuitry comprises a wireless local area network (LAN) interface card, module or access point, the processing device comprises a computer, and the peripheral comprises a keyboard, monitor, speaker, docking station or other peripheral connectable to the computer.

Abstract: The present invention provides a high definition media interface (HDMI) controller having a modular design internal bus structure, and applications thereof. The controller includes a circuit interface, an address decoder coupled to the circuit interface, a plurality of sub-circuits, wherein each sub-circuit includes registers used to configure and control the sub-circuit, and a bus that couples the registers of each sub-circuit to the address decoder. After startup of the controller, the sub-circuits are configured by using the circuit interface, address decoder, and bus to write values to the registers of the sub-circuits. The sub-circuits of the controller include a video pixel sampler, an audio sampler, a frame composer, and a power controller. The video sampler can be configured to convert one of a plurality of RGB and YCbCr signals to a common format signal used by other sub-circuits of the controller.

Abstract: A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ones of a first rising edge and a first falling edge of the clock, respectively, to generate two plurality of instances of sampled data having a first width. The plurality of instances of sampled data is then sampled at a second rising edge of the clock and parallelized to generate a second plurality of instances of parallel data having a second width greater than the first width. The parallel data may then be processed to for example generate statistics to monitor link integrity, prior to being transmitted. A 10 Gbps data transmission speed may be maintained using the IEEE 802.3ae-specified media independent interface clock.

Abstract: The present invention provides a method that enables application instances to pass block mode storage requests directly to a physical I/O adapter without run-time involvement from either the local operating system or hypervisor. In one aspect of the present invention, a mechanism is provided for determining whether a user space operation is a resource management operation of a work processing operation. If the user space operation is a resource management operation, appropriate functions are performed to either query, create, modify or destroy resource allocations in the I/O adapter. If the user space operation is a work processing operation, appropriate functions are performed to create work queue entries and inform the I/O adapter of the work queue entries and to retrieve completion queue entries for work queue entries whose processing has been completed by the I/O adapter.

Abstract: An apparatus and method for regenerating S/PDIF data is disclosed. The apparatus includes a buffer for buffering sample words of the data units; a decision unit for receiving control words of the data units and outputting a selected control word according to a current control word of a current data unit and a previous control word of a previous data unit; and a transmitter for generating the bitstream of the first digital interconnect format according to the sample words of the data units and the selected control words outputted from the decision unit.

Abstract: Methods and apparatus that may be utilized in an effort to ensure bytes of data sequentially received on multiple single-byte data paths with properly aligned when presented on a multi-byte interface are provided. A sufficient number of bytes received each channel may be stored (e.g., buffered) and examined to properly match data from each single-byte path. Once matched, the data may be output in a proper order on the multi-byte interface, for example, via some type of multiplexor arrangement.

Abstract: An optical storage system for coupling to at least a plurality of peripheral devices. The optical storage system includes a data read subsystem to read out data stored in an optical storage medium, a data process subsystem to generate address information and data information according to the read out data, and an interface controller to generate output data according to the address information and the data information and to transfer the output data to one of the peripheral devices. A number of bits of the output data being transferred in parallel is configurable according to a parallel bit number. The data information and the address information are transferred via the same pins.

Abstract: In one embodiment of the invention, a method for providing a multi-mode port in a network device, includes: setting a first mode on the port, wherein the network device can perform serial communication on the port; and setting a second mode on the port, wherein the network device can perform network communication on the port. In another embodiment of the invention, an apparatus for enabling a multi-mode port in a network device, includes an adapter configured for attachment to and detachment from a connector of a port in the network device; wherein the network device can perform serial communication on the port in a first mode; and wherein the network device can perform network communication on the port in a second mode.

Abstract: Systems and methods of storing previously transmitted data and using it to reduce bandwidth usage and accelerate future communications are described. By using algorithms to identify long compression history matches, a network device may improve compression efficiently and speed. A network device may also use application specific parsing to improve the length and number of compression history matches. Further, by sharing compression histories and compression history indexes across multiple devices, devices can utilize data previously transmitted to other devices to compress network traffic. Any combination of the systems and methods may be used to efficiently find long matches to stored data, synchronize the storage of previously sent data, and share previously sent data among one or more other devices.

Abstract: Monitoring a converter (1) includes detecting whether a value of an input variable (2) for the converter (1) assumes a first prescribed input reference value (41) and checking whether an output variable (3) from the converter (1) likewise assumes a corresponding, second prescribed output reference value (61). This means that the operation of the converter is tested only at occasional instants, specifically only using individual, prescribed values. The fact that only prescribed values (41, 61) are compared with instantaneous values of the input and output variables (2, 3) means that the invention can be implemented using very simple means. The method is particularly suitable for monitoring the operation of a converter (1) in a control or protective device for an electrical switchgear assembly. In this context, when a malfunction in the converter (1) is detected, all protective functions which are dependent on the converter (1) are preferably turned off.