Abstract: A computer-based switch enables automated testing of the fail-over and load-balancing operations of a cluster of network servers. The computer-based switch includes a control component, a switching component, and a plurality of network adapters each for forming a connection with a network server. The switching component directs network communication data received from clients on an external network to the network servers through the network adapters. The network adapters are selectively disabled and re-enabled by the control component to create connection failure and recovery conditions. The switching component is also programmable to operate on the network communication data passing therethrough to create other test conditions such as communication delay, data loss, data reordering, and data corruption. The switching component also allows communication flows from the individual network servers to the clients to be monitored for determining whether load balancing of the servers is properly performed.

Abstract: A content-transmitting apparatus transmits reproduction control information including order of reproduction, reproducing section, and reproduction date information of contents which transmitted in the past. In a content-receiving apparatus, when a transmission destination chooses a specific television channel using a receiving side input unit, a receiving side control unit reproduces contents according to the reproduction control information. When the transmission source controls contents including the contents which transmitted in the past to the transmission destination, the transmission destination can view and listen to the contents that the transmission source intends to reproduce, with easiness just like changing television channels.

Abstract: A method for conveying display device data over an ultra wideband wireless link that provides an information handling system with an information handling system ultra wideband communication link. The method also provides a display device with a display device ultra wideband communication link and transmits display data between the information handling system ultra wideband communication link and the display device ultra wideband communication link.

Abstract: A method according to one embodiment may include discovering at least one ATA/ATAPI target device. The method of this embodiment may also include discovering a SAS address for at the least one ATA/ATAPI target device. The method of this embodiment may also include returning the SAS address for the at least one ATA/ATAPI target device in response to a device inquiry command. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.

Abstract: A format converter includes a first input buffer for storing input data, an output buffer for storing output data, a converter connected between the first input buffer and the output buffer, and a register that the converter refers to. The register allows plural kinds of conversion patterns to be defined in conformity with a desired data format conversion. The converter generates the output data based on the input data, in accordance with the conversion pattern defined in the register.

Abstract: A method and apparatus are disclosed for implementing STP flow control in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. Connections to a SATA HDD are supported using SATA Tunnelling Protocol (STP), which allows SATA traffic to be carried over a SAS network topology. Flow control in a STP connection is applied through a set of special SATA primitives, both for forward and backward flow control. A method is described herein in which STP flow control is supported without the use of a SATA link layer state machine. This allows STP flow control to be terminated on a hop-by-hop basis without knowing the data channel direction or maintaining a SATA link state machine, and while minimizing gate count.

Abstract: The present invention is directed to a method and system for providing, transparent mixed mode, object and block data storage transport. The system implements I/O modules capable of translating between communication protocols for providing common message passing multi-channel data transport for data storage while providing apparent I/O circuit exclusivity to controllers. The system is capable of converting object based transports for block storage, thus permitting both block and object based access to the storage complex. Implementing the system of the present invention allows for a common data transport system permitting component scalability and virtualization while allowing for target and initiator mode utilization of I/O interface circuits.

Abstract: The invention concerns a method and a multimode user interface for processing multimode user inputs, which are entered into a computer unit in various input modes within one specified application environment of several different ones, and converted there into different data streams. To make specially flexible processing of multimode user input possible, without having to switch manually between different input modes, it is proposed that within the data streams different information categories should be distinguished, depending on a context in which the data streams were generated, a suitable processing sequence of the information categories within the individual data streams should be determined, and the data streams should be processed in the determined sequence, the context comprising the current and/or past application environments.

Abstract: A DVD reproducing device is capable of being connected to a certain external electronic device. The DVD reproducing device includes an external input receiving unit connected with the external electronic device to receive an external input signal from the external electronic device. A key input receiving unit receives a user selection signal for selecting whether or not the external input signal is transformed. An external signal processing unit transforms the external input signal into a certain form according to a user selection signal.

Abstract: A method and apparatus for interfacing a personal digital assistant (PDA) with a communications appliance is provided. The method comprising a communication station receiving semi-structured data from a personal digital assistant (PDA) in a format native to the PDA, and parsing the semi-structured data to identify a type of the semi-structured data. If the semi-structured data is destination data, sending a job to a destination indicated by the semi-structured data.

Abstract: Data objects are sent using a data carousel and forward error correction. This involves segregating a file into groups, wherein each group represents k data blocks. From the k data blocks of each group, n erasure-encoded blocks are calculated, where n>k. The n erasure-encoded blocks are sent in a round-robin fashion using IP multicast technology: the first erasure-encoded block for each group, then the second block of each group, and so on. At a receiver, the blocks are stored on disk as they are received. However, they are segregated by group as they are stored. When reception is complete, each group is read into RAM, decoded, and written back to disk. In another embodiment, the receiver segregates allocated disk space into areas corresponding to sets of groups. Received blocks are then segregated only by set as they are written to disk. One or more RAM buffers can be used in this embodiment. When reception is complete, each set is read into RAM, decoded, and then written back to disk.

Abstract: A device and method for electronic data conversion is provided. Data according to IEEE 1394 format and protocol is received and converted to USB format and protocol and supplied to a system configured to receive data according to USB format and protocol.

Abstract: A data input/output circuit of a semiconductor memory device has a data inversion determination function. In an input mode, the data input/output circuit inverts an input data group in response to an input inversion flag and transmits the inverted input data group to a memory cell array. In an output mode, the data input/output circuit inverts a data group, output from the memory cell array, when the output data group satisfies a predetermined inversion condition, and transmits the inverted output data group to the outside of the data input/output circuit. In this case, an output inversion flag, indicating that the output data group is to be inverted, is generated. Further, the data input/output circuit stores the input inversion flag in the memory cell array in the input mode, and compares the input inversion flag, stored in the memory cell array, with the output inversion flag in the output mode.

Abstract: A memory device removably insertable into or otherwise removably connected to a plurality of host devices includes a first memory storing multimedia data. A first circuit portion of the memory device determines the host device capabilities when the memory device is connected to a host device and a second circuit portion feeds the multimedia data to the host device in a format compatible with the determined capabilities of the host device.

Abstract: A method and system for exporting ultrasound data is provided. The method includes accessing ultrasound data stored within an ultrasound system. The ultrasound data is stored in an ultrasound system readable format. The method further includes converting the ultrasound system readable format data to a user device readable format data for export from the ultrasound system and access via a user device.

Abstract: Disclosed herewith is a semiconductor data processing device that realizes low power consumption at the standby time and at the operation time, as well as speeds up the interfacing operation. The semiconductor data processing device can connect a non-volatile storage device to a general-purpose bus of a host system. The data processing device enters the active or standby state in response to the state of the general-purpose bus. In the standby state, the data processing device stops the internal clock signal and applies a substrate bias voltage to each object so as to suppress the potential sub-threshold leak current therefrom. This bias voltage is also applied to the central processing unit and the rewritable non-volatile memory for storing a control program to be executed by the central processing unit. The central processing unit processes data in units of n bits or below when the interface controller and the data transfer controller input/output parallel data in units of 2n bits.

Abstract: A method of reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method comprises the steps of identifying the optimal number of data elements, that can be accessed as a single full-word transfer, setting data packing criteria and analysing the data pattern and determining the impact of offset direction on data packing. If the packing criteria are met, the data is compacted and fetched in four bytes or two half-words in one transaction by performing a full-word transfer instead of a partial transfer. If the packing criteria are not met, a single byte or a single half word is fetched. This invention provides a system for reducing data transfer overheads. The system comprises of an external address generation unit for generating external memory addresses and corresponding byte enables and a read local address generation unit for generating internal memory addresses and corresponding byte enables.

Abstract: A system for connecting a console device to computers comprising a graphic user interface menu apparatus for controlling the computers. The system comprises a user-side circuit, a central crosspoint switch, a plurality of computer-side circuits, a menu generating unit and a first switching device. The user-side circuit coupled to the console device receives electronic signals produced by the keyboard and cursor control device and creates a data packet. The central crosspoint switch is coupled to the user-side circuits, receives the data packets and routes the data packets. The computer-side circuits coupled to the central crosspoint switch and the computers receive the data packets from the central crosspoint switch for supplying the data packets to the computers. The menu generating unit generates a menu to be displayed. The first switching device alternately outputs a video signal of the menu data and a video signal from the computers to the video monitor according to a vertical synchronization signal.

Abstract: An architecture is described, wherein an operation unit, such as an arithmetic unit, is used for performing a variety of repetitive tasks. The present invention includes embodiments and related methods for power and computationally efficiency in performing repetitive tasks. The system includes an operation unit and a configuration control unit that is in communication with a processor. The processor sends the configuration information to the configuration unit and the configuration unit provides configuration information to the operation unit. The method includes configuring the operation unit using the configuration unit based on the configuration information, retrieving data from a designated location upon which the operation unit operates, and producing a result that is formatted and send to a destination.

Abstract: Circuits and methods of rearranging the order of data in a memory having asymmetric input and output ports are disclosed. According to one embodiment, a method comprises steps of providing an input port of a memory having an input width and output port having an output width which is different than the input width. A plurality of data words are received at the input of the memory, wherein each data word has a width corresponding to the input width. The order of the plurality of input data words is rearranged; and an output word based upon the rearranged data words and having a width corresponding to the output width is generated. Various circuits and algorithms for implementing the methods are also disclosed.

Abstract: A multi-protocol serial interface (MPSI) apparatus can include a controller circuit that is configured to receive information about a type of MPSI utilized for data transfer and that is configured to control a format of the data transfer and input/output timing associated with the data transfer. A data generation and processing circuit is coupled to the controller circuit and is configured to extract information from a buffer memory to generate data for the data transfer according to the format based on the information and is configured to generate the data in a packet format or a bit format based on the information.

Abstract: There is provided a performance information reproducing apparatus that is capable of realizing desired synchronized reproduction of a plurality of types of data, such as music and images with ease. An external storage device stores a musical tone data file, in which musical tone information is recorded, and at least one media data file, in which at least one other type of media information is recorded, together with a management file in which reading manners of the musical tone data file and the media data files are recorded. A CPU generates, based on the musical tone data file and the management file, reproduction data that designates the musical tone information and the media data file to be reproduced, using designation information in a same format as the musical tone information.

Abstract: A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.

Abstract: A method and apparatus for converting different format content into one or more first common formats. This conversion method allows content that is received in multiple, different formats to be converted into one standard format for manufacturing and, optionally, into an Internet format rather quickly. This method allows the content to be available in both the production master and Internet formats nearly simultaneously. The converted Internet ready content file can be “bundled” with its associated metadata in another step and entered into a database.

Abstract: The present invention provides a detachable add-on card unit to a host system that combines mass storage capability and a processor on the same card. The card can receive data from the host, process the data, and store it in processed form, as well as the reverse process of retrieving stored data, processing it, and supplying it to the host. The non-volatile mass storage memory may contain program storage as well as card system data and user data. The end user of the card can program applications into the program storage. The combination of mass storage and a processor also adds to the capabilities of the on-card processor, allowing the card to store and execute programs. The present invention is able to provide a programmable add-on card unit to a host system. A number of applications can be stored in the card's mass storage and loaded as needed by the on-card micro-controller.

Abstract: A multimedia input system for a handheld device includes a gateway interface for connecting to the handheld device a plurality of discrete input sources generating a plurality or unique input signals and capable of communicating with the gateway interface. A converter is used for converting the each of the plurality of input signals into a signal format acceptable by the handheld device. The gateway interface may be a hub or a router. The gateway interface is adapted for selectively receiving each of the unique input signals at a single port.

Abstract: A vehicle control apparatus comprises: a computer operable to execute a control program, a first memory storing the control program, and a second memory storing the produced data. The control program includes: a platform program for inputting data from a hardware device and storing inputted data as first data in a first section of the second memory, an application program for processing for a vehicle control in accordance with an AP interface, and a coupling processing program. The coupling processing program performs mediation in the processing using the application program by converting the first data provided from the processing using the platform program to second data in accordance with the PF interface so that the second data is adapted to the AP interface. The application program executes vehicle control by using the second data. The platform program performs an operation at different predetermined intervals than the coupling program.

Abstract: When needing to make write accesses to both upper and lower sides of a counter in a timer, a CPU accesses the lower side last, and accesses the lower side first when needing to make read accesses thereto. The timer stores data of the data bus in the write buffer at the write access to the upper side, and writes the data of the data bus to the lower side and writes the data of the write buffer to the upper side at the write access to the lower side. At the read access to the lower side of the counter, the timer reads the data of the lower side for output to the data bus and reads the data of the upper side for storage in the read buffer. At the read access to the upper side, it outputs data of the read buffer to the data bus.

Abstract: The on-chip copy process is extended so that the data may be copied between two blocks that may be on different chips, different planes on the same chip, or the same plane of the same chip. More specifically, the methods described here provide a single data copying mechanism that allows data to be copied between any two locations in a memory system. An exemplary embodiment uses an EDO-type timing. According to another aspect, selected portions of the relocated data, such as chosen words in a transferred page, can be updated in the controller on the fly. In addition to transferring a data set directly from a read buffer of a source array to a write buffer of a destination array, the data set can concurrently be copied, if desired, into the controller where an error detection and correction operation can be performed on it.

Abstract: A system and method is provided for making highly accurate data propagation delay measurements in a serializer/deserializer (SERDES) integrated circuit. The invention detects a selected special character when the special character is present at the input of a transmit data path of the SERDES integrated circuit. The invention also detects the special character when the special character appears at the output of the transmit data path. The invention then counts the number of clock cycles during which the selected character was in the transmit data path. This provides the data propagation delay of the special character through the transmit data path. The invention also makes data propagation delay measurements for a receive data path of a SERDES integrated circuit.

Abstract: Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, the processing of the packet includes accessing one or more processing resources across a resource network shared by multiple packet processing engines. In one implementation, a global packet memory is one of these resources. In one implementation, these resources are accessed using direct memory access (DMA) techniques.

Abstract: A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the peripheral, and completing the access using the endianness control to affect the endianness order of the information transferred during the access. In one embodiment, the first endianness control overrides a default endianness corresponding to the access. The default endianness may be provided by a master endianness control corresponding to a master requesting the current access. A data processing system includes a first bus master, first and second peripherals, first endianness control corresponding to the first peripheral and second endianness control corresponding to the second peripheral, and control circuitry which uses the first endianness control to control endianness for an access between the first bus master and the first peripheral. In one embodiment, the data processing system may include multiple masters.

Abstract: This communication system performs serial data communication between a master apparatus and a plurality of the slave apparatus via a data transmission line. The master apparatus generates, by using a controller, a serial conversion order control signal for controlling serial conversion order for the data in the slave apparatus, and then transmits the signal to the slave apparatus. The slave apparatus sets up serial conversion order for system information data in accordance with the serial conversion order control signal, then performs serial conversion in accordance with the set-up order, and then transmits the serial conversion data to the master apparatus. The master apparatus can read the system information data in the slave apparatus in the order specified by the serial conversion order control signal.

Abstract: A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.

Abstract: Symbols are prepared for transmission by representing each bit of the symbols by a cluster of consecutive bits, identical to the bit, in a transmission bit sequence. The transmission bit sequence is transmitted at a particular bit rate. A reception bit sequence of received bits is received at the particular bit rate, and the reception bit sequence is identical to the transmission bit sequence in the absence of errors. The symbols are reconstructed from the reception bit sequence of received bits by identifying boundaries of clusters of received bits in the reception bit sequence and selecting an inner bit of each of the clusters of received bits as a bit of a reconstructed symbol. The boundary identification involves comparing neighboring received bits. The transmission of the transmission bit sequence and reception of the reception bit sequence may conform to the Peripheral Components Interconnect (PCI) Express Specifications.

Abstract: A system and method in a fibre channel environment supporting serial ATA devices. In one embodiment, the system and method includes a network having a plurality of servers and a plurality of fiber-channel devices connected to each other through the network. In another embodiment, a command arbitrator answers at least one non-media access command received from a transmitting server. Furthermore, a buffer may store a first consecutive write command for a first time interval and a second consecutive write command for a second time interval if the first time interval has not expired in one embodiment. In addition, a reset command may be generated if at least a first and a nth retry request for a failed command is unsuccessful, in one embodiment.

Abstract: A computer system including a power supply; a connector to be connected with a detachable storage medium; an auxiliary memory; a selection input part to generate a storage function processing signal to store data of the storage medium to the auxiliary memory according to an operation of a user; a an essential basic input/output system storage to store a basic input/output system command for a basic operation of the storage medium and the auxiliary memory; an OS storage to store an essential operating system and a storage function command required to process the storage function; and a controller to control the power supply to supply electric power to the auxiliary memory and to perform the BIOS command in the BIOS storage and the OS and the storage function command in the OS storage, so that the storage function is performed based on the data of the storage medium, according to the storage function processing signal from the selection input part.

Abstract: Provided are an apparatus and method for transforming an application for a multi-modal interface. The apparatus includes: a parsing means for parsing an original application to generate a parsed structure of the original application; an application transforming/creating means for transforming the parsed structure generated by the parsing means; a multi-modal synthesizing means for synthesizing the contents created by the application transforming/creating means with multi-modal information of the user terminal; a multi-modal detecting means for detecting multi-modal information received from the user terminal and transforming the detected information into contents that can be used by the device; and an action mapping means for mapping the contents, which are received from the multi-modal detecting means and can be used in the device, to action information contained in the original application to generate an event of the device according to the action information.

Abstract: A system-on-chip (100) includes a 16-bit DSP (102), a 16-bit data bus (202) coupled to the DSP, at least one 32-bit-only peripheral (110), a 32-bit data bus (212) coupled to the peripheral, and a bridge (108), including a write merge system (200), coupled between the 16-bit and 32-bit buses. A method of the write merge system includes pre-storing addresses of peripherals in a memory map structure (220 and 221), receiving 16-bit data and a write transaction from the DSP for modifying sixteen bits of a 32-bit data location of the peripheral; reading 32-bit contents of the data location of the peripheral; multiplexing the received 16-bit data with the read 32-bit contents; and writing a new 32-bit word, including the modified sixteen bits and an unmodified sixteen bits, to the data location of the peripheral, without any intervention from the DSP subsequent to receiving the write transaction.

Abstract: A distributed buffering system includes at least one input buffer, at least one serializing module, a at least one deserializing module, at least one output buffer, and a programmable logic device. The input buffer is operably coupled to store at least one data block of incoming data. The serializing module serializes the data block as it is retrieved from the input buffer to produce a serial stream of data. The programmable logic device receives the serial stream of data and distributes it to one or more of the at least one deserializing modules. The at least one deserializing module converts the serial stream back into the data block. The recaptured data block is then provided to the corresponding output buffer, which stores the recaptured data.

Abstract: Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

Abstract: A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a cache line size without a remainder, a valid data length is set equal to the length field. However, if the frame size divided by the cache line size results in a remainder, the length field is set to align the data with the cache line size. The data transfer is then initiated using these fields.

Abstract: A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of consecutive sequence ordered sets, from the stream of data blocks to create a first modified data stream which is coupled to a memory device. Finally, a second circuit coupled to the memory device generates a second modified data stream using a second clock signal. The second modified data stream preferably comprises the data blocks of the first modified data stream and idle data blocks inserted among the data blocks of the first modified data stream. Methods of buffering data received in a first clock domain and output in a second clock domain are also disclosed.

Abstract: Method for decreasing the existence of externally detectable revealing signals, so-called {umlaut over (R)}Ö{umlaut over (S)}, from keyboards (1), e.g. for computers, where the keyboard is fed with signals, so-called matrix signals, which are detected for detection of activity regarding the keys (2) of the keyboard, whereby said matrix signals are generated by means of signal devices. The method is especially characterized in that the matrix signals are high-frequency filtered before they are fed to the keyboard.

Abstract: An apparatus, system, and method for managing and formatting data in an autonomous data transfer operation are provided. An initialization module is configured to prepare metadata corresponding to a data source. A loader loads autonomous operation instructions corresponding to the data source into a first location and loads autonomous operation instructions corresponding to the metadata into a second location. An assembler selectively assembles, according to a set of formatting rules, autonomous operation instructions from the first location and the second location into a set of autonomous operation instructions. By assembling an ordered set of autonomous operation instructions, a third party autonomous operation may effectively insert metadata into and remove metadata from a contiguous data stream of a data source without altering the data.

Abstract: Methods and Apparatuses are provided for automatically converting a word length of sample data being transmitted over a serial link. A serial interface transmits and/or receives one or more data words comprising digital signals, a bit clock synchronizes transmission of individual bits, and a word clock is used to group the bits into sample words. A desired word length is determined based on the relationship between the bit clock and the word clock during the transmission or reception of a data word. Based on the desired word length, the sample data is either truncated or padded, and an appropriate amount of dither is added to the sample words to reduce the distortion and quantization artifacts introduced by the word length conversion.

Abstract: A circuit card assembly provides signal conditioning for signal discretes in control systems integrating a legacy, distributed processing architecture and a distributed I/O control system. Signal conditioning functions are determined, and the necessary physical circuits to perform the signal conditioning functions are incorporated into a circuit card. The Integrated Signal Conditioning Circuit Card Assembly is installed within the control system between legacy controllers and distributed I/O modules. The Integrated Signal Conditioning Circuit Card Assembly may leave any discrete signal unaltered or otherwise condition discretes with interrupt, interrupt on demand, over-ride, and monitor circuits. The centralized processor accesses and controls the conditioned discretes transmitted over a common hardware connection for use in system feedback and control.

Abstract: An information processing system operating in response to a remote control signal transmitted from a remote controller, the information processing system including a remote signal receiver to receive the remote control signal; an interrupt generator to generate a system management interrupt signal when receives the remote control signal by the remote signal receiver; and a controller to process the remote control signal received by the remote signal receiver and to control the information processing system to operate in correspondence to the remote control signal when the interrupt generator generates the system management interrupt signal.

Abstract: A file splitting apparatus for splitting a data file recorded over a plurality of recording management regions arranged in the recording region of a recording medium includes a management region recording part detecting section for detecting a management region recording part including a file splitting position out of a plurality of management region recording parts of a plurality of recording management regions of the data file recorded in the recording region at the time of being split at a predetermined file splitting position, a management region recording part copying section for copying the management region recording part including the file splitting position as detected by the management region recording part detecting section to some other recording management region of the recording region and a management information altering section for altering the management information of the data file to first management information for managing one of the split data files obtained by splitting the data file a