Cross-interrogating Patents (Class 711/124)
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Patent number: 8086801Abstract: A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation register or collection point for partial data access from a first cache line while waiting for a second cache line to be accessed. Because the accesses to separate cache lines are concatenated within the vector rename register without the need for an accumulator, an off-alignment load instruction is completely pipeline-able and flushable with no cleanup consequences.Type: GrantFiled: April 8, 2009Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: David A. Hrusecky, David S. Ray, Bruce J. Ronchetti, Shih-Hsiung S. Tung
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Publication number: 20110271057Abstract: The disclosed embodiments provide a system that filters duplicate requests from an L1 cache for a cache line. During operation, the system receives at an L2 cache a first request and a second request for the same cache line, and stores identifying information for these requests. The system then performs a cache array look-up for the first request that, in the process of creating a load fill packet for the first request, loads the cache line into a fill buffer. After sending the load fill packet for the first request to the L1 cache, the system uses the cache line data still stored in the fill buffer and stored identifying information for the second fill request to send a subsequent load fill packet for the second request to the L1 cache without performing an additional cache array look-up.Type: ApplicationFiled: May 3, 2010Publication date: November 3, 2011Applicant: ORACLE INTERNATIONAL CORPORATIONInventor: Martin R. Karlsson
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Patent number: 8051223Abstract: In an embodiment, buffer constructs may be generated to be associated with any one of multiple mutually exclusive states, including an open state and a closed state. When the buffer construct is in the closed state, the region of memory represented by the buffer construct is made accessible to one or more direct memory access (DMA) operations. Upon completion of the one or more DMA operations, the buffer construct transitions from the closed state to the open state. The region of memory represented by the buffer construct is made accessible for use with one or more cache operations when the buffer construct is in the open state, so that the one or more cache operations are not in conflict with the one or more DMA operations.Type: GrantFiled: December 9, 2008Date of Patent: November 1, 2011Assignee: Calos Fund Limited Liability CompanyInventors: Peter Mattson, David Goodwin
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Patent number: 8037253Abstract: A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to apply global ordering to the requests. A bus interface having request, snoop, and response logic is provided for each agent. A bus interface having request, snoop and response logic is provided for the global arbiter, and a bus interface is provided to couple the global arbiter to each type of fabric it is responsible for. Global ordering and arbitration logic tags incoming requests from the multiple agents and insures that snoops are responded to according to the global order, without regard to latency differences in the fabrics.Type: GrantFiled: September 10, 2009Date of Patent: October 11, 2011Assignee: MIPS Technologies, Inc.Inventors: Thomas A. Petersen, Sanjay Vishin
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Patent number: 8032709Abstract: A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject that is followed by an instruction completion, and reset on an exclusive XI acknowledgement. If the XI reject counter reaches a preset threshold value, the processor's pipeline is drained by blocking instruction issue and prefetching attempts, creating a window for an exclusive XI from another processor to be honored, after which normal instruction processing is resumed. Configuring the preset threshold value as a programmable value allows for fine-tuning of system performance.Type: GrantFiled: February 22, 2008Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: Chung-Lung Kevin Shum, Charles F. Webb
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Publication number: 20110238916Abstract: An apparatus and a method for accessing data at a server node of a data grid system with distributed cache is described. The server receives a request to access a logical tree structure of a cache nodes at a tree structure interface module of the server. The tree structure interface operates on a flat map structure of the cache nodes corresponding to the logical tree structure, transparent to the request. Each cache node is defined and operated on using a two-dimensional coordinate including a fully qualified name and a type.Type: ApplicationFiled: March 26, 2010Publication date: September 29, 2011Inventor: Manik Surtani
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Patent number: 8028131Abstract: According to one embodiment of the invention, a processor comprises a memory, a plurality of processor cores in communication with the cache memory and a scalability agent unit that operates as an interface between an on-die interconnect and both multiple processor cores and memory.Type: GrantFiled: November 29, 2006Date of Patent: September 27, 2011Assignee: Intel CorporationInventor: Krishnakanth Sistla
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Patent number: 8015362Abstract: A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.Type: GrantFiled: February 15, 2008Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventors: Gregory W. Alexander, Christian Jacobi, Barry W. Krumm, Chung-Lung Kevin Shum, Aaron Tsai
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Patent number: 8001328Abstract: A method and apparatus in which the observability of cross-invalidates requests within remote nodes is controlled at the time of a partial response generation, when a remote request initially checks/snoops the directory state of the remote node, but before such the time that the cross-invalidate request is actually sent to the processors on a given node. If all of the remote nodes in the system indicate that the cross-invalidates could be sent during an initial directory snoop, the requesting node is able to return full exclusivity to a given cache line to a requesting processor at the time when it receives all of the partial responses, instead of having to wait for the final responses from each of the remote nodes within the system.Type: GrantFiled: January 29, 2008Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Sebastian C. Burckhardt, Arthur J. O'Neill, Vesselina K. Papazova, Craig R. Walters
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Patent number: 7996614Abstract: Computer implemented method, system and computer usable program code for processing a data request in a data processing system. A read command requesting data is received from a requesting master device. It is determined whether a cache of a processor can provide the requested data. Responsive to a determination that a cache of a processor can provide the requested data, the requested data is routed to the requesting master device on an intervention data bus of the processor separate from a read data bus and a write data bus of the processor.Type: GrantFiled: January 4, 2008Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Robert Michael Dinkjian, Bernard Charles Drerup
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Patent number: 7991959Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. At least some of the information from the caches is associated with a common address. The processor also provides the information to a user of the software.Type: GrantFiled: May 15, 2006Date of Patent: August 2, 2011Assignee: Texas Instruments IncorporatedInventors: Oliver P. Sohm, Gary L. Swoboda, Brian Cruickshank
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Publication number: 20110185126Abstract: When a processor has transitioned to an operation stop state, it is possible to reduce the power consumption of a cache memory while maintaining the consistency of cache data. A multiprocessor system includes first and second processors, a shared memory, first and second cache memories, a consistency management circuit for managing consistency of data stored in the first and second cache memories, a request signal line for transmitting a request signal for a data update request from the consistency management circuit to the first and second cache memories, an information signal line for transmitting an information signal for informing completion of the data update from the first and second cache memories to the consistency management circuit, and a cache power control circuit for controlling supply of a clock signal and power to the first and second cache memories in accordance with the request signal and the information signal.Type: ApplicationFiled: January 24, 2011Publication date: July 28, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tsuneki SASAKI, Shuichi KUNIE, Tatsuya KAWASAKI
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Publication number: 20110153946Abstract: Briefly stated, technologies are generally described for accessing a data block in a cache with a domain based cache coherence protocol. A first processor in a first tile and first domain can be configured to evaluate a request to access the data block. A cache in a second tile in the first domain can be configured to send the data block to the first tile when the data block is cached in the second tile. The first processor can be configured to send the request to a third tile in another domain when the cached location is outside the first processor's domain. The third processor can be configured to determine and send the request to a data domain associated with the cached location of the data block. A fourth tile can be configured to receive the request and send the data block to the first tile.Type: ApplicationFiled: December 22, 2009Publication date: June 23, 2011Inventor: Yan Solihin
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Patent number: 7962696Abstract: Systems and methods are disclosed for updating owner predictor structures. In one embodiment, a multi-processor system includes an owner predictor control that provides an ownership update message corresponding to a block of data to at least one of a plurality of owner predictors in response to a change in an ownership state of the block of data. The update message comprises an address tag associated with the block of data and an identification associated with an owner node of the block of data.Type: GrantFiled: January 15, 2004Date of Patent: June 14, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Simon C. Steely, Jr., Gregory Edward Tierney
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Patent number: 7953932Abstract: A system and method for avoiding deadlocks when performing storage updates in a multi-processor environment. The system includes a processor having a local cache, a store queue having a temporary buffer with capability to reject exclusive cross-interrogates (XI) while an interrogated cache line is owned exclusive and is to be stored, and a mechanism for performing a method. The method includes setting the processor into a slow mode. A current instruction that includes a data store having one or more target lines is received. The current instruction is executed, with the executing including storing results associated with the data store into the temporary buffer. The store queue is prevented from rejecting an exclusive XI corresponding to the target lines of the current instruction. Each target line is acquired with a status of exclusive ownership, and the contents from the temporary buffer are written to each target line after instruction completion.Type: GrantFiled: February 13, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Chung-Lung Kevin Shum, Brian D. Barrick, Aaron Tsai, Charles F. Webb
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Publication number: 20110072214Abstract: A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.Type: ApplicationFiled: September 18, 2009Publication date: March 24, 2011Applicant: International Business Machines CorporationInventors: Jian Li, Ramakrishnan Rajamony, William E. Speight, Lixin Zhang
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Publication number: 20110060880Abstract: A multiprocessor according to an embodiment of the present invention comprises: a provisional determination unit that provisionally determines one transfer source for each transfer destination by performing predetermined prediction processing based on monitoring of transfer of cache data among cache memories. A data transfer unit activates, after a provisional determination result of the provisional determination unit is obtained, only a tag cache corresponding to the provisionally-determined one transfer source when the transfer of the cache data is performed and determines whether cache data corresponding to a refill request is cached referring to only the activated tag cache.Type: ApplicationFiled: July 29, 2010Publication date: March 10, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Soichiro Hosoda
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Patent number: 7890700Abstract: A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.Type: GrantFiled: March 19, 2008Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Ka Shan Choy, Jennifer A. Navarro, Chung-Lung Kevin Shum, Aaron Tsai
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Patent number: 7890704Abstract: A system and method for implementing an enhanced hover state with active prefetches. According to a preferred embodiment of the present invention, a snooper in a processing unit receives a system-wide update complete operation indicating a completion of a storage-modifying operation targeting a particular address, where the storage-modifying operation results in a modified first cache line in a first cache memory. The snooper determines if a second cache memory held a second cache line associated with the particular address prior to receiving the system-wide update complete operation. If so, the snooper issues a prefetch request for a copy of the modified first cache line to replace the second cache line in the second cache memory. The snooper updates the second cache memory with a copy of the modified first cache line.Type: GrantFiled: December 19, 2006Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Leo J. Clark, James S. Fields, Jr., Pak-Kin Mak, William J. Starke
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Patent number: 7853692Abstract: A server connectable to a client apparatus over a network is disclosed. The server includes: means for generating a file containing an address of a download server that can distribute a download file to the client apparatus over the network and a first parameter that temporally regulates access from the client apparatus to the download server; and means for distributing the file to the client apparatus in response to a request from the client apparatus.Type: GrantFiled: June 16, 2008Date of Patent: December 14, 2010Assignee: Sony CorporationInventor: Hirofumi Kouda
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Publication number: 20100306475Abstract: A cache memory system includes a first array of storage elements each configured to store a cache line, a second array of storage elements corresponding to the first array of storage elements each configured to store a first partial status of the cache line in the corresponding storage element of the first array, and a third array of storage elements corresponding to the first array of storage elements each configured to store a second partial status of the cache line in the corresponding storage element of the first array. The second partial status indicates whether or not the cache line has been modified. When the cache memory system modifies the cache line within a storage element of the first array, it writes only the second partial status in the corresponding storage element of the third array to indicate that the cache line has been modified but refrains from writing the first partial status in the corresponding storage element of the second array.Type: ApplicationFiled: May 27, 2009Publication date: December 2, 2010Applicant: VIA TECHNOLOGIES, INC.Inventors: Rodney E. Hooker, Colin Eddy, G. Glenn Henry
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Patent number: 7836257Abstract: A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.Type: GrantFiled: December 19, 2007Date of Patent: November 16, 2010Assignee: International Business Machines CorpationInventors: Robert John Dorsey, Jason Alan Cox, Hien Minh Le, Richard Nicholas, Eric Francis Robinson, Thuong Quang Truong
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Patent number: 7827354Abstract: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.Type: GrantFiled: October 25, 2007Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Leo James Clark, James Stephen Fields, Jr., Guy Lynn Guthrie, Bradley David McCredie, William John Starke
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Patent number: 7797492Abstract: A method and apparatus for dedicating cache entries to certain streams for performance optimization are disclosed. The method according to the present techniques comprises partitioning a cache array into one or more special-purpose entries and one or more general-purpose entries, wherein special-purpose entries are only allocated for one or more streams having a particular stream ID.Type: GrantFiled: February 20, 2004Date of Patent: September 14, 2010Inventors: Anoop Mukker, Zohar Bogin, Tuong Trieu, Aditya Navale
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Patent number: 7769951Abstract: Apparatus and methods for storing user data for use in real-time communications (e.g., IM or VoIP) are provided. The apparatus comprises at least a first cache device (e.g., a cache server) and a second cache device for storing user data, wherein the user data stored with the first cache device is mirrored with the second cache device. The apparatus further comprising a server having logic for causing access to the user data (e.g., to respond to or process messages) from the first cache device, if accessible, and from the second cache device if the user data is not accessible form the first cache device. The apparatus may further include logic for causing user data to be restored to the first cache device from the second cache device if the first cache device loses user data (e.g., if the first cache device goes down).Type: GrantFiled: April 10, 2007Date of Patent: August 3, 2010Assignee: Yahoo! Inc.Inventors: Ming Judy Lu, Rajanikanth Vemulapalli, Alan S. Li
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Patent number: 7769959Abstract: A system may comprise a first node that includes an ordering point for data, the first node being operative to employ a write-back transaction associated with writing the data back to memory. The first node broadcasts a write-back message to at least one other node in the system in response to an acknowledgement provided by the memory indicating that the ordering point for the data has migrated from the first node to the memory.Type: GrantFiled: January 20, 2004Date of Patent: August 3, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Stephen R. Van Doren, Gregory Edward Tierney, Simon C. Steely, Jr.
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Publication number: 20100131714Abstract: Techniques for caching images are presented. A matrix of pixel values represents an image. A diagonal of the matrix is used as an array of numbers representing an index value. The index value is compared to existing index values housed in a cache. When no match is present, the index value is inserted into the cache and the corresponding image associated with the inserted index value acquired. When a match is present no action is taken on the index values of the cache.Type: ApplicationFiled: November 26, 2008Publication date: May 27, 2010Applicant: NOVELL, INC.Inventor: Karthik Chandrasekaran
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Publication number: 20100131713Abstract: Specifically, under the present invention an available on-chip memory is coupled to another logic core or memory (e.g., cache) unit using a set of cache managers. Specifically, each cache manager is coupled to the input and output of a cache memory unit. This allows the assigned memory to become an extension of the same level cache, next level cache memory, or memory buffer. This also allows the recovery of a memory block whose logic core is not operational, and is used to improve cache memory performance of the system.Type: ApplicationFiled: November 21, 2008Publication date: May 27, 2010Applicant: International Business Machines CorporationInventors: Karl J. Duvalsaint, Daeik Kim, Moon J. Kim
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Patent number: 7698506Abstract: A technique for partially offloading, from a main cache in a storage server, the storage of cache tags for data blocks in a victim cache of the storage server, is described. The technique includes storing, in the main cache, a first subset of the cache tag information for each of the data blocks, and storing, in a victim cache of the storage server, a second subset of the cache tag information for each of the data blocks. This technique avoids the need to store the second subset of the cache tag information in the main cache.Type: GrantFiled: April 26, 2007Date of Patent: April 13, 2010Assignee: Network Appliance, Inc.Inventors: Robert L. Fair, William P. McGovern, Thomas C. Holland, Jason Sylvain
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Patent number: 7669011Abstract: A processor includes a processor core coupled to an address translation storage structure. The address translation storage structure includes a plurality of entries, each corresponding to a memory page. Each entry also includes a physical address of a memory page, and a private page indication that indicates whether any other processors have an entry, in either a respective address translation storage structure or a respective cache memory, that maps to the memory page. The processor also includes a memory controller that may inhibit issuance of a probe message to other processors in response to receiving a write memory request to a given memory page. The write request includes a private page attribute that is associated with the private page indication, and indicates that no other processor has an entry, in either the respective address translation storage structure or the respective cache memory, that maps to the memory page.Type: GrantFiled: December 21, 2006Date of Patent: February 23, 2010Assignee: Advanced Micro Devices, Inc.Inventor: Patrick N. Conway
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Publication number: 20100030965Abstract: Caching where portions of data are stored in slower main memory and are transferred to faster memory between one or more processors and the main memory. The cache is such that an individual cache system must communicate to other associated cache systems, or check with such cache systems, to determine if they contain a copy of a given cached location prior to or upon modification or appropriation of data at a given cached location. The cache further includes provisions for determining when the data stored in a particular memory location may be replaced.Type: ApplicationFiled: May 5, 2009Publication date: February 4, 2010Inventors: David S. Hutton, Kathryn M. Jackson, Keith N. Langston, Pak-kin Mak, Chung-Lung K. Shum
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Publication number: 20100017567Abstract: A cache memory control circuit includes a selecting section configured to select each way or two or more ways in a cache memory in which plural ways have been divided by a predetermined division number, in a predetermined order; a detecting section configured to detect a cache hit in each way; a controlling section configured to, if the cache hit is detected, stop the selection of each way in the selecting section; and a division number changing section having a comparing section, which compares respective values of two pieces of read data from the cache memory having been propagated through two paths, one of which has a predetermined amount of delay with respect to the other one, the division number changing section which changes the predetermined division number depending on whether the two pieces of the read data match or mismatch with each other in the comparing section.Type: ApplicationFiled: June 12, 2009Publication date: January 21, 2010Applicant: Kabushiki Kaisha ToshibaInventor: Toshio FUJISAWA
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Patent number: 7644237Abstract: A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to apply global ordering to the requests. A bus interface having request, snoop, and response logic is provided for each agent. A bus interface having request, snoop and response logic is provided for the global arbiter, and a bus interface is provided to couple the global arbiter to each type of fabric it is responsible for. Global ordering and arbitration logic tags incoming requests from the multiple agents and insures that snoops are responded to according to the global order, without regard to latency differences in the fabrics.Type: GrantFiled: February 20, 2004Date of Patent: January 5, 2010Assignee: MIPS Technologies, Inc.Inventors: Thomas A. Petersen, Sanjay Vishin
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Patent number: 7613882Abstract: An example embodiment of the present invention provides processes relating to a cache coherence protocol for distributed shared memory. In one process, a DSM-management chip receives a request to modify a block of memory stored on a node that includes the chip and one or more CPUs, which request is marked for fast invalidation and comes from one of the CPUs. The DSM-management chip sends probes, also marked for fast invalidation, to DSM-management chips on other nodes where the block of memory is cached and responds to the original probe, allowing the requested modification to proceed without waiting for responses from the probes. Then the DSM-management chip delays for a pre-determined time period before incrementing the value of a serial counter which operates in connection with another serial counter to prevent data from leaving the node's CPUs over the network until responses to the probes have been received.Type: GrantFiled: January 29, 2007Date of Patent: November 3, 2009Assignee: 3 Leaf SystemsInventors: Isam Akkawi, Michael Woodacre, Bryan Chin, Krishnan Subramani, Najeeb Imran Ansari, Chetana Nagendra Keltcher, Janakiramanan Vaidyanathan
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Publication number: 20090265485Abstract: Managing data traffic among three or more bus agents configured in a topological ring can include numbering each bus agent sequentially and injecting messages from the bus agents into the ring during cycles of bus agent activity, where the messages include a binary polarity value and a queue entry value. Messages are received from the ring into two or more receive buffers of a receiving bus agent. The value of the binary polarity value is changed after succeeding N cycles of bus ring activity, where N is the number of bus agents connected to the ring. The received messages are ordered for processing by the receiving bus agent based on at least in part on the polarity value of the messages and the queue entry value of the messages.Type: ApplicationFiled: February 24, 2009Publication date: October 22, 2009Applicant: Broadcom CorporationInventor: Fong Pong
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Publication number: 20090216951Abstract: A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject that is followed by an instruction completion, and reset on an exclusive XI acknowledgement. If the XI reject counter reaches a preset threshold value, the processor's pipeline is drained by blocking instruction issue and prefetching attempts, creating a window for an exclusive XI from another processor to be honored, after which normal instruction processing is resumed. Configuring the preset threshold value as a programmable value allows for fine-tuning of system performance.Type: ApplicationFiled: February 22, 2008Publication date: August 27, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chung-Lung Kevin Shum, Charles F. Webb
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Publication number: 20090210626Abstract: The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership slate of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.Type: ApplicationFiled: February 15, 2008Publication date: August 20, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vesselina K. Papazova, Ekaterina M. Ambroladze, Michael A. Blake, Pak-kin Mak, Arthur J. O'Neill, JR., Craig R. Waters
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Publication number: 20090193192Abstract: Cache coherency latency is reduced through a method and apparatus that expedites the return of line exclusivity to a given processor in a multi-node data handling system through enhanced inter-node communications.Type: ApplicationFiled: January 29, 2008Publication date: July 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sebastian Burckhardt, Arthur J. O'Neill, Vesselina K. Papazova, Craig R. Walters
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Publication number: 20090177841Abstract: Techniques for maintaining consistent replicas of data are disclosed. By way of example, a method for managing copies of objects within caches, in a system including multiple caches, includes the following steps. Consistent copies of objects are maintained within the caches. A home cache for each object is maintained, wherein the home cache maintains information identifying other caches likely containing a copy of the object. In response to a request to update an object, the home cache for the object is contacted to identify other caches which might have copies of the object.Type: ApplicationFiled: January 9, 2008Publication date: July 9, 2009Inventors: Judah M. Diament, Arun Kwangil Iyengar, Thomas A. Mikalsen, Isabelle Marie Rouvellou
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Patent number: 7552288Abstract: In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with the data in the first level cache may be maintained inclusively with a directory portion of the second level cache. Other embodiments are described and claimed.Type: GrantFiled: August 14, 2006Date of Patent: June 23, 2009Assignee: Intel CorporationInventors: Ravishankar Iyer, Li Zhao, Srihari Makineni, Donald Newell
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Patent number: 7529799Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. A transaction tag format for a standard bus protocol is expanded to ensure unique transaction tags are maintained throughout the system. A sideband signal is used for intervention and Reruns to preserve transaction tags at the node controller in certain circumstances.Type: GrantFiled: June 5, 2002Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: Manuel Joseph Alvarez, II, Sanjay Raghunath Deshpande, Kenneth Douglas Klapproth, David Mui
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Patent number: 7523260Abstract: A method, processing node, and computer readable medium for propagating data using mirrored lock caches are disclosed. The method includes coupling a first mirrored lock cache associated with a first processing node to a bus that is communicatively coupled to at least a second mirrored lock cache associated with a second processing node in a multi-processing system. The method further includes receiving, by the first mirrored lock cache, data from a processing node. The data is then mirrored automatically so that the same data is available locally at the second mirrored lock cache for use by the second processing node.Type: GrantFiled: December 22, 2005Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Ravi K. Arimilli, Rama K. Govindaraju, Peter H. Hochschild, Bruce G. Mealey, Satya P. Sharma, Balaram Sinharoy
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Patent number: 7493621Abstract: An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.Type: GrantFiled: December 18, 2003Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Jeffrey Powers Bradford, Harold F. Kossman, Timothy John Mullins
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Publication number: 20090037658Abstract: In one embodiment, the present invention includes a method for receiving requested data from a system interconnect interface in a first scalability agent of a multi-core processor including a plurality of core-cache clusters, storing the requested data in a line of a local cache of a first core-cache cluster including a requester core, and updating a cluster field and a core field in a vector of a tag array for the line. Other embodiments are described and claimed.Type: ApplicationFiled: July 31, 2007Publication date: February 5, 2009Inventor: Krishnakanth Sistla
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Patent number: 7487321Abstract: Systems, methods, apparatus and software can be implemented to detect memory leaks with relatively high confidence. By analyzing memory blocks stored in a memory, implicit and/or explicit contingency chains can be obtained. Analysis of these contingency chains identifies potential memory leaks, and subsequent successive verification confirms whether the potential memory leaks are memory leaks.Type: GrantFiled: February 15, 2005Date of Patent: February 3, 2009Assignee: Cisco Technology, Inc.Inventors: Manikam Muthiah, Chandra Sekhar Putha, Jun Xu, Xiangrong Wang
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Publication number: 20090024797Abstract: The present invention proposes a novel cache residence prediction mechanism that predicts whether requested data of a cache miss can be found in another cache. The memory controller can use the prediction result to determine if it should immediately initiate a memory access, or initiate no memory access until a cache snoop response shows that the requested data cannot be supplied by a cache. The cache residence prediction mechanism can be implemented at the cache side, the memory side, or both. A cache-side prediction mechanism can predict that data requested by a cache miss can be found in another cache if the cache miss address matches an address tag of a cache line in the requesting cache and the cache line is in an invalid state. A memory-side prediction mechanism can make effective prediction based on observed memory and cache operations that are recorded in a prediction table.Type: ApplicationFiled: July 18, 2007Publication date: January 22, 2009Inventors: Xiaowei Shen, Jaehyuk Huh, Balaram Sinharoy
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Patent number: 7444474Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive status information from circuit logic that collects the status information from caches associated with different processor cores. The software also causes the processor to provide the information to a user of the software. The status information indicates whether one of the caches comprises an entry associated with a virtual address.Type: GrantFiled: May 15, 2006Date of Patent: October 28, 2008Assignee: Texas Instruments IncorporatedInventors: Oliver P. Sohm, Brian Cruickshank
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Publication number: 20080256299Abstract: A system and method for maintaining consistency in a system where multiple copies of an object may exist is provided for maintaining consistent copies. Consistency is maintained using a plurality of consistency policies in which at least one consistency policy results in different performance than a second consistency policy. A consistency policy is selected from the plurality consistency policies for each object to improve system performance.Type: ApplicationFiled: June 20, 2008Publication date: October 16, 2008Inventors: Arun Kwangil Iyengar, Richard P. King, Lakshmish Macheeri Ramaswamy, Daniela Rosu, Karen Witting
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Publication number: 20080256298Abstract: Apparatus and methods for storing user data for use in real-time communications (e.g., IM or VoIP) are provided. The apparatus comprises at least a first cache device (e.g., a cache server) and a second cache device for storing user data, wherein the user data stored with the first cache device is mirrored with the second cache device. The apparatus further comprising a server having logic for causing access to the user data (e.g., to respond to or process messages) from the first cache device, if accessible, and from the second cache device if the user data is not accessible form the first cache device. The apparatus may further include logic for causing user data to be restored to the first cache device from the second cache device if the first cache device loses user data (e.g., if the first cache device goes down).Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Applicant: Yahoo! Inc.Inventors: Ming J. Lu, Rajanikanth Vemulapalli, Alan S. Li
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Patent number: 7421538Abstract: A storage control apparatus controls physical disks according to the host access using a pair of controllers, while mirroring processing is decreased when data is written to a cache memory and high-speed operation is enabled. The mirror management table is created with allocating the mirror area of the cache memory of the other controller, and acquisition of a mirror page of the cache memory of the other controller is executed referring to the mirror management table without an exchange of mirror page acquisition messages between the controllers.Type: GrantFiled: November 19, 2003Date of Patent: September 2, 2008Assignee: Fujitsu LimitedInventors: Joichi Bita, Daiya Nakamura