Abstract: A non-uniform memory access (NUMA) computer system includes a node interconnect to which a remote node and a home node are coupled. The home node contains a home system memory, and the remote node includes at least one processing unit and a cache. In response to the cache deallocating an unmodified cache line that corresponds to data resident in the home system memory, a cache controller of the cache issues a deallocate operation on a local interconnect of the remote node. In one embodiment, the deallocate operation is further transmitted to the home node via the node interconnect only in response to an indication, such as a combined response, that no other cache in the remote node caches the cache line. In response to receipt of the deallocate operation, a memory controller in the home node updates a local memory directory associated with the home system memory to indicate that the remote node does not hold a copy of the cache line.

Abstract: To provide a large scale multiprocessor system capable of executing an area limited cache coherency control implementing a high speed operation while substantially reducing the amount of processor-to-processor communications there is provided a translation lookaside buffer which retains cache coherency attribute information defining a limitable cache coherent area to maintain data consistency among caches, and a processor memory interface unit includes a cache coherency control which identifies whether cache coherency is required only within a particular cluster of processors or is required for every one of the cache memories in every one of the clusters throughout the system, on the basis of the contents of the cache coherency attribute information. Further, in another version of large scale multiprocessor system, each cluster may be provided with an export directory which registers an identifier of data whose copy is cached in cache memories in other clusters.

Abstract: A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters which coordinate bus-to-bus communications in such a way as to maintain cache memory coherency with a small amount of cross-bus traffic. In addition, the system provides a multiported pool of memory cells which interconnect the multiple buses.

Abstract: According to one embodiment, a method is disclosed. The method includes receiving a first request from a first node in a multi-node computer system to invalidate a first cache line at a second node. The method also includes receiving a second request from the second node to invalidate the first cache line at the first node and detecting the concurrent requests at conflict detection circuitry.

Abstract: According to one embodiment, a method is disclosed. The method comprises receiving a read request from a first node in a multi-node computer system to read data from a memory at a second node. Subsequently, a write request from a third node is received to write data to the memory at the second node. The read request and write request is detected at conflict detection circuitry. Finally, read data from the memory at the second node is transmitted to the first node.

Abstract: A computer system with a shared-buffer memory includes a plurality of interconnected host systems. Each of the host systems includes system random access memory, with a portion of the system random access memory defined as shared-buffer memory. A system memory controller determines if the host has updated the shared-buffer memory, and if so, signals that the shared-buffer memory has been updated. This signal is accomplished by initiating a PCI Special Cycle which indicates the location and length in the shared-buffer of the update. A buffer control and interconnect device receives the signal from the system memory controller that the shared-buffer memory has been updated, reads the update from the shared-buffer memory, and exports the update. The exported update is received at the buffer control and interconnect device of each of the other host systems. The receiving buffer control and interconnect device writes the update to its shared-buffer memory.

Abstract: A multilevel cache system and method. A first data array and a second data array are coupled to a merged tag array. The merged tag array stores tags for both the first data array and second data array.

Abstract: A method and apparatus in a data processing system for caching data in an internal cache and in an external cache A set of fragments is received for caching. A location is identified to store each fragment within the plurality of fragments based on a rate of change of data in each fragment. The set of fragments is stored in the internal cache and the external cache using the location identified for each fragment within the plurality of fragments.

Abstract: Apparatus and method for Storage Resource Management (SRM)—i.e., the management of computer storage devices as resources. Methods for Storage Resource Management are described that can be easily and efficiently scaled to computer systems which could include thousands of computers while providing detailed file storage attributes. These methods include three phases: (1) an initialization phase, (2) a data collection phase, and (3) a management server communication phase.

Abstract: A method and system for high speed data access of a banked cache memory. In accordance with the method and system of the present invention, during a first cycle, in response to receipt of a request address at an access controller, the request address is speculatively transmitted to a banked cache memory, where the speculative transmission has at least one cycle of latency. Concurrently, the request address is snooped in a directory associated with the banked cache memory. Thereafter, during a second cycle the speculatively transmitted request address is distributed to each of multiple banks of memory within the banked cache memory. In addition, the banked cache memory is provided with a bank indication indicating which bank of memory among the multiple banks of memory contains the request address, in response to a bank hit from snooping the directory.

Abstract: An apparatus comprising system memory and a cache memory maintain system coherency for data stored in a subset of memory elements utilizing software coherency control, while system coherency for all remaining memory elements is maintained utilizing hardware coherency control.

Abstract: Storing content of a particular type at one or more cache servers may be accomplished according to a cache protocol selected according to the type of the content, a site (e.g., an origin server) associated with the content and/or a class of service requirement. In this scheme, the cache protocol may be selected and/or varied according to load balancing requirements and/or traffic conditions within a network. For example, the cache protocol may migrate from a first protocol (e.g., CARP) that allows only one copy of the content to be stored to a second protocol (e.g., HTCP or ICP) that allows more than one copy of the content to be stored. Further, the depth to which a request query is to be searched within a cache hierarchy may be determined according to the site, the content type and/or the class of service. Where necessary, a path for retrieving the content may be determined, at least in part, according to the content type.

Abstract: A computer system and method for enhancing memory-to-memory copy operations includes transmitting from the processor to the source system control unit a plurality of memory-to-memory copy transactions where each transaction includes a source address and a destination address. A lookup operation is performed on the destination address to determine the destination system control unit that controls access to the destination memory which contains the destination address. A number of data blocks located at the source address in the source memory are retrieved and transmitted to the destination address. The number of data blocks are stored at the destination address in the destination memory.

Abstract: A system and method for storage and retrieval of objects. The objects are stored on a permanent medium in a manner to allow for fast recovery of the objects from the medium. The objects are stored in a format that is structurally equivalent to the format of the objects on a volatile medium, such as memory of a general-purpose computer. Objects are stored according to a data relationship with other objects. The objects may be stored as a stream of objects and offset references. Offset references are converted to actual memory addresses as objects are retrieved into the volatile medium.

Abstract: A memory area for storing the data for management of a page and a memory area for storing the data of the page itself are allowed to be distributed and allocated to separate caches. An access request for a storage module is received by a cache module managing the access request, and if a requested page is stored in another cache module, a responding process for the access request is performed jointly with the other cache module.

Abstract: A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which effect the same operation in synchronism with each other.

Abstract: A multi processor computer system including a set of processors connected to a memory subsystem via a local interconnect. The memory subsystem includes a load miss block suitable for queuing a first processor load operation that misses in an L1 cache of the first processor and a store miss block suitable for queuing store type operations. The subsystem further includes an arbiter suitable for receiving queued operations from the load and store miss blocks. The arbiter is further configured for selecting one of the received operations and initiating the selected operation. The subsystem further includes means for snooping the address associated with the first processor load operation when the first processor load operation is selected and initiated by the arbiter. The subsystem further includes a snoop control block adapted to receive a snoop response from a second processor associated with the memory subsystem.

Abstract: The invention provides a method and system for operating multiple communicating caches. Between caches, unnecessary transmission of repeated information is substantially reduced. Each cache maintains information to improve the collective operation of the system of multiple communicating caches. This can include information about the likely contents of each other cache, or about the behavior of client devices or server devices coupled to other caches in the system. Pairs of communicating caches substantially compress transmitted information. This includes both reliable compression, in which the receiving cache can reliably identify the compressed information in response to the message, and unreliable compression, in which the receiving cache will sometimes be unable to identify the compressed information. A first cache refrains from unnecessarily transmitting the same information to a second cache when each already has a copy.

Abstract: An apparatus, method and computer program product for network client-server multiplexing. The apparatus is implemented within an interface unit connecting a plurality of servers to the Internet, which is connected to a plurality of clients. According to a “connection pooling” aspect of the invention, the interface unit opens and maintains connections with the servers and handles the opening and closing of connections with clients accessing the servers, thereby freeing the servers of the processing load incurred by opening and closing connections. According to a “connection distribution” aspect oft he invention, the interface unit examines the path names within requests received from clients and selects the server hosting the requested information according to the path names.

Abstract: A caching system and method are disclosed that allow for the caching of web pages that have dynamic content. The caching system and method utilize a cacheability analyzer that analyzes responses based on time, content, user identification, and macro hierarchy. The caching system only caches those responses having dynamic content that are deemed cacheable. Further, the automatic caching system can be overridden by the information author, the page creator or the system designer.

Abstract: There is provided a method for reordering and renaming memory references in a multiprocessor computer system having at least a first and a second processor. The first processor has a first private cache and a first buffer, and the second processor has a second private cache and a second buffer. The method includes the steps of, for each of a plurality of gated store requests received by the first processor to store a datum, exclusively acquiring a cache line that contains the datum by the first private cache, and storing the datum in the first buffer. Upon the first buffer receiving a load request from the first processor to load a particular datum, the particular datum is provided to the first processor from among the data stored in the first buffer based on an in-order sequence of load and store operations.

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node.

Abstract: One or more improved transmit units tightly integrated into an enhanced cluster cache with controller. Coherent memory transactions in a loosely coupled computer network are supported by sending all cache updates to all computers in the loosely coupled computer network through high speed, low latency and high bandwidth serial lines linking all computers to all other computers. The cluster cache controller may include a local cache controller and/or as a local bus controller. The local bus controller is operable to coupled the cluster cache to an I/O subsystem. A local cache memory preferably caches data and/or instructions, or locations thereof for the entire computer, making the local computer cache available to the entire computer cluster through the transmit unit. Each transfer unit is a full-duplex transceiver that includes transmitter and receiver functions. Each transfer unit can send and receive data simultaneously since operation of their transmitter and receiver functions are independent.

Abstract: A method and system are described which allow programs to become dynamically reconfigurable without programmer intervention. This means that the programs can be dynamically distributed among multiple computers within a computer network without modification to the source code of the programs running on the system. In addition, the method and system described allow an administrator of the system to specify conditions under which reconfiguration is to occur without modification to the source text of the program to be dynamically reconfigured.

Abstract: A method for providing cache coherency in a RAID system in which multiple RAID controllers provide read/write access to shared storage devices for multiple host computers. Each controller includes read, write and write mirror caches and the controllers and the shared storage devices are coupled to one another via common backend busses. Whenever a controller receives a write command from a host the controller writes the data to the shared devices, its write cache and the write mirror caches of the other controllers. Whenever a controller receives a read command from a host the controller attempts to return the requested data from its write mirror cache, write cache and read cache and the storage devices, in that order.

Abstract: A memory cache system is used in a multiprocessor environment. The first processor accesses data using a first level 1 cache, and the second processor accesses data using a second level 1 cache. A storage control circuit is positioned between the first and second level 1 caches and a level 2 cache and main memory. The level 2 cache maintains copies of data in main storage and further maintains an indication of those level 1 caches having copies of data and whether those copies have been modified. When a processor accesses data that is not resident in the connected level 1 cache, a request is delivered to the level 2 cache for this data. The level 2 cache then determines whether it can return a copy of the data to the level 1 cache or must access the data from main memory.

Abstract: A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

Abstract: A hybrid non-uniform-memory-architecture/simple-cache-only-memory-architecture (NUMA/S-COMA) memory system and method are described useful in association with a computer system having a plurality of nodes coupled to each other. The plurality of nodes include NUMA memory which are configured to store data lines. The NUMA memories include a NUMA coherence subsystem for coordinating transfer of data between the nodes. At least one S-COMA cache is provided on at least one node of the computer system. The at least one S-COMA cache is configured to employ the NUMA coherence subsystem in sending data communication to or receiving data communication from another node of the plurality of nodes of the computer system. Data stored at another node of the system is accessed using a home node real address as the network address. The home node real address is translated into a local real address at the client node using a boundary function translation table.

Abstract: Each of processors in a multiprocessor system has a circuit for sending a synchronizing signal to a storage controller (SC) connected thereto when executing a synchronization instruction such as a start, end or barrier synchronization instruction. Each of the SCs has a circuit for notifying the corresponding processor of establishment of a synchronization upon detection of completion of a check to be made by an address management table FAA and of the issuing of necessary cache cancel requests corresponding to a store instruction issued before the synchronization instruction and upon recognition of the fact that all the processors have sent their synchronizing signals and that the issuing of all the cache cancel requests have been complete.

Abstract: Bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

Abstract: A process control system includes a plurality of machine controllers for individually controlling a plurality of process chambers and a main controller for controlling the machine controllers. Each of the machine controllers has a function of transferring process data detected by its corresponding process chamber to the main controller. The main controller has a storage device for accumulating process data transferred from the machine controllers and a function of transferring the accumulated process data to a host computer when the main controller is in a predetermined control load state.

Abstract: A scalable distributed caching system on a network receives a request for a data object from a user. The caching system carries out a locator function that locates a directory cache for the object. The directory cache stores a directory list that identifies the locations of object caches that purport to store copies of the object requested by the user. The object caches on the object directory list are polled, and in response send messages to the cache that received the user request indicating if each object cache stores a copy of the requested object. The receiving cache sends a message requesting a copy of the object to the object cache that sent the message first received by the receiving cache indicating that an object cache stores the requested object. The object cache that sent the first received message then sends a copy of the object to the receiving cache, which stores a copy and then sends a copy to the user.

Abstract: On the Internet (106), rather than retrieving a frequently requested Web object from its originating server (105) in response to a request from a client terminal (101, 102), the object rather can be retrieved from a cache (103) within the Internet Access Service Provider (IASP) (104), which connects the client terminal to the Internet. What is stored in the cache may, however, not be the most recent version of the object. Distinct from providing the Web object itself, information about changes to the object is provided by the server in response to a cache request that is asynchronous to a request from a client for the object. Such information about changes to an object includes the date and time when the object was last modified, the byte size of the modified object, and information on the type of content of the object. After receiving this information about changes to an object, the cache may then request that a copy of the object be downloaded to it.

Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

Abstract: On the Internet (106), rather than retrieving a frequently requested Web object from its originating server (105) in response to a request from a client terminal (101, 102), the object rather can be retrieved from a cache (103) within the Internet Access Service Provider (IASP) (104), which connects the client terminal to the Internet. What is stored in the cache may, however, not be the most recent version of the object. Distinct from providing the Web object itself, information about changes to the object is provided by the server in response to a cache request that is asynchronous to a request from a client for the object. Such information about changes to an object includes the date and time when the object was last modified, the byte size of the modified object, and information on the type of content of the object. After receiving this information about changes to an object, the cache may then request that a copy of the object be downloaded to it.

Abstract: A method and apparatus for maintaining coherence between shared data stored within a plurality of memory devices, each memory device residing in a different node within a tightly coupled multiprocessor system. Each node includes a "local coherence unit" and an associated processor. A cache unit is associated with each memory/processor pair. Each local coherence unit maintains a table which indicates whether the most current copy of data stored within the node resides in the local memory, in the local cache, or in a non-local cache. The present invention includes a "global coherence" unit coupled to each node via the logical interconnect. The global coherence unit includes a interconnect monitoring device and a global coherence table. When data which resides within the memory of a first node is transferred to a second node, the interconnect monitoring device updates the global coherence table to indicate that the data is being shared.

Abstract: A method of storing values in a cache used by a processor of a computer system, the cache having two or more cache directories. An address tag associated with the memory block is written into a first cache directory during an initial processor cycle, the address tag is written into a second cache directory during the next or subsequent processor cycle. Another address tag associated with a different memory block may be read from the second cache directory during the initial processor cycle. Additionally, another address tag associated with yet a different memory block may be read from the first cache directory during the subsequent processor cycle.

Abstract: A cache memory system includes multiple cache levels arranged in a hierarchical fashion. A data item stored in a higher level cache level is also stored in all lower level caches. The most recent version of a data item is detected during an initial lookup of a higher level cache. The initial lookup of a higher level cache includes a comparison of address bits for the next lower level cache. Thus the most recent version of a data item is able to be detected without additional lookups to the lower level cache.

Abstract: A method of accessing values stored in a cache used by a processor of a computer system, whereby two read operations may occur simultaneously is disclosed. Memory blocks from a memory device are loaded into respective cache lines of the cache, and address tags associated with the memory blocks are written into two redundant cache directories of the cache. Thereafter, a first memory block can be read from the cache using the first cache directory, while a second memory block is simultaneously read from the cache using the second cache directory. The cache can have a single cache entry array, or two (redundant) cache entry arrays connected respectively to the two cache directories. If an error occurs when examining a particular address tag in one cache directory, then a redundant address tag can be substituted for the particular address tag by examining a corresponding line of the other cache directory.

Abstract: A cache system for multiple processors including multiple caches, one of the caches serving each respective processor, a main memory system, and a bus interconnecting the caches and the main memory, the bus allowing data to be written directly between the caches without accessing the main memory system.

Abstract: An improved method and apparatus for distributing transactions among a plurality of groups of processors in a multiprocessor computer system are disclosed. An embodiment of the invention includes the following operations. First, receiving an address request at a first group of processors. The address request is associated with a memory address corresponding to a requested memory page. Next, identifying those of the groups of processors that are interested in the address request and identifying those of the groups of processors that are uninterested in the address request. Thereafter, substantially simultaneously broadcasting the address request to the interested groups of processors and not to the uninterested groups of processors.

Abstract: A method of retrieving Web content from a plurality of Web servers for delivery to a Web client connectable to the World Wide Web via a communication link. The Web client is preferably a data processing system connectable to a television or other conventional monitor to provide low cost Internet access. The method begins by having the user define a set of one or more servers from which content is desired to be retrieved and stored in the cache. These servers are preferably identified by a "list" of favorite Web sites. A test is then made to determine whether a given download period has terminated. Typically, this download period occurs during an "off" period, such as in the middle of the night, to avoid traffic congestion at the Web server sites. If the given download period has not terminated, a determination is then made of an activity level for the communication link as content is being downloaded to the cache from the one or more servers.

Abstract: A multiprocessing computer system employing a three-hop communications protocol. When a request is sent by a requesting node to a home node, the home node sends read and/or invalidate demands to any slave nodes holding cached copies of the requested data. The demands from the home node to the slave nodes may each advantageously include a value indicative of the number of replies the requesting agent should expect to receive. The slaves reply back to the requesting node with either data or an acknowledge. Each reply may further include the number of replies the requester should expect. Upon receiving all expected replies, the requesting node may send a completion message back to the home and may treat the transaction as completed and proceed with subsequent processing.

Abstract: A method and apparatus is provided for determining and resolving cache conflicts among data arrays that are stored in the main memory of a computer system in which the main memory is coupled with a memory cache that is coupled in turn with a microprocessor. According to the method of the invention, a cache shape vector that characterizes the size and dimension of the cache is determined under computer control. A determination of at least one cache conflict among the arrays stored in the main memory is then determined, in addition to the conflict region in the cache for the conflicting arrays. A padding value is then determined for the arrays stored in the main memory, and the memory locations of the arrays are adjusted in accordance with the padding value to prevent cache conflicts when the data from the conflicting arrays is transferred from the main memory into the cache.

Abstract: A scalable distributed caching system on a network receives a request for a data object from a user. The caching system carries out a locator function that locates a directory cache for the object. The directory cache stores a directory list that identifies the locations of object caches that purport to store copies of the object requested by the user. The object caches on the object directory list are polled, and in response send messages to the cache that received the user request indicating if each object cache stores a copy of the requested object. The receiving cache sends a message requesting a copy of the object to the object cache that sent the message first received by the receiving cache indicating that an object cache stores the requested object. The object cache that sent the first received message then sends a copy of the object to the receiving cache, which stores a copy and then sends a copy to the user.

Abstract: A method and system are provided which allow heterogeneous computing systems to have direct access to the same data storage areas on a shared data storage subsystem such that the method and system are transparent to the heterogeneous computing systems. The method and system achieve the foregoing via the following steps. A data storage subsystem controller queries all computing systems having direct access to the same data storage areas of a shared data storage subsystem as to the operating systems utilized by such computing systems. In response to answers received in response to the queries, the data storage subsystem controller creates and stores meta-data which associates each computing system having direct access with whatever operating system is running on each computing system having direct access.

Abstract: A two domain digital network with each domain having its own system bus and its own bus exchange module permits Write operation addresses to be passed between domains. Each bus exchange module provides a match filter which prevents the passage from one bus to the other bus of a duplicate Write operation (OP) address which has already been transferred, thus relieving the busses of excess traffic when a duplicate Write OP address is being sent to a cache memory for an invalidation operation. A Read operation will nullify the match filter to then allow passage of each incoming Write OP invalidation address to the snoop invalidation queue, but prevent the passage of a subsequent duplicate Write OP address, so long as the read OP is ongoing.

Abstract: Bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

Abstract: An efficient streamlined cache coherent protocol for replacing data is provided in a multiprocessor distributed-memory computer system. In one implementation, the computer system includes a plurality of subsystems, each subsystem includes at least one processor and an associated cache and directory. The subsystems are coupled to a global interconnect via global interfaces. In one embodiment, when data is replaced from a requesting subsystem, an asynchronous flush operation is initiated. In this implementation, the flush operation includes a pair of decoupled local flush instruction and corresponding global flush instruction. By decoupling the local flush instructions from the global flush instructions, once the requesting processor in the requesting subsystem is done issuing the local flush instruction, the requesting processor does not have to wait for a corresponding response from home location associated with the data being replaced.

Abstract: An efficient streamlined coherent protocol for a multi-processor multi-cache computing system. Each subsystem includes at least one processor and an associated cache and directory. The subsystems are coupled to a global interconnect via global interfaces. In one embodiment, each global interface includes a request agent (RA), a directory agent (DA) and a slave agent (SA). The RA provides a subsystem with a mechanism for sending read and write request to the DA of another subsystem. The DA is responsible for accessing and updating its home directory. The SA is responsible for responding to requests from the DA of another subsystem. Each subsystem also includes a blocker coupled to a DA and associated with a home directory. All requests for a cache line are screened by the blocker associated with each home directory. Blockers are responsible for blocking new request(s) for a cache line until an outstanding request for that cache line has been serviced.