Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

Abstract: Examples herein disclose a cache controller to receive a cache signal. A physical unclonable function (PUF) circuit is coupled to the cache controller. The PUF circuit obscures the cache signal in response to the cache signal receipt.

Abstract: An operating method for a data storage device may include: reading data from a first memory region of a storage medium; storing the read data in a data buffer; and writing the data stored in the data buffer to a second memory region of the storage medium, based on a read count for the first memory region.

Abstract: Data can be stored in a persistent-memory device, rather than a hard drive, of a computing device. A copy of the data can also be stored in another persistent-memory device of a remote computing device. For example, a central processing unit (of the computing device) can perform a first write operation to cause a file to be stored in the persistent-memory device. A memory controller can perform a second write operation to cause another memory controller of the remote computing device to store a copy of the file in the other persistent-memory device of the remote computing device.

Abstract: A method of rebuild operation of a memory controller, the method includes: searching a reference page information stored in a first memory block when a power is restored after occurrence of a sudden power off; identifying a reference page of a second memory block and storing the reference page information of the reference page into the first memory block when the reference page information is determined not to be stored in the first memory block; and performing a rebuild operation to data stored in the second memory block based on the reference page information stored in the first memory block.

Abstract: A method begins by determining whether at least one encoded data slice of a corresponding set of encoded data slices associated with a primary storage unit requires rebuilding and includes one or more excess encoded data slices of the set of encoded data slices stored in a secondary storage unit. The method continues by identifying the excess encoded data slices based on scan response messages from the secondary storage units. The method continues by assigning, for each data segment associated with at least one of an encoded data slice requiring rebuilding and an excess encoded data slice, a priority level in accordance with a prioritization scheme. The method continues by facilitating, for each data segment, rebuilding of the encoded data slices requiring rebuilding and deletion of excess encoded data slices requiring deletion in accordance with the assigned priority level of the data segment.

Abstract: In one embodiment, a method comprises generating, by a network device in a network, a Bloom filter bit vector representing services provided by service provider devices in the network; and the network device executing a service discovery operation based on identifying, relative to the Bloom filter bit vector, whether an identified service in a received message is executed in the network.

Abstract: A data processing system comprising an accelerator that acts as a common shared resource for plural applications executing in respective virtual machines. The data processing system includes an interface mapping unit that facilitates the submission of tasks from applications to the accelerator. The interface mapping unit includes physical registers that act as physical register input/output interfaces for the accelerator. The interface mapping unit exposes a plurality of virtual accelerator input/output interfaces to the applications that are then dynamically mapped to the physical register input/output interfaces by the interface mapping unit to allow applications to access, and thereby submit a task to, a given physical register input/output interface.

Abstract: A mass storage device for providing persistent storage. The system includes a plurality of instances of virtual flash translation layers, each associated with a namespace and configured to provide, to one or more virtual machines executing in a host connected to the mass storage device, access to read and write operations in the persistent storage.

Abstract: A system includes reception of a value, determination of whether the value is associated with a respective value identifier in a dictionary index associating each of a plurality of values with a respective value identifier, and in response to a determination that the value is not associated with a respective value identifier in the dictionary index: reservation of a slot of a reservation array comprising a plurality of slots, writing of the value into the reserved slot, insertion of a reserved value identifier of the reserved slot and a version counter of the reserved slot into a position of the dictionary index corresponding to the value, insertion of the value into a position of a dictionary vector storing a respective value in each of a plurality of vector positions, insertion of a first value identifier corresponding to the position of the dictionary vector into the position of the dictionary index corresponding to the value, and returning of the first value identifier.

Abstract: A method for execution by a computing device of a dispersed storage network (DSN). The method begins with identifying an encoded data slice for rebuilding, wherein a data segment of a data object is dispersed storage error encoded to produce a set of encoded data slices that is stored in a set of storage units of the DSN, wherein the set of encoded data slices includes the encoded data slice, wherein in a storage unit of the set of storage units includes a memory device that stores the encoded data slice. The method continues by identifying an issue with the memory device and by identifying sets of encoded data slices. The method continues by generating an additional encoded data slice for each of the sets of encoded data slices to produce a group of encoded data slices and storing the group of encoded data slices in memory of the DSN.

Abstract: In an example, the present invention provides a memory interface device. The device has a command interface, address interface, and a control interface device coupled, respectively, to a command address bus, an address bus, and a control interface bus of a host memory controller. The device has a status signal interface configured to output a status signal coupled to the data interface bus of the host memory controller. In an example, the status signal is asserted in an absence of data asserted on the data interface bus.

Abstract: A system, and corresponding method, for retrieving image and metadata from multiple sources in response to a query received from an originator having a corresponding clearance level. The query is received through an interface and then any errors or ambiguities in the received query are determined and corrected to create a parsed query. A standardized query is created from the parsed query and has a system usable format including corresponding query processing limitations and the standardized query is stored for later processing. The standardized query comprises one or more terms not accessible to the originator. The stored standardized query is processed to collect resulting corresponding image and metadata information. The query results are presented to the originator if a corresponding clearance level of the query results is at or below the clearance level of the originator.

Abstract: Systems and methods for intelligent memory sharing and contextual retrieval across multiple devices and multiple applications are provided. The systems and methods do not just show a user what he or she has stored across his or her different devices but intelligently suggests relevant topics and/or information based on what is contained in a shared working memory compiled from the temporary memories on all of the user devices.

Abstract: Technology is disclosed for storing data in a distributed storage system using a virtual chunk service (VCS). In the VCS based storage technique, a storage node (“node”) is split into multiple VCSs and each of the VCSs can be assigned a unique ID in the distributed storage. A set of VCSs from a set of nodes form a storage group, which also can be assigned a unique ID in the distributed storage. When a data object is received for storage, a storage group is identified for the data object, the data object is encoded to generate multiple fragments and each fragment is stored in a VCS of the identified storage group. The data recovery process is made more efficient by using metadata, e.g., VCS to storage node mapping, storage group to VCS mapping, VCS to objects mapping, which eliminates resource intensive read and write operations during recovery.

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

Abstract: A first write data and a second write data destined for a first solid state storage channel and a second solid state storage channel, respectively, is received. The first write data is chopped using a chopping factor in order to obtain (1) a first piece of chopped write data destined for the first solid state storage channel and (2) a second piece of chopped write data destined for the first solid state storage channel. The second write data is chopped using the chopping factor in order to obtain (1) a third piece of chopped write data destined for the second solid state storage channel and (2) a fourth piece of chopped write data destined for the second solid state storage channel.

Abstract: Example embodiments of the present invention include a method, a system, and a computer-program product for storage automation. The method includes receiving a request for storage, determining a storage allocation for provisioning according to the request for storage and available storage resources, and provisioning storage according to the determined storage allocation.

Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal.

Abstract: System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result; comparing the count value for the at least one tracked attribute with a threshold associated with the at least one tracked attribute; assigning the metric of sticky property to a cache line corresponding to the translation look-aside buffer entry when the count value for at least one of the at least one tracked attribute exceeds the threshold. Selective caching then assigns different protection status to the cache lines with and without sticky property; and evicting a cache line in accordance with a cache eviction policy starting with the cache lines with the lowest protection status.

Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application, and accessing data storage memory through the first and second memory devices.

Abstract: Operating a shared nothing cluster system (SNCS) in order to perform a backup of a data element. The SNCS includes at least a first and a second storage node connected via a first network of the SNCS. The first and second storage nodes are configured to store a first set and a second set of blocks, respectively, in which the first and second set of blocks form a single data element. A backup server is connected to the first and second storage nodes, and the backup server includes a backup information table. The first and second storage nodes are configured to act as backup clients in a client-server configuration involving the backup server, upon receiving at the first and the second storage nodes a request to backup the data element. For each node of the first and second storage nodes, the node identifies one or more block sequences of consecutive blocks in a set of blocks of the data element stored in the node.

Abstract: A semiconductor apparatus includes a plurality of dies. Any one of the dies may be set to a first rank and another of the dies may be set to a second rank. One or more of the first and second ranks may be configured to output any one of an even-numbered byte and an odd-numbered byte through an input/output stage at a timing earlier than the other one, according to a read command.

Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

Abstract: A system includes off-memory-module ECC-supplemental memory. In a process, an ECC-capable memory controller converts non-ECC data words to ECC data words and distributes each ECC data word between a non-ECC memory module set (of one or more non-ECC memory modules) and the ECC-supplemental memory. A host computer system can include a baseboard on which are mounted an ECC-capable memory controller, off-memory-module ECC-supplemental memory, and sockets for installing non-ECC memory modules.

Abstract: A technique of rebuilding encoded data slices in a dispersed storage network when detecting a plurality of encoded data slices that require rebuilding, as may occur upon failure of a memory device storing the encoded data slices. A plurality of rebuilding resources capable for use to rebuild the plurality of data slices are determined and, based on one or more attributes associated with the determination, a rebuilding task is apportioned. The resulting rebuilding assignments are allocated to the plurality of rebuilding resources to rebuild the encoded data slices. The allocation of the rebuilding assignments permits more than one rebuilding resource and associated distributed storage units to rebuild the encoded data slices.

Abstract: A method, non-transitory computer readable medium and storage node computing device that reserves one of a plurality of data storage devices that is designated as a coordinator data storage device. A section of the storage cluster that is unowned is identified. Ownership of a subset of the data storage devices that is in the section of the storage cluster is obtained. A determination is made when the subset of the data storage devices includes the coordinator data storage device. The reservation of the coordinator data storage device is released, when the determining indicates that the subset of the data storage devices does not include the coordinator data storage device.

Abstract: One embodiment of the system described herein facilitates a virtualized heterogeneous disk that supports differentiated storage service qualities. During operation, the system mounts a plurality of partitions of a heterogeneous disk at different mount points, each mount point corresponding to a level of quality of service (QoS). The system then receives a write command and identifies a QoS level indication associated with the write command. Subsequently, the system selects a partition on the heterogeneous disk with performance parameters matching the identified QoS level and writes data to the selected partition. The heterogeneous disk is an abstraction of a plurality of virtualized storage devices. Furthermore, the heterogeneous disk has a single block address space, and the virtualized storage devices are allowed to have differentiated performance parameters, thereby facilitating differentiated QoS levels in the heterogeneous disk.

Abstract: The subject disclosure is generally directed towards load balancing between storage processors based upon dynamic redirection statistics, in which load balancing includes changing a preferred path/a mounted file system from one storage processor to another. In one example, load balancing technology compares a current delta of directed and redirected I/O counts to a previous delta. If the result turns from negative to positive, that is, redirection is becoming prevalent, a load balancing threshold may be changed based upon the current delta value. Load balancing is thus based on the latest trend of I/O redirection.

Abstract: Data can be stored in a persistent-memory device, rather than a hard drive, of a computing device. A copy of the data can also be stored in another persistent-memory device of a remote computing device. For example, a central processing unit (of the computing device) can perform a first write operation to cause a file to be stored in the persistent-memory device. A memory controller can perform a second write operation to cause another memory controller of the remote computing device to store a copy of the file in the other persistent-memory device of the remote computing device.

Abstract: A system includes global memory circuitry configured to store input tensors and output tensors. Row data paths are each connected to an output port of the memory circuitry. Column data paths are connected to an input port of the memory circuitry. Processing elements are arranged in rows and columns along the row data paths and column data paths, respectively. The processing elements include local memory circuitry configured to store multiple masks and processing circuitry. The processing circuitry is configured to receive portions of the input tensors from one of the row data paths; receive masks from the local memory circuitry; perform multiple tensor operations on a same received portion of an input tensors by applying a different retrieved mask for each tensor operation; and generate, using results of the multiple tensor operations, an output for a corresponding column data path.

Abstract: A distributed storage network (DSN) can include a DSN memory and a distributed storage (DS) managing unit in communication with the DSN memory. The DSN memory includes DS units physically located at different sites. The DS units store encoded data slices associated with a storage vault having a number of pillars and a read threshold. The number of pillars correspond to a number of encoded data slices generated from a particular segment of data, and the read threshold corresponds to subset of those encoded data slices required to reconstruct the particular segment of data. The DS managing unit assigns storage of particular encoded data slices to particular DS units based, at least in part, on a pillar associated with the encoded data slices and on the physical locations, e.g. the sites, at which the DS units are located.

Abstract: A method comprising executing an application on a JAVA virtual machine, the JAVA virtual machine executing on a computing device, the application having allocated memory, monitoring, by the JAVA virtual machine, memory consumed by the application during execution, determining, based on the consumed memory, that the allocated memory is to be adjusted; and adjusting, by the JAVA virtual machine, the allocated memory during runtime without restarting the execution of the application.

Abstract: A host sends an I/O transaction. The I/O transaction relates to a read or write operation for a first datum. A first listening service which manages I/O transactions for a first set of addresses receives the I/O transaction. The first listening service forwards the I/O transaction to a second listening service. The second listening service manages I/O transactions for a second set of addresses. The second listening service executes the I/O transaction at a selected address of the second set of addresses. The second listening service creates a data packet to respond to the I/O transaction. The header of the data packet includes the selected address. The second listening service transmits the data packet to the host. The host uses the selected address to update a database which includes addresses of data within.

Abstract: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit (GPU) and a shared virtual memory supported by a physical private memory space of at least one heterogeneous processor or a physical shared memory shared by the heterogeneous processor. The CPU (producer) may create shared multi-version data and store such shared multi-version data in the physical private memory space or the physical shared memory. The GPU (consumer) may acquire or access the shared multi-version data.

Abstract: Methods and apparatus related to sharing Serial Peripheral Interface (SPI) flash memory in a multi-node server SoC (System on Chip) platform environment are described. In one embodiment, multi-port non-volatile memory is shared by a plurality of System on Chip (SoC) devices. Each of the plurality of SoC devices comprises controller logic to control access to the multi-port non-volatile memory and/or to translate a host referenced address of a memory access request to a linear address space and a physical address space of the multi-port non-volatile memory. Other embodiments are also disclosed and claimed.

Abstract: A method for use in analyzing tenant-specific data is disclosed. First data for a first tenant and second data for a second tenant is stored in a multi-tenant data storage system. A first portion of the first data is selected. Based on the selection, the first portion of the first data is copied to a data store that is specific to the first tenant. Data analysis techniques are applied to the data store.

Abstract: Memory space is managed to release storage area occupied by pages similar to stored reference pages. The memory is examined to find two similar pages, and a transformation is obtained. The transformation enables reconstructing one page from the other. The transformation is then stored and one of the pages is discarded to release its memory space. When the discarded page is needed, the remaining page is fetched, and the transformation is applied to the page to regenerate the discarded page.

Abstract: The embodiments described herein provide a video router with integrated control layers and a method of operating the same. The video router includes line cards and fabric cards coupled to a controller communication network. The line cards and fabric cards include crosspoint switches and card controllers. Each card controller controls the operation of the corresponding crosspoint switches. Each crosspoint switch includes a plurality of input switch terminals and output switch terminals coupled to a backplane, providing signal communication paths between the line and fabric cards. The configuration of at least some of the crosspoint switches may be controlled by the controller on the same card or on other cards. The video router may include a switch configuration table to track the coupling of input and output terminals through each of the cross-point switches.

Abstract: Technologies for dynamic home tile mapping are described. an address request can be received from a processing core, the processing core being associated with a home tile table, the home tile table including respective mappings of one or more directory addresses to one or more home tiles. A buffer can be scanned to identify a presence of the address within the buffer. Based on an identification of the presence of the address within the buffer, a home tile identifier corresponding to the address can be provided from the buffer.

Abstract: Various systems and methods for performing Input/Output (I/O) quiesce and drain operations in multi-node distributed storage systems are disclosed. For example, one method involves receiving a message. The message indicates a request for a operation to be performed by a node, where the node can receive I/O requests from an application, as well as remote I/O requests from another node. The node can issue the I/O requests and the remote I/O requests to the one or more storage devices. In response to receipt of the message, the method performs a first portion of a operation on the node. The first portion of the operation includes the node not processing any additional locally generated I/O requests and processing additional remote I/O requests.

Abstract: A data processing system (2) includes memory protection circuitry (10) storing access control data for controlling accesses to data at memory addresses within a main memory (16). An access control cache (14) may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry (10) to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache (14) is storing access control data for a memory access request, then the access control data stored within the access control cache (14) is used in place of access control data retrieved form the memory protection circuitry (10).

Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.

Abstract: Communication between program components executing in different virtual machines on the same physical computer may be optimized utilizing various mechanisms. A virtual machine manager may be configured to route network communications between virtual machines on the same physical host through a memory buffer. The virtual machine manager might also be configured to provide a shared memory and/or a shared data structure for enabling data communication between program components executing in different virtual machines on the same physical computing device. Mechanisms might also be implemented in order to prevent inconsistent read and/or write operations from being performed on the shared memory and/or the shared data structure. Mechanisms might also be implemented to minimize copying of a memory buffer, shared memory, and/or shared data structure.

Abstract: Methods, systems and computer program products are provided for mixed shared/non-shared memory transport in virtual machines. A computer-implemented method may include providing a shared memory area writeable by a first virtual processor and a second virtual processor that are runnable on a host CPU, retrieving the information stored in the shared memory area by the first virtual processor when the first virtual processor stops running on the host CPU and before the second virtual processor runs on the host CPU, and storing the retrieved information from the shared memory area in a non-shared memory.

Abstract: A system and method for recognizing data access patterns in large data sets and for preloading a cache based on the recognized patterns is provided. In some embodiments, the method includes receiving a data transaction directed to an address space and recording the data transaction in a first set of counters and in a second set of counters. The first set of counters divides the address space into address ranges of a first size, whereas the second set of counters divides the address space into address ranges of a second size that is different from the first size. One of a storage device or a cache thereof is selected to service the data transaction based on the first set of counters, and data is preloaded into the cache based on the second set of counters.

Abstract: A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer.