Abstract: A method includes providing a persistent common view of a virtual shared storage system. The virtual shared storage system includes a first shared storage system and a second shared storage system, and the persistent common view includes information associated with data and instructions stored at the first shared storage system and the second shared storage system. The method includes automatically updating the persistent common view to include third information associated with other data and other instructions stored at a third shared storage system in response to adding the third shared storage system to the virtual shared storage system.

Abstract: Available capacity of a specific memory block is secured as much as possible. A termination candidate process selection unit (204) selects, for each of a plurality of memory blocks, a plurality of processes as a termination candidate process group, a termination process decision unit (206) determines whether or not the selected termination candidate process group is to be terminated with priority over a currently held termination candidate process group, a process group termination possibility determination unit (205) determines whether of not the termination candidate process group determined to be terminated can be terminated, and the termination process decision unit (206) rewrites the currently held termination candidate process group to the termination candidate process group determined to be able to be terminated, and decides the currently held termination candidate process group as a process to be terminated when selection of a termination candidate process group is ended for all the memory blocks.

Abstract: An electronic system including a system-on-chip (SoC) providing access to a shared memory via a chip-to-chip link includes a memory device, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first central processing unit (CPU) and a memory access path configured to enable access to the memory device. The second semiconductor device is configured to access the memory device via the memory access path of the first semiconductor device. The second semiconductor device is permitted to access the memory device while the memory access path is active and the first CPU is inactive, and the memory access path is configured to become active without intervention of the first CPU.

Abstract: A storage control system judges whether the data pattern of data exchanged with a higher-level device (hereafter “data”) conforms to one or a plurality of write-excluded data patterns comprised in write-excluded data pattern information prepared in advance. If a negative judgment result is obtained, the storage control subsystem stores the data in a logical device formed on a disk storage device. If, on the other hand, a positive judgment result is obtained, the storage control subsystem erases the data without storing in a logical device.

Abstract: A system is described in which a plurality of host computers are coupled to a storage system for storing and retrieving data in the storage system. The storage system includes individually addressable units of storage such as volumes or logical unit numbers. A security management system controls access to each of the individually addressable units of storage based upon the identification of the host permitted to access that unit of storage.

Abstract: A storage system adapted to be coupled to a plurality of host devices via a fiber channel. The storage system including a plurality of storage devices, at least a portion of the plurality of storage devices corresponding to a logical unit of a plurality of logical units, the logical unit having a logical unit number (LUN). The storage system also including a storage control device having a cache memory and controlling to store data, addressed to the LUN, into the portion of the plurality of storage devices. The storages system also including an input device being adapted to be used to set information, which is used to prevent an unauthorized access to the logical unit and which corresponds to a relationship between a host device of the plurality of host devices and the logical unit.

Abstract: Various technologies and techniques are disclosed for providing type stability techniques to enhance contention management. A reference counting mechanism is provided that enables transactions to safely examine states of other transactions. Contention management is facilitated using the reference counting mechanism. When a conflict is detected between two transactions, owning transaction information is obtained. A reference count of the owning transaction is incremented. The system ensures that the correct transaction was incremented. If the owning transaction is still a conflicting transaction, then a contention management decision is made to determine proper resolution. When the decision is made, the reference count on the owning transaction is decremented by the conflicting transaction. When each transaction completes, the reference counts it holds to itself is decremented. Data structures cannot be deallocated until their reference count is zero.

Abstract: Embodiments of computer processing systems and methods are provided that include a memory protection unit (MPU), and a plurality of region descriptors associated with the MPU. The region descriptors include address range and translation identifier values for a respective region of memory. Control logic determines whether a translation identifier control indicator is in a first state, and if the translation identifier control indicator is in the first state, the control logic allows a first process being executed by the processing system to access a memory region allocated to a second process being executed by the processing system.

Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

Abstract: Coordinating media requests from a plurality of sources that share a shared media resource is disclosed. One or more media requests requiring action by the shared media resource is received from one or more of the plurality of sources. Each received media request is placed in a queue of requests requiring action by the shared media resource. Media requests in the queue are serviced based at least in part on their relative importance.

Abstract: A method, system and program code for implementing distributed locks to be maintained through the use of on disk heartbeats. An instance of a node need only maintain a single heartbeat for all locks associated with the node and all of its processes. The node updates its heartbeat by accessing common storage, either virtual or physical, and updating a timestamp value in its heartbeat within a predetermined time interval, otherwise the heartbeat becomes stale. Expired heartbeats can be cleared or broken to allow redistribution of any locks associated therewith. The inventive technique may be implemented in a traditional computer environment or in a fully or partially virtualized environment and requires no use of an IP network or a separate network based lock manager.

Abstract: A method of and apparatus for arbitrating a memory access conflict to a memory array. The apparatus may include selection logic coupled with a plurality of ports and a memory array to arbitrate among a plurality of contending memory access requests and to conditionally block write data from accessing the memory array when write data arrives late in time.

Abstract: An automatic mutual exclusion computer programming system is disclosed which allows a programmer to produce concurrent programming code that is synchronized by default without the need to write any synchronization code. The programmer creates asynchronous methods which are not permitted make changes to shared memory that they cannot reverse, and can execute concurrently with other asynchronous methods. Changes to shared memory are committed if no other thread has accessed shared memory while the asynchronous method executed. Changes are reversed and the asynchronous method is re-executed if another thread has made changes to shared memory. The resulting program executes in a serialized order. A blocking system method is disclosed which causes the asynchronous method to re-execute until the blocking method's predicate results in an appropriate value. A yield system call is disclosed which divides asynchronous methods into atomic fragments.

Abstract: Managing memory access in a non-uniform memory access (NUMA) multiprocessor architecture including two computation units and at least two separate memories is disclosed. Each memory, including at least one logic memory entity, is locally associated with a computation unit. After receiving a control for access to a logic memory entity, the status of an indicator of the status of the logic memory entity (first entity) to which the received command applies is determined. If the indicator is in a first state, the received control is executed. If, on the contrary, the indicator is in a second state, data stored in the first entity is migrated into a second logic memory entity of a memory separate from the memory including the first entity, and the status of the second entity is placed into the first state.

Abstract: A method of acquiring a lock by a node, on a shared resource in a system of a plurality of interconnected nodes, is disclosed. Each node that competes for a lock on the shared resource maintains a list of locks currently owned by the node. A lock metadata is maintained on a shared storage that is accessible to all nodes that may compete for locks on shared resources. A heartbeat region is maintained on a shared resource corresponding to each node so nodes can register their liveness. A lock state is maintained in the lock metadata in the shared storage. A lock state may indicate lock held exclusively, lock free or lock in managed mode. If the lock is held in the managed mode, the ownership of the lock can be transferred to another node without a use of a mutual exclusion primitive such as the SCSI reservation.

Abstract: A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a reservation for a predetermined memory address. The first thread then executes a reservation-based instruction that can change the execution state of the first thread. Reservation circuitry of the processing device that was executing the first thread monitors the reservation. In the event that the reservation cleared, such as by the second thread modifying data at the predetermined memory address, the first thread is reinstated to its prior execution state. By using a hardware reservation mechanism to monitor for clearing of a set reservation, repeated memory accesses to the memory address by the first thread can be minimized or avoided while in the polling loop and other threads can be allowed to execute at the processing device with reduced interference from the waiting thread.

Abstract: A system and method for concurrency control may use slotted read-write locks. A slotted read-write lock is a lock data structure associated with a shared memory area, wherein the slotted read-write lock indicates whether any thread has a read-lock and/or a write-lock for the shared memory area. Multiple threads may concurrently have the read-lock but only one thread can have the write-lock at any given time. The slotted read-write lock comprises multiple slots, each associated with a single thread. To acquire the slotted read-write lock for reading, a thread assigned to a slot performs a store operation to the slot and then attempts to determine that no other thread holds the slotted read-write lock for writing. To acquire the slotted read-write lock for writing, a thread assigned to a slot sets its write-bit and then attempts to determine that the write-lock is not held.

Abstract: Systems and methods for managing divergence of best effort transactional support mechanisms in various transactional memory implementations using a portable transaction interface are described. This interface may be implemented by various combinations of best effort hardware features, including none at all. Because the features offered by this interface may be best effort, a default (e.g., software) implementation may always be possible without the need for special hardware support. Software may be written to the interface, and may be executable on a variety of platforms, taking advantage of best effort hardware features included on each one, while not depending on any particular mechanism. Multiple implementations of each operation defined by the interface may be included in one or more portable transaction interface libraries.

Abstract: Disclosed are methods, systems and products, including a method that includes establishing in a computing environment, implemented using at least one processor-based device, a non-immutable object as being a read-only object, the computing environment not allowing performance of operations that cause modification of the read-only non-immutable object. The method also includes preventing by the at least one processor-based device performance of an operation on the read-only non-immutable object that would cause the read-only non-immutable object to be modified.

Abstract: A system and method for locking memory areas in a Java Virtual Machines (JVM) to facilitate sharing between virtual servers. In accordance with an embodiment, the system comprises a computing/virtual execution environment, which includes one or more physical computers, computer systems, server computers, or similar computing devices, a hypervisor, and a virtual machine or JVM. The JVM allows one or more application images to be run on the computer, wherein the application images can include application server instances. The application server uses a first large page in memory during its startup process, and is configured so that it signals to the JVM when the application server has completed its startup and has potentially pre-optimized important code. When the JVM receives this signal, it internally write-protects or locks the page used for application server code memory, so that any new JITed code or re-optimized code is subsequently written into a new large page.

Abstract: A multi-port memory, comprising: a plurality of ports, each port including port input logic that generates a write enable value from received control signals, and a delay stage coupled to store the write enable value from the input stage, and configured to force the write enable value to a disable state in response to an asserted busy signal of the port; and an arbitration circuit coupled to the ports that arbitrates contending accesses to the ports by de-asserting a busy signal to one port, and asserting a busy signal for all other ports.

Abstract: This invention relates, according to a first aspect, to electronic equipment comprising a processor (2), a memory (11) and a communication module (3) ensuring an interface with an avionics data network. The communication module (3) and the processor (2) are embedded within a microcontroller (1) so that the memory (11) is shared between the processor and the communication module. The electronic equipment also includes a module for monitoring the accesses to the memory (17) which are configured so as to detect an access of the communication module (3) into an unauthorized address area (12) of the memory (11). According to a second aspect, the invention relates to a method of making a processor secure against the failures of a complex peripheral.

Abstract: At least one node of a plurality of nodes in an information processing apparatus executes the following processing for data included in a memory of one node or other nodes and stored in a shared memory area which the node and the other nodes access. That is, the node detects an ICE which occurs over a predetermined number of times within a predetermined time or a PCE which occurs at a single location in the shared memory area. When the error is detected, the node performs control to prevent the node and the other nodes from accessing the shared memory. The node recovers the data in a memory area different from the shared memory area. The node notifies information about the different memory area to the other nodes. The node performs control to resume the access to the data from the node and the other nodes.

Abstract: A control method of a virtual memory is adapted for using in a computer. The control method includes the following steps. First, a plurality of application programs executed in the computer are monitored. Second, the application programs are compared with at least a predetermined program, respectively. Third, the virtual memory of a solid state disk (SSD) is controlled to be turned on or turned off according to a comparing result. Herein, the virtual memory of the SSD is controlled to be turned on or turned off to enhance both lifetime of the SSD and operation efficiency of the computer.

Abstract: A computer processing system having memory and processing facilities for processing data with a computer program is a Hybrid Transactional Memory multiprocessor system with modules 1 . . . n coupled to a system physical memory array, I/O devices via a high speed interconnection element. A CPU is integrated as in a multi-chip module with microprocessors which contain or are coupled in the CPU module to an assist thread facility, as well as a memory controller, cache controllers, cache memory, and other components which form part of the CPU which connects to the high speed interconnect which functions under the architecture and operating system to interconnect elements of the computer system with physical memory, various 1/0, devices and the other CPUs of the system.

Abstract: A storage management system and method for managing access between a plurality of processes and a common store. In one embodiment, each individual process comprises data processing means, a cache for the temporary storage of data generated by the data processing means, and a control unit for managing the transferral of data between the cache and a common store. The control unit comprises a manager for monitoring the availability of storage locations in the store to receive and store data and for allocating data to available storage locations, an interface for transferring the allocated data to the available storage locations, and a locking arrangement for locking the store during data transfer in order to ensure exclusive access and thereby preserve data integrity.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.

Abstract: A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.

Abstract: A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device. A block control device for use in a semiconductor memory includes a block address comparator configured to compare a first block address with a last block address, and output a same pulse or unequal pulse according to the comparison result, a block address driver configured to output a lock state control signal for driving a block address in response to the same pulse, a block address counter configured to count block addresses from the first block address to the last block address in response to the unequal pulse, and generate a block data activation pulse, and a block address register configured to store a lock state of a corresponding block in response to the lock state control signal and the block data activation pulse.

Abstract: Systems and methods of protecting a shared resource in a multi-threaded execution environment in which threads are permitted to transfer control between different software components, for any of which a disclaimable lock having a plurality of orderable locks can be identified. Back out activity can be tracked among a plurality of threads with respect to the disclaimable lock and the shared resource, and reclamation activity among the plurality of threads may be ordered with respect to the disclaimable lock and the shared resource.

Abstract: Systems and methods of protecting a shared resource in a multi-threaded execution environment in which threads are permitted to transfer control between different software components, for any of which a disclaimable lock having a plurality of orderable locks can be identified. Back out activity can be tracked among a plurality of threads with respect to the disclaimable lock and the shared resource, and reclamation activity among the plurality of threads may be ordered with respect to the disclaimable lock and the shared resource.

Abstract: When a thread begins an atomic transaction, the thread reads one or more variables from one or more source addresses. The read portion of the transaction is constrained to a predetermined amount of time or number of cycles (N). The mechanism then performs a test and set operation to determine whether any other threads hold locks on the one or more source addresses. If the locks for the one or more source addresses are free, then the thread acquires locks on the one or more source addresses. The thread then performs work and updates the one or more variables. Thereafter, the mechanism delays for an amount of time or number of cycles greater than or equal to N before releasing the locks. If another thread attempts to acquire a lock on the one or more source addresses, then the test and set operation for that other thread will fail.

Abstract: A storage apparatus is connected via a network to a plurality of host computers requesting data writing. The storage apparatus includes: a volume creation unit for creating virtual volumes to be accessed by the host computers; an allocation unit for allocating a storage area of the storage apparatus to a data storage area of the virtual volumes in response to a data write request from the host computers; and a capacity management unit for managing the capacity of data written from the host computers; wherein the capacity management unit adds the data written from the host computers with regard to each host computer and judges whether a total value of the added data exceeds a specified threshold or not.

Abstract: In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.

Abstract: Embodiments of the present invention provide an approach for intelligent storage planning and planning within a clustered computing environment (e.g., a cloud computing environment). Specifically, embodiments of the present invention will first determine/identify a set of storage area network volume controllers (SVCs) that is accessible from a host that has submitted a request for access to storage. Thereafter, a set of managed disk (mdisk) groups (i.e., corresponding to the set of SVCs) that are candidates for satisfying the request will be determined. This set of mdisk groups will then be filtered based on available space therein, a set of user/requester preferences, and optionally, a set of performance characteristics. Then, a particular mdisk group will be selected from the set of mdisk groups based on the filtering.

Abstract: An approach for automatic storage planning and provisioning within a clustered computing environment is provided. Planning input for a set of storage area network volume controllers (SVCs) will be received within the clustered computing environment, the planning input indicating a potential load on the SVCs and its associated components. Analytical models (e.g., from vendors) can be also used that allow for a load to be accurately estimated on the storage components. Configuration data for a set of storage components (i.e., the set of SVCs, a set of managed disk (Mdisk) groups associated with the set of SVCs, and a set of backend storage systems) will also be collected. Based on this configuration data, the set of storage components will be filtered to identify candidate storage components capable of addressing the potential load. Then, performance data for the candidate storage components will be analyzed to identify an SVC and an Mdisk group to address the potential load.

Abstract: In one embodiment, the present invention includes a method for accessing a shared memory associated with a reader-writer lock according to a first concurrency mode, dynamically changing from the first concurrency mode to a second concurrency mode, and accessing the shared memory according to the second concurrency mode. In this way, concurrency modes can be adaptively changed based on system conditions. Other embodiments are described and claimed.

Abstract: An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node.

Abstract: The invention relates to an EtherCAT fieldbus system, a master and a slave for the system and a method. The slave is configured to be coupled to the EtherCAT fieldbus. A first configurable memory of the slave stores a first activation list indicating for consecutive bytes of data of an EtherCAT datagram a corresponding fieldbus memory management information or synchronization management information.

Abstract: A memory protection method of dividing the address space of a memory into two or more protection regions, and protecting the memory from an unauthorized access to a protection region by a program includes a definition step of defining the relation between protection regions, a determination step of, when the relation between the protection regions is an inclusion relation, determining that an included protection region cannot directly access an including protection region and the including protection region can directly access the included protection region, and a step of, when an access to the protection region determined to be able to be directly accessed is requested, permitting a direct access to the protection region determined to be able to be directly accessed, and prohibiting a direct access to the protection region determined to be unable to be directly accessed.

Abstract: A method of memory sharing implemented by logic of a computer memory control unit, the control unit comprising at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N?2 non-cooperative processors via the second interfaces, the logic operatively coupled to the first and second interfaces. The method includes receiving, via the second interfaces, a request to access data of the main physical memory from a first processor of the set; evaluating if a second processor has previously accessed the data requested by the first processor; and deferring the request from the first processor when the evaluation is positive, or, granting the request from the first processor when the evaluation is negative.

Abstract: A method that includes providing LRU selection logic which controllably pass requests for access to computer system resources to a shared resource via a first level and a second level, determining whether a request in a request group is active, presenting the request to LRU selection logic at the first level, when it is determined that the request is active, determining whether the request is a LRU request of the request group at the first level, forwarding the request to the second level when it is determined that the request is the LRU request of the request group, comparing the request to an LRU request from each of the request groups at the second level to determine whether the request is a LRU request of the plurality of request groups, and selecting the LRU request of the plurality of request groups to access the shared resource.

Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

Abstract: A distributed shared memory multiprocessor that includes a first processing element, a first memory which is a local memory of the first processing element, a second processing element connected to the first processing element via a bus, a second memory which is a local memory of the second processing element, a virtual shared memory region, where physical addresses of the first memory and the second memory are associated for one logical address in a logical address space of a shared memory having the first memory and the second memory, and an arbiter which suspends an access of the first processing element, if there is a write access request from the first processing element to the virtual shared memory region, according to a state of a write access request from the second processing element to the virtual shared memory region.

Abstract: A digital system is provided with a memory interposer module configured to be coupled between a processor module and a memory module. The memory interposer module has a memory controller configured to couple to the memory module. It also includes a first memory emulator configured to couple to the processor module via a connector, wherein the first memory emulator is configured to emulate the memory module. There is an arbiter coupled between the memory controller and the memory emulator. A second memory emulator is connected to the arbiter, wherein the second memory emulator is also configured to emulate the memory module. Each memory emulator is operable to stall a memory request when a conflict occurs.

Abstract: Systems, methods, and computer program products are disclosed for intermixing different types of machine instructions. One embodiment of the invention provides a protocol for intermixing the different types of machine instructions. By adhering to the protocol, different types of machine instructions may be intermixed to concurrently update data structures without leading to unpredictable results.

Abstract: A method for managing software modules of at least two operating systems sharing physical resources of a computing environment, but running in different partitions separated by a virtualization boundary comprises accumulating module information in a virtualization subsystem that directs the creation and management of the partitions. The accumulated module information is used across the virtualization boundary to manage the use of the software modules. Also, a method for managing software modules comprises making at least two operating systems aware that they are being hosted in a virtualized computing environment.

Abstract: Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.

Abstract: In a memory system using a removable recording medium and data stored in the recording medium, identifying information for identifying each recording medium from others is held in the recording medium, and when data stored in the recording medium is used, the identifying information of the recording medium is required. As a result, when a flash memory card, etc. is used, a copyright is reliably protected.