Abstract: In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.

Abstract: A method, system and computer readable medium for joining multiple virtual machines (VMs). The method includes identifying a first virtual machine (VM) executing a first operating system (OS) for joining with a second VM executing a second OS, wherein the first OS and the second OS are compatible. A new VM having a new disk is created, wherein the new disk includes the contents of a first existing disk of the first VM and a second existing disk of the second VM.

Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer usable program code for managing a heap. The heap is partitioned into at least one sub heap based on a relationship to at least one memory class of a plurality of memory classes. A memory allocation request comprising a memory class is received from a requester. A unique heap handle based on the memory class and associated with a specific sub heap is generated. The unique heap handle is then returned to the requester.

Abstract: The present invention is directed to a method and software for managing the host-to-volume mappings of a SAN storage system. The host-to-volume mappings of the SAN storage system are represented in mapping configuration components. The active mapping configuration component represents the current host-to-volume mapping for the SAN storage system. Only one mapping configuration component is active at a time. The host-to-volume mappings of the SAN storage system are changed by deactivating the active mapping configuration component and activating an inactive mapping configuration component that represents a different mapping configuration, effecting a repartition, repurpose, disaster recovery, or other business activity. This can be a scheduled task or performed in an on-demand manner. The mapping configuration components are managed and controlled through the management component of the SAN storage system.

Abstract: Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection.

Abstract: A managed memory in which multiple computing entities each have a corresponding entity-specific portion that is subject to garbage collection. An immutable buffer is located outside of managed memory. For a given computing entity, the corresponding managed memory portion contains entity-specific objects that can be accessed by a specific computing entity, but not by the other multiple computing entities. For one or more of the entity-specific managed memory portions, the portion also includes a reference to shared memory, such as an immutable buffer. The reference is structured to be ignored by the garbage collector, though the reference may appear just as a normal object in the managed memory portion. Thus, a unified memory access model is made possible in which the methods for a computing entity to access a regular object in managed memory is similar to how the computing entity accesses shared memory.

Abstract: A method of implementing virtualization involves an improved approach to resource management. A virtualizing subsystem is capable of creating separate environments that logically isolate applications from each other. Some of the separate environments share physical resources including physical memory. When a separate environment is configured, properties for the separate environment are defined. Configuring a separate environment may include specifying a physical memory usage cap for the separate environment. A global resource capping background service enforces physical memory caps on any separate environments that have specified physical memory caps.

Abstract: A processor 6 is provided with a plurality of hardware resources, such as performance monitors 12 and context pointers 18. Boundary indicating circuitry 14, 20 stores a boundary value which is programmable and which indicates a boundary position dividing the hardware resources into a first portion and a second portion. Resource control circuitry 16, 22 controls access to the hardware resources such that when program execution circuitry 8 is executing a first program it is responsive to a query as to how many off said plurality of hardware resources are present to return a first value whereas when the program execution circuitry is executing a second program it responds to such a query by returning a value corresponding to those hardware resources within the second portion.

Abstract: A host information handling system (IHS) provides virtualization of host channel adapters (HCAs). A hypervisor partitions a system memory of the host IHS into multiple logical partitions (LPARs). A particular LPAR includes a single instance of an operating system. The single instance of the operating system includes a common layer that provides virtualization of physical HCAs and sharing of the physical HCAs by multiple virtual HCAs.

Abstract: A hybrid memory system includes a central processing unit, a storage device configured to store user data and code data, and a main memory including a volatile memory and a nonvolatile memory, the main memory being configured to receive data necessary to perform an operation of the central processing unit from the storage device and to store the data, a part of the volatile memory being allocated for a cache for data stored in the nonvolatile memory.

Abstract: A computer implemented method for sharing physical memory among logical partitions. A computer reserves physical memory of a Central Electronic Complex (CEC) for communication within the CEC as a shared memory pool. The computer creates a first logical partition using resources of the CEC that are not reserved as the shared memory pool. The computer creates a second logical partition using resources of the CEC that are not reserved as the shared memory pool. The computer creates a virtual local area network (VLAN) having at least two addresses within the CEC. The computer allocates a portion of the shared memory to the VLAN as the shared memory pool.

Abstract: A memory architecture for storing information units, the memory architecture comprising a plurality of memory banks or a plurality of memory devices and a memory controller for initiating storage of an information unit and a number of replicas of the information unit in the memory banks or in the memory devices, the memory controller discriminating the replicas in dependence on a size of the information unit.

Abstract: A method of executing an algorithm in a parallel manner using a plurality of concurrent threads includes generating a lock-free barrier that includes a variable that stores both a total participants count and a current participants count. The total participants count indicates a total number of threads in the plurality of concurrent threads that are participating in a current phase of the algorithm, and the current participants count indicates a total number of threads in the plurality of concurrent threads that have completed the current phase. The barrier blocks the threads that have completed the current phase. The total participants count is dynamically updated during execution of the current phase of the algorithm. The generating, blocking, and dynamically updating are performed by at least one processor.

Abstract: A computing device includes a data store having two or more partitions. A first partition can be used to store information, to host a first operating system, and to perform computing tasks requested by a user. The computing tasks can be performed by the first operating system and can use/manipulate the stored information. The computing device can communicate over a network with a software server to determine whether a software update for the computing device is available for download. The software update can be downloaded into the second partition autonomously from the computing tasks being performed by the first operating system in the first partition. The downloaded software update can also be installed into the second partition autonomously from the computing tasks being performed. When the device is rebooted, either the first operating system or the second operating system (if the installation was successful) can be booted.

Abstract: Within a partitioned system, a first system partition operates in a safety domain in which predictable operation of the first system partition is necessary to protect the system or operators of the system from harm. A second system partition operates in a user domain in which information supplied by the second system partition is not sufficiently reliable to be used by the first system partition within the safety domain. A mediator controller is connected between the first system partition and the second system partition. The mediator controller receives the information supplied by the first system partition. The mediator controller monitors and supervises use of the information by the second system partition in order maintain requirements of the safety domain to protect the system or operators of the system from harm.

Abstract: A virtual EEPROM driver is simulated for a virtual switch. A write function may be written to a shared memory device and designated as a virtual EEPROM driver. The virtual EEPROM driver may be duplicated into a non-volatile memory providing availability during a boot process.

Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.

Abstract: An on-disk structure of a file system has the capability to generate snapshots and provide fast sequential read access to data containers, such as files. The on-disk structure arranges sequential portions of files on disk within regions, wherein each region comprises a predetermined amount of disk space represented by blocks and wherein the data of the files stored within each region may or may not be stored sequentially within the region. In addition, the on-disk structure accommodates a plurality of types of regions, including (i) active regions that contain active file system data for large files, (ii) snapshot regions that contain “copy out” snapshot data for the large files and (iii) metadata regions that contain metadata, as well as directories and small files.

Abstract: Disclosed are systems and methods for transporting data using shared memory comprising allocating, by one of a plurality of sender application, one or more pages, wherein the one or more pages are stored in a shared memory, wherein the shared memory is partitioned into one or more pages, and writing data, by the sender application, to the allocated one or more pages, wherein a page is either available for use or allocated to the sender applications, wherein the one or more pages become available after the sender application has completed writing the data. The systems and methods further disclose sending a signal, by the sender application, to a receiver application, wherein the signal notifies the receiver application that writing the data to a particular page is complete, reading, by the receiver application, the data from the one or more pages, and de-allocating, by the receiver application, the one or more pages.

Abstract: A dual-mode, dual-display shared resource computing (SRC) device is usable to stream SRC content from a host SRC device while in an on-line mode and maintain functionality with the content during an off-line mode. Such remote SRC devices can be used to maintain multiple user-specific caches and to back-up cached content for multi-device systems.

Abstract: In one exemplary embodiment, a method includes allocating an arena block of a shared memory of a database node server. The arena block is divided into one or more slots. The one or more slots include a discreet and constant area of memory within the arena block. Each slot is assigned a constant-memory address relative to an arena-block's shared memory address. The index is implemented as a red-black tree data structure. Each red-black tree node is mapped to a slot. Each red-black-tree node is provided a pointer to one or more neighbor nodes. The index stored in shared memory can be used during a ‘warm’ rebooting process.

Abstract: In a system-on-chip (SoC), a method is provided for partitioning access to resources. A plurality of processors is provided, including a configuration master (CM) processor, a memory, a plurality of OSs, and accessible resources. The method creates a mapping table with a plurality of entries, each entry cross-referencing a range of destination addresses with a domain ID, where each domain ID is associated with a corresponding processor. Access requests to the resource are accepted from the plurality of processors. Each access request includes a domain ID and a destination address. A mapping table is consulted to determine the range of destination addresses associated with the access request domain IDs. The accesses are authorized in response to the access request destination addresses matching the range of destination addresses in the mapping table, and the authorized access requests are sent to the destination addresses of the requested resources.

Abstract: An image forming apparatus has a read unit to read a document image and generate image data of the document image, a memory management unit to manage a storage unit which is segmented into storage regions, and an engine to write the image data generated by the read unit to the storage unit. The engine acquires setting information related to writing of the image data from the memory management unit, and writes the image data to the storage unit based on the setting information that is acquired.

Abstract: A request for a physical import/export (I/E) slot is satisfied using a tape library slot that is not a physical I/E slot. According to one embodiment, the request for the physical I/E slot, that is associated with the tape library, is received. A different slot, which is not any of the physical I/E slots associated with the tape library, is used to satisfy the request.

Abstract: The present invention overcomes the disadvantages of the prior art by providing a technique that stripes data containers across volumes of a striped volume set (SVS) using one of a plurality of different data placement patterns to thereby reduce the possibility of hotspots arising due to each data container using the same data placement pattern within the SVS. The technique is illustratively implemented by calculating a first index value, an intermediate index value and calculating a hash value of an inode associated with a data container to be accessed within the SVS. A final index value is calculated by multiplying the intermediate index value by the hash value, modulo the number of volumes of the SVS. Further, a Locate( ) function may be used to compute the location of data container content in the SVS to which a data access request is directed to ensure consistency of such content.

Abstract: A rebuilder application operates on a dispersed data storage grid and rebuilds stored data segments that have been compromised in some manner. The rebuilder application actively scans for compromised data segments, and is also notified during partially failed writes to the dispersed data storage network, and during reads from the dispersed data storage network when a data slice is detected that is compromised. Records are created for compromised data segments, and put into a rebuild list, which the rebuilder application processes.

Abstract: A technique for managing shared memory includes linking address translation data structures used by first and second sharing applications. The first sharing application is managed by a first operating system (OS) and the second sharing application is managed by a second OS that hosts an associated virtual object. Virtual addresses of the first and second sharing applications are bound, based on the linking, to a changeable set of physical addresses that the second OS assigns to the associated virtual object such that the associated virtual object, which is shared by the sharing applications, is pageable by the second OS without permission of the first OS.

Abstract: Embodiments of the present invention provide a computer system, comprising at least two logical partitions, each partition having allocated computing resources, wherein the computing resources allocated to a first partition include memory storing a file system accessible by processes executing in the first partition; and a partition resource allocator, wherein the partition resource allocator is arranged to migrate the memory storing the file system from the first partition to a second partition, such that the file system is accessible by processes executing in the second partition.

Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

Abstract: Aspects include a system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined whether the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations managed in different zones of memory. Based on determining that the memory address refers to the SMO, it is determined whether the configuration has access to the SMO. Based on determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the configuration and the plurality of configurations is allowed.

Abstract: Various embodiments storing volumes of data in a data storage system, including one or more data storage containers, the data storage containers being thin-provisioned to provide virtual data storage capacity which is greater than a real data storage capacity of the data storage hardware are provided. In one embodiment, by way of example only, a real data storage capacity of the data storage system for accommodating new volumes is determined. Over-allocation information relating to one or more data storage containers is determined. Extrapolated future anticipated use of one or more containers of the data storage system from historical data storage use information is determined. One or more candidate data storage containers on the basis of information from the determining the real data storage capacity, over-allocation information, and the extrapolated future anticipated use is selected. Additional system and computer program product embodiments are disclosed and provide related advantages.

Abstract: In one embodiment of the invention, a system is disclosed including a master memory controller and a plurality of memory modules coupled to the master memory controller. Each memory module includes a plurality of read-writeable non-volatile memory devices in a plurality of memory slices to form a two-dimensional array of memory. Each memory slice in each memory module includes a slave memory controller coupled to the master memory controller. When the master memory controller issues a memory module request, it is partitioned into a slice request for each memory slice.

Abstract: At least one node of a plurality of nodes in an information processing apparatus executes the following processing for data included in a memory of one node or other nodes and stored in a shared memory area which the node and the other nodes access. That is, the node detects an ICE which occurs over a predetermined number of times within a predetermined time or a PCE which occurs at a single location in the shared memory area. When the error is detected, the node performs control to prevent the node and the other nodes from accessing the shared memory. The node recovers the data in a memory area different from the shared memory area. The node notifies information about the different memory area to the other nodes. The node performs control to resume the access to the data from the node and the other nodes.

Abstract: A system, method and computer program product for seismic imaging implements a seismic imaging algorithm utilizing Reverse Time Migration technique requiring large communication bandwidth and low latency to convert a parallel problem into one solved using massive domain partitioning. Since in RTM, both the forward and reverse wave propagation is iteratively calculated on time step increments, the method implements methods that includes partitioning memory between computation and intermediate results to optimize an RTM computation. The methods make maximum use of the memory to either eliminate storing the snapshot wavefield data to disk, or hide all or a significant portion of the disk I/O time. Furthermore, the schemes can provide the flexibility to vary a number of iterations (step size) for each snapshot to be kept in the memory. If any of the given conditions changes during the process, maximum usage of the available memory is ensured.

Abstract: A memory control device has a write-request distribution unit and controllers. The write-request distribution unit divides data to be written in a memory and outputs a plurality of divided data blocks obtained by the division while distributing the divided data blocks to a plurality of buses. The controllers write the plurality of divided data blocks output by the write-request distribution unit in the memory through the plurality of buses, with the divided data blocks being in contact with each other in each of the buses.

Abstract: For segments having the number of IOs exceeding a threshold, a data collection unit connects adjacent segments whose distance is within “s” to each other and extracts the connected segments and segments in the range of “s” from outside of the connected segments as an n_segment. A workload analysis unit then determines a target whose data is moved from an HDD to an SSD in units of n_segments.

Abstract: A method of partitioning a physical block in a memory includes: determining a sub-block size according to a data length of a sequential write and a block size; partitioning the physical block into sub-blocks, each having a size equal to the sub-block size; and mapping logical blocks to the sub-blocks.

Abstract: Techniques for configuring and operating a virtual desktop session are disclosed herein. In an exemplary embodiment, an inter-partition communication channel can be established between a virtualization platform and a virtual machine. The inter-partition communication channel can be used to configure a guest operating system to conduct virtual desktop sessions and manage running virtual desktop sessions. In addition to the foregoing, other techniques are described in the claims, the detailed description, and the figures.

Abstract: A storage device includes a memory having one or more storage regions each of which is assigned a physical address, and a controller having a writing control circuit configured to write data that is divided into a plurality of data units into logical storage positions, at least one of which is associated with two storage regions of the memory, and a conversion unit configured to perform a conversion process on a logical address of the logical storage position that is associated with two storage regions of the memory to generate physical addresses corresponding to the two storage regions of the memory.

Abstract: Embodiments of switching between multiple operating systems (OSes) using sleep state management and sequestered re-baseable memory are generally described herein. Embodiments of the invention allow one OS to be suspended into S3 or sleep mode, saving its state to memory and turning off its devices. Then, another sleeping OS can be resumed from another location in memory by switching a memory base addressed to a sequestered memory region and restoring its device state. Other embodiments may be described and claimed.

Abstract: A primary processing unit entitlement is determined for a logical partition. A smaller secondary processing unit entitlement is also determined. A partition manager allocates primary processing units to the logical partition from a primary shared processor pool, and the logical partition is activated. The secondary processing units are reserved for the logical partition from a secondary shared processor pool, and the logical partition can be relocated to the secondary shared processor pool in response to a condition such as a hardware failure. The logical partition can continue to process its workload with the fewer processor resources, and can be restored to the primary processing unit entitlement.

Abstract: Profile properties in a partition profile are user-configurable through a management entity such as a management console. A partition manager calculates a secondary processing unit entitlement for a logical partition based in part on a secondary processing unit mode property in the partition profile. The secondary processing unit entitlement may be smaller than a primary processing unit entitlement for the logical partition. The partition manager reserves processing units from a secondary shared processor pool equal to the logical partition's secondary entitlement for the logical partition. The primary and secondary processing unit entitlements may be stored in primary and secondary configuration data structures associated with the logical partition. The partition manager may relocate the logical partition to the secondary shared processor pool in response to a predetermined condition.

Abstract: A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined condition, such as a hardware failure. The relocated logical partition is allocated a smaller quantity of processing units from the secondary pool than it was allocated from the primary pool. A quantity of processing units reserved for a second logical partition is identified in the secondary shared processor pool, and a portion of those reserved processing units are allocated to the relocated logical partition. The reserved processing units may be redistributed among multiple relocated logical partitions.

Abstract: Systems and methods may be implemented in a power device subsystem topology to provide an arbitration and communication scheme between a single consolidated non-volatile random access (NVRAM) memory device and multiple discrete digital power controller devices in a manner that provides data protection and the ability to update the full NVRAM content when needed.

Abstract: Domains can also be used to control access to physical memory space. Data in a physical memory space that has been used by a process sometimes endures after the process stops using the physical memory space (e.g., the process terminates). In addition, a virtual memory manager may allow processes of different applications to access a same memory space. To prevent exposure of sensitive/confidential data, physical memory spaces can be designated for a specific domain or domains when the physical memory spaces are allocated.

Abstract: A technology can be provided for managing shared memory used by a plurality of compute nodes. An example system can include a shared globally addressable memory to enable access to shared data by the plurality of compute nodes. A memory interface can process memory requests sent to the shared globally addressable memory from the plurality of processors. A memory write module can be included for the memory interface to allocate memory locations in the shared globally addressable memory and write read-only data to the globally addressable memory from a writing compute node. In addition, a read module for the memory interface can map read-only data in the globally addressable shared memory as read-only for subsequent accesses by the plurality of compute nodes.

Abstract: According to one embodiment, a memory system comprises a storage areas each having a physical page that is data-write- and read-accessible, the storage areas being divided into a plurality of parallel operation elements capable of performing a parallel operation, and the physical pages of the storage areas being associated with a logical page, a storage unit having a first buffer configured to store data to be rewritten in the storage areas, and a control unit configured to perform data transfer between the storage areas and the storage unit. The control unit comprises a logical page management unit configured to divide the logical page in a predetermined number of parallel operation elements out of the plurality of parallel operation elements, and a system control unit configured to perform a predetermined operation in each of the divided logical pages.

Abstract: An apparatus having one or more memories and a controller is disclosed. The memories are divided into a plurality of regions. Each regions is divided into a plurality of blocks. The blocks correspond to a plurality of memory addresses respectively. The controller is configured to (i) receive data from a host, (ii) generate metadata that maps a plurality of host addresses of the data to the memory addresses of the memories and (iii) write sequentially into a given one of the regions both (a) a portion of the data and (b) a corresponding portion of the metadata.

Abstract: The present disclosure includes methods and systems that share memory located on one PCIe based HBA across other PCIe based HBAs in the system. In addition, the backup battery is effectively shared across multiple PCIe based HBAs in the system. This approach saves significant costs by avoiding the need to have a separate DRAM with its own dedicated battery backup on each HBA board in the system. This also allows the redundant memory and backup batteries to be removed while still retaining the same functionality through the common DDR3 memory chip and battery backup shared across multiple HBAs in the system. The component cost for batteries and memory, management module, board space, and the board manufacturing cost are all reduced as a result.

Abstract: A storage integrity system in a dispersed storage network scans an address range of data slices to identify errors in one of a plurality of encoded data slices, wherein the plurality of encoded data slices are generated from a data segment using an error encoding dispersal function. When the storage integrity system detects an error, it identifies one of the encoded data slices for rebuilding. The identified data slice is rebuilt in response to the type of error. For example, when the type of the error includes a temporary error, the storage integrity system waits a predetermined time period to determine whether the error still exists prior to rebuilding the identified data slice.