Memory Partitioning Patents (Class 711/173)
  • Publication number: 20140372725
    Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gheorghe Almasi, Barnaby Dalton, Ilie G. Tanase, Ettore Tiotto
  • Publication number: 20140372724
    Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gheorghe Almasi, Barnaby Dalton, Ilie G. Tanase, Ettore Tiotto
  • Patent number: 8914607
    Abstract: A broadcast receiving apparatus and memory managing method thereof are provided. The broadcast receiving apparatus includes a storage unit which includes a plurality of memory areas for each of a plurality of operating systems, a determination unit which periodically determines a retrievable memory area for each of the plurality of memory areas, and a controller which reallocates at least part of the retrievable memory area, if memory area reallocation is necessary.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-ho Choi
  • Patent number: 8914806
    Abstract: A virtual storage management method that can increase the overall processing speed while preventing a processor from being overloaded. A request for acquisition of a memory area in a primary storage device is received from a process executed by a processor. It is determined whether or not the process that has made the acquisition request is a utility process executable in cooperation with another process. Control is provided so as to restrict swap-out of the utility process when it is determined that the process that has made the received acquisition request is a utility process executable in cooperation with another process, and a process cooperating with the utility process executed by the processor is a preferred process of which swap-out is restricted, and a processor utilization of the preferred process is greater than a predetermined value.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: December 16, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Akira Ishikawa
  • Patent number: 8914606
    Abstract: According to at least one embodiment, a method comprises partitioning a computer system into a plurality of soft partitions that each run an operating system. The method further comprises instantiating a separate firmware instance for each of the plurality of soft partitions, wherein each of the firmware instances provides a pre-defined firmware interface for the operating system of its respective soft partition.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: December 16, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Bradley G. Culter
  • Patent number: 8909893
    Abstract: System embodiments for facilitating overflow storage of special data sets that reside on a single logical volume are provided. A virtual logical volume is created from unallocated memory units across a plurality of logical volumes in a volume group. The virtual logical volume appears the same as any one of the logical volumes in the volume group to an external client. Upon receipt of a special data set that must reside in a single logical volume, an attempt is first made to allocate the special data set to one of the logical volumes in the volume group. If that allocation attempt fails, the special data set is allocated to the virtual logical volume. The virtual logical volume may be created only upon the failure to allocate the special data set to one of the logical volumes, and may be destroyed if sufficient space in one of the logical volumes is freed up to transfer the special data set.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: David C. Reed, Max D. Smith, Kyle B. Dudgeon, Esteban Rios
  • Patent number: 8909854
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory which stores data in units of a write unit includes cells, and a controller which controls the memory and partitions memory space of the memory. In response to a request to write write-data to the memory from a host, the controller requests the host to transmit a segment of the write-data with a specified size. The write-data segment has a size of an integral multiple of a size determined to allow for a set of the write-data segment and corresponding additional data to be the largest while smaller than the write unit. Before completion of processing a first command which requests access to a first partition, the controller accepts a second command which requests access to a second partition.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Yamagishi, Atsushi Shiraishi, Misao Hasegawa
  • Patent number: 8909716
    Abstract: Administering truncated receive functions in a parallel messaging interface (‘PMI’) of a parallel computer comprising a plurality of compute nodes coupled for data communications through the PMI and through a data communications network, including: sending, through the PMI on a source compute node, a quantity of data from the source compute node to a destination compute node; specifying, by an application on the destination compute node, a portion of the quantity of data to be received by the application on the destination compute node and a portion of the quantity of data to be discarded; receiving, by the PMI on the destination compute node, all of the quantity of data; providing, by the PMI on the destination compute node to the application on the destination compute node, only the portion of the quantity of data to be received by the application; and discarding, by the PMI on the destination compute node, the portion of the quantity of data to be discarded.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, Michael A. Blocksome, Joseph D. Ratterman, Brian E. Smith
  • Patent number: 8909891
    Abstract: Method embodiments for facilitating overflow storage of special data sets that reside on a single logical volume are provided. A virtual logical volume is created from unallocated memory units across a plurality of logical volumes in a volume group. The virtual logical volume appears the same as any one of the logical volumes in the volume group to an external client. Upon receipt of a special data set that must reside in a single logical volume, an attempt is first made to allocate the special data set to one of the logical volumes in the volume group. If that allocation attempt fails, the special data set is allocated to the virtual logical volume. The virtual logical volume may be created only upon the failure to allocate the special data set to one of the logical volumes, and may be destroyed if sufficient space in one of the logical volumes is freed up to transfer the special data set.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: David Charles Reed, Max Douglas Smith, Kyle Barret Dudgeon, Esteban Rios
  • Patent number: 8907964
    Abstract: A system to process a plurality of vertices to model an object. An embodiment of the system includes a processor, a front end unit coupled to the processor, and cache configuration logic coupled to the front end unit and the processor. The processor is configured to process the plurality of vertices. The front end unit is configured to communicate vertex data to the processor. The cache configuration logic is configured to establish a cache line size of a vertex cache based on a vertex size of a drawing command.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: December 9, 2014
    Assignee: Vivante Corporation
    Inventors: Keith Lee, Mike M. Cai
  • Publication number: 20140359249
    Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for storing data in an adjustably partitionable memory array, and a method to store data in an adjustably partitionable memory array. According to an embodiment of the disclosure, a system to store data in an adjustably partitionable memory array is provided, the system including a plurality of memory cells arranged in an array of rows and columns, a plurality of bit lines, and a plurality of switches, wherein each bit line is electrically coupled to a column of memory cells and each bit line comprises a switch configured to allow the respective bit line to be partitioned by opening of the switch.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 4, 2014
    Inventors: Rex Kho, Michael Hassel, Wolfgang Beck, Thomas Liebermann
  • Patent number: 8904146
    Abstract: Described are techniques for performing data storage system management. The data storage system is divided into a plurality of virtual partitions. A plurality of policy sets are specified where each of the policy sets includes one or more policies. One of the plurality of policy sets is assigned to each of the plurality of virtual partitions. Each of the plurality of policy sets includes an access control policy that assigns a portion of data storage of the data storage system as a resource for exclusive use in one of the plurality of virtual partitions that is assigned said each policy set.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: December 2, 2014
    Assignee: EMC Corporation
    Inventor: Gregory W. Lazar
  • Patent number: 8904067
    Abstract: An adaptive multi-thread buffer supports multiple writer process and reader processes simultaneously without blocking. Writer processes are assigned a reserved write slot using a writer index that is incremented for each write request. When a reserved write slot is not null, the buffer is resized to make room for new data. Reader processes are assigned a reserved read slot using a reader index that is incremented for each read request. When data is read out to the reader process, the read slot content is set to null. When a writer process attempts to write null data to a write slot, the buffer replaces the null write data with an empty value object so that content of the buffer is null only for empty slots. When an empty value object is read from a slot, the buffer replaces the content with null data to send to the reader process.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: December 2, 2014
    Assignee: Microsoft Corporation
    Inventor: Erwien Saputra
  • Patent number: 8904145
    Abstract: Acceptable memory allocation for a partition is determined during and with minimal impact on normal operation of the partitioned system. The approach includes: collecting, by a processor, statistics on a rate at which pages are transferred between uncompressed and compressed memory spaces of the partition's memory; adjusting size of the uncompressed memory space; and subsequent to the adjusting, continuing with collecting of the statistics, and referencing the resultant statistics in determining an acceptable memory allocation for the partition. In one implementation, the adjusting includes stepwise decreasing size of the uncompressed memory space by reallocating uncompressed memory space to compressed memory space, and repeating the collecting of statistics for a defined measurement period for each adjusted uncompressed memory space size until performance of the partition is negatively impacted by the reallocation of uncompressed memory space to compressed memory space.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark R. Funk, Vernon R. Pahl, Ronald D. Young
  • Publication number: 20140351550
    Abstract: Disclosed herein are a memory management apparatus and method for threads of Data Distribution Service middleware. The apparatus includes a memory area management unit, one or more thread heaps, and a queue. The memory area management unit partitions a memory chunk allocated for the DDS middleware by a Cyber-Physical System on a memory page basis, manages the partitioned memory pages, and allocates the partitioned memory pages to the threads of the DDS middleware that have requested memory. The thread heaps are provided with the memory pages allocated to threads of the DDS middleware by the memory area management unit, and manage the provided memory pages. The queue receives memory used pages returned by the thread heaps. The thread heaps are provided with the memory pages for the threads by the queue if a memory page is not present in the memory area management unit when the threads request memory.
    Type: Application
    Filed: July 26, 2013
    Publication date: November 27, 2014
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyung-Kook JUN, Jae-Hyuk KIM, Soo-Hyung LEE, Won-Tae KIM
  • Patent number: 8898370
    Abstract: A data storage method for storing data into a flash memory chip is provided. The flash memory chip has a plurality of physical addresses, and these physical addresses include a plurality of fast physical addresses and a plurality of slow physical addresses. In the data storage method, the usage rate of the physical addresses is monitored. When the usage rate is not larger than a usage rate threshold value, only the fast physical addresses are used for storing the data into the flash memory chip. When the usage rate is larger than the usage rate threshold value, the fast physical addresses and the slow physical addresses are used for storing the data into the flash memory chip. Thereby, the speed of storing data into the flash memory chip is effectively increased.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: November 25, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Kang Yeh, Yong-Long Su
  • Patent number: 8898399
    Abstract: Disclosed are systems and methods for transporting data using shared memory comprising allocating, by one of a plurality of sender application, one or more pages, wherein the one or more pages are stored in a shared memory, wherein the shared memory is partitioned into one or more pages, and writing data, by the sender application, to the allocated one or more pages, wherein a page is either available for use or allocated to the sender applications, wherein the one or more pages become available after the sender application has completed writing the data. The systems and methods further disclose sending a signal, by the sender application, to a receiver application, wherein the signal notifies the receiver application that writing the data to a particular page is complete, reading, by the receiver application, the data from the one or more pages, and de-allocating, by the receiver application, the one or more pages.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: November 25, 2014
    Assignee: TIBCO Software Inc.
    Inventors: Dan Leshchiner, Balbhim Mahurkar
  • Patent number: 8898422
    Abstract: A workload-aware distributed data processing apparatus and method for processing large data based on hardware acceleration are provided. The data processing apparatus includes a memory buffer including partitions. The data processing apparatus further includes a partition unit configured to distribute a mapping result to the partitions based on a partition proportion scheme. The data processing apparatus further includes a reduce node configured to receive content of a corresponding one of the partitions, and perform a reduction operation on the content to generate a reduce result.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-June Jung, Ju-Pyung Lee
  • Patent number: 8898421
    Abstract: An electronic device having one or more services made available to a host equipment with which it is connected. The device automatically adjusts the access capability to the services made available depending on the software platform available within the host equipment. The electronic device may include a platform identifier operating on data exchanged with the host equipment to identify the platform. The electronic device may be an electronic storage device providing access capability for reading/writing to memory, wherein the access capability is adapted to the host equipment. A memory may be partitioned into areas of memory dedicated to first and second types of software platforms available within the host equipment, and an area independent of the type of software platform. A memory may also be operated to list services authorized for a given platform, wherein a reference to this memory may be contained in a reserved memory.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: November 25, 2014
    Assignee: Gemalto SA
    Inventor: Stephane Durand
  • Patent number: 8898388
    Abstract: In one embodiment, non-volatile random access memory (NVRAM) caching and logging delivers low latency acknowledgements of input/output (I/O) requests, such as write requests, while avoiding loss of data. Write data may be stored in a portion of an NVRAM configured as, e.g., a persistent write-back cache, while parameters of the request may be stored in another portion of the NVRAM configured as one or more logs, e.g., NVLogs. The write data may be organized into separate variable length blocks or extents and “written back” out-of-order from the write back cache to storage devices, such as solid state drives (SSDs). The write data may be preserved in the write-back cache until each extent is safely and successfully stored on SSD (i.e., in the event of power loss), or operations associated with the write request are sufficiently logged on NVLog.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: November 25, 2014
    Assignee: NetApp, Inc.
    Inventor: Jeffrey S. Kimmel
  • Publication number: 20140344508
    Abstract: Processing a plurality of data units to generate result information, includes: performing a data operation for each data unit of a first subset of data units from the plurality of data units, and storing information associated with a result of the data operation in a first set of one or more data structures stored in working memory space of a memory device; after an overflow condition on the working memory space is satisfied, storing information in overflow storage space of a storage device; and repeating an overflow processing procedure multiple times during the processing of the plurality of data units, the overflow processing procedure including: updating a new set of one or more data structures stored in the working memory space using at least some information stored in the overflow storage space.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 20, 2014
    Applicant: Ab Initio Technology LLC
    Inventors: Muhammad Arshad Khan, Stephen G. Rybicki, Joel Gould
  • Publication number: 20140344547
    Abstract: Memory resource partitioning code allocates a memory partition in response to a process requesting access to memory storage. Memory partition rules may define attributes of the memory partition. The attributes may include a minimum memory allocation and a maximum memory allocation for the memory partition.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventor: Michael Kisel
  • Patent number: 8892812
    Abstract: A data writing method for a flash memory. First, a plurality of blocks of a flash memory is classified into a plurality of block groups according to the erase counts of the blocks. A logical address range of a host is then divided into a plurality of logical address sections respectively corresponding to the block groups. Write data is then received from the host. A target logical address section to which the logical address of the write data belongs is then determined. A target block group corresponding to the target logical address section is then determined. A target block is then selected from the blocks of the target block group. The write data is then written to the target block.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 18, 2014
    Assignee: Silicon Motion, Inc.
    Inventor: Hsu-Ping Ou
  • Patent number: 8892844
    Abstract: Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: November 18, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Robert Walker
  • Patent number: 8885203
    Abstract: An optical reading device has an optical reading unit having optical elements disposed in a line that reads a medium; a storage unit having a ring buffer formed in the storage space; and a control unit that writes scanned data read by the optical reading unit to the ring buffer, reads the scanned data written to the ring buffer, and transfers the scanned data that was read. The control unit also manages positions in the ring buffer for writing and reading the scanned data using a write pointer denoting the position for writing the scanned data to the ring buffer, and a read pointer denoting the position of scanned data that has not been read.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: November 11, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Kenji Asada
  • Patent number: 8886911
    Abstract: Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Siamack Nemazie, Farshid Tabrizi, Berhanu Iman, Ruchir Shah, William E. Benson, Michael George
  • Patent number: 8886912
    Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Beem Im, Hye-Young Kim, Young-Joon Choi, Dong-Gi Lee, Shea-Yun Lee
  • Patent number: 8880795
    Abstract: Multiple memory devices, such as hard drives, can be combined and logical partitions can be formed between the drives to allow a user to control regions on the drives that will be used for storing content, and also to provide redundancy of stored content in the event that one of the drives fails. Priority levels can be assigned to content recordings such that higher value content can be stored in more locations and easily accessible locations within the utilized drives. Users can control and organize how recorded content is stored between the drives such that an external drive may be removed from a first gateway device and attached to a second gateway device without losing the ability to access the recorded content from the first gateway device at a later time. In this manner, a user is provided with the ability to transport an external drive containing stored content recordings between multiple different gateway devices such that the recordings may be accessed at different locations or user premises.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: November 4, 2014
    Assignee: Comcast Cable Communications, LLC.
    Inventor: Ross Gilson
  • Patent number: 8880582
    Abstract: A partitionable server that enables user access thereto is provided. The partitionable server includes a plurality of partitions, each running an independent instance of an operating system (OS) and a first management module located in the partitionable server and interfacing with the plurality of partitions, the first management module is separate from the plurality of partitions and includes a physical user interface for local access to the partitionable server. The first management module is operable to provide mapping of a physical user interface device, which locally accesses the partitionable server through the physical user interface, to a virtual user interface of any one of the plurality partitions as desired for accessing the one partition.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: November 4, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Daniel Zilavy
  • Patent number: 8880858
    Abstract: Illustrative embodiments include a method, system, and computer program product for estimating boot-time memory requirement of a data processing system. A data processing system identifies, using system configuration information associated with the data processing system, a set of components needed for booting up the data processing system. The data processing system determines a dependency of a component identified in the set of components, the component including a memory estimator program. The data processing system determines an ancestry of the component identified in the set of components. The data processing system receives, using the memory estimator program of the component, a boot-time memory requirement of the component. The data processing system calculates a total boot-time memory requirement. The data processing system determines whether an amount of real memory of the data processing system satisfies the total boot-time memory requirement.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Vishal Chittranjan Aslot, Adekunle Bello, Liang Jiang
  • Patent number: 8881146
    Abstract: A method and apparatus for creating a machine image to be used in instantiating virtual nodes in a cloud computing environment. A virtual machine operating system image is created based on the configuration file. The machine operating system image is loaded in the cloud environment as a machine instance. An EBS disk is created based on the configuration file, and the EBS disk is attached to the machine instance. The method and apparatus allow software to be provisioned on the fly merely by being specified in the configuration file, which can be an XML file or other declarative document.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: November 4, 2014
    Assignee: Infosys Limited
    Inventors: Srinivas Padmanabhuni, Allahbaksh M. Asadullah, Basava M. Raju
  • Patent number: 8880841
    Abstract: Embodiments of the present invention provide an approach to forecast a potential demand for partitioned/sharded data and to distribute the data among a set of data partitions based on forecasted demand to optimize network characteristics (e.g., network bandwidth) and/or expedite data retrieval. For example, the data may be distributed among the partitions based on a quantity of trends/requests/hits on the data, so that requests for the data can be balanced among the partitions geographically.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ryan G. DeJana, Lisa Seacat DeLuca, Soobaek Jang, Daniel C. Krook
  • Patent number: 8880825
    Abstract: A LUN is provided that can store multiple datasets (e.g., data and/or applications, such as virtual machines stored as virtual hard drives). The LUN is partitioned into multiple partitions. One or more datasets may be stored in each partition. As a result, multiple datasets can be accessed through a single LUN, rather than through a number of LUNs proportional to the number of datasets. Furthermore, the datasets stored in the LUN may be pivoted. A second LUN may be generated that is dedicated to storing a dataset of the multiple datasets stored in the first LUN. The dataset is copied to the second LUN, and the second LUN is exposed to a host computer to enable the host computer to interact with the dataset. Still further, the dataset may be pivoted from the second LUN back to a partition of the first LUN.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: November 4, 2014
    Assignee: Microsoft Corporation
    Inventors: Chris Lionetti, Robert Pike
  • Patent number: 8880837
    Abstract: Provided are a computer program product, system, and method for preemptively allocating extents to a data set in a storage system. A data set is comprised of a plurality of extents configured in at least one volume in the storage system. A first extent is allocated to the data set in a first volume to extend the data set. A determination is made as to whether a second extent can be allocated to the data set in the first volume in response to the allocating of the first extent. The second extent in a second volume is allocated for the data set in response to determining that the second extent cannot be allocated to the data set in the first volume.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kyle B. Dudgeon, David C. Reed, Esteban Rios, Max D. Smith
  • Publication number: 20140325126
    Abstract: A method of operating a data storage device comprises allocating a plurality of data blocks among received data to a plurality of intellectual property (IP) cores, performing an atomic write independently for of the IP cores, wherein the atomic write for each of the IP cores writes corresponding allocated data blocks to a corresponding memory region of the data storage device, and generating an independent identifier indicating completion of the atomic write for each of the IP cores.
    Type: Application
    Filed: April 28, 2014
    Publication date: October 30, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: SANG HOON CHOI, MOON SANG KWON, ALAIN TRAN, SANG PHIL LIM, HYUNG JIN IM
  • Patent number: 8874981
    Abstract: An exemplary method of creating a target storage layout table referenced for partitioning a storage space of a storage device includes following steps: identifying defective storage areas in the storage space of the storage device, and accordingly generating an identification result; and creating the target storage layout table according to the identification result.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: October 28, 2014
    Assignee: Mediatek Inc.
    Inventors: Meng-Chang Liu, Chen-Tsung Hsieh
  • Patent number: 8874830
    Abstract: A control method for a Flash memory array and a Flash memory is disclosed. The Flash memory array includes a plurality of blocks which are classified into groups and each group includes at least one block. The control method includes the steps of: recognizing an attribute of data transferred from a host, obtaining a storage group selected from the groups based on the attribute of the data, and storing the data into the blocks of the storage group and thereby the blocks of a same group store data of a same attribute; and performing a valid data collection, restricted to the blocks belonging to a same group, to release blocks of space.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: October 28, 2014
    Assignee: Silicon Motion, Inc.
    Inventor: Chang-Kai Cheng
  • Patent number: 8874854
    Abstract: A mechanism for selectively disabling and enabling read caching based on past performance of the cache and current read/write requests. The system improves overall performance by using an autonomic algorithm to disable read caching for regions of backend disk storage (i.e., the backstore) that have had historically low cache hit ratios. The result is that more cache becomes available for workloads with larger hit ratios, and less time and machine cycles are spent searching the cache for data that is unlikely to be there.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Lee Charles La Frese, Joshua Douglas Martin, Justin Thomson Miller, Vernon Walter Miller, James Russell Thompson, Yan Xu, Olga Yiparaki
  • Patent number: 8874848
    Abstract: A change in workload characteristics detected at one tier of a multi-tiered cache is communicated to another tier of the multi-tiered cache. Multiple caching elements exist at different tiers, and at least one tier includes a cache element that is dynamically resizable. The communicated change in workload characteristics causes the receiving tier to adjust at least one aspect of cache performance in the multi-tiered cache. In one aspect, at least one dynamically resizable element in the multi-tiered cache is resized responsive to the change in workload characteristics.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: October 28, 2014
    Assignee: Net App, Inc.
    Inventors: Gokul Soundararajan, Kaladhar Voruganti, Lakshmi Narayanan Bairavasundaram, Priya Sehgal, Vipul Mathur
  • Patent number: 8868829
    Abstract: A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits; receiving, at an interface circuit, a first command issued from the system to the virtual memory circuit; and in response to receiving the first command, 1) directing a copy of the first command to a first physical memory circuit of the multiple physical memory circuits, and 2) performing a power-saving operation on at least one other physical memory circuit of the multiple physical memory circuits.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: October 21, 2014
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Patent number: 8861013
    Abstract: A CPU perform the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area; (b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and (c) causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area. The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) along the order of (a), (b), (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).
    Type: Grant
    Filed: November 10, 2013
    Date of Patent: October 14, 2014
    Assignee: Kyocera Document Solutions Inc.
    Inventor: Hiroyuki Hara
  • Patent number: 8862853
    Abstract: A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform, which includes Virtual Machine Monitor (VMM) managed components coupled to the VMM and a plurality of Virtual Machines (VMs). One of the VMM managed components is a Trusted Platform Module (TPM) Each virtual machine includes a guest Operating System, a TPM device driver (TDD), and at least one security application. The VMM creates an intra-partition in memory for each TDD such that other code and information at a same or higher privilege level in the VM cannot access the TDD's memory contents. The VMM also maps access only from the TDD to a TPM register space specifically designated for the VM requesting access. Contents of the TPM requested by the TDD are stored in an exclusively VMM-managed protected page table that provides hardware-based memory isolation for the TDD.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Ravi Sahita, Travis T. Schluessler
  • Patent number: 8862852
    Abstract: A method is disclosed to selectively provide information to one or more remote computing devices. The method provides an information storage and retrieval system comprising first information, a first logical partition, and a second logical partition, where the first information is disposed in the first logical partition. The method further provides a data extraction algorithm, forms second information comprising an instantaneous point-in-time copy of the first information, and forms third information from the second information using the data extraction algorithm. The method then migrates the third information from the first logical partition to the second logical partition, and provides access rights to that third information to one or more computing devices capable of communicating with the information storage and retrieval system.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventor: Robert F. Kern
  • Patent number: 8862855
    Abstract: The present invention is adapted to data storage technology field, and provides a reading/writing control method and system for nonvolatile memory, the method including the following steps: dividing valid blocks in the nonvolatile memory into different zones, the zones including at least one data zone having fixed number of valid blocks and one exchange zone having at least two valid blocks; creating a mapping table of logic blocks and physical blocks in each zone; establishing a mapping table of logic pages and physical pages in the blocks based on redundant area information of pages in the blocks, and storing the mapping table of the logic blocks and physical blocks in each zone and the mapping table of logic pages and physical pages in each block in a private data area; and writing data segments in an idle page of the blocks of the data zones in sequence, or reading data segments from valid pages in the data zones, thus the data reading/writing speed and efficiency is promoted.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: October 14, 2014
    Assignee: Shenzhen Netcom Electronics Co., Ltd.
    Inventors: Zhixiong Li, Enhua Deng, Dan Guo
  • Patent number: 8856488
    Abstract: Apparatuses and methods for implementing partitioning in memory cards and modules where conventional memory cards or modules have only a single partition. A representative memory card/module in accordance with the invention includes a memory device(s), and a memory interface which includes a data bus, a command line and a clock line. The memory card/module further includes a memory controller coupled to the memory device(s) and to the memory interface. The memory card/module includes means for controlling the partitioning of the memory device(s), and the memory controller is configured to operate the memory device(s) in accordance with the partition information.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: October 7, 2014
    Assignee: Memory Technologies LLC
    Inventors: Yevgen Gyl, Jussi Hakkinen, Kimmo J. Mylly
  • Patent number: 8856486
    Abstract: A technique deploys a copy of a disk image from source storage to target storage. The technique involves identifying a particular disk image to be copied from the source storage to the target storage. The technique further involves performing a comparison operation between a first disk image list which lists disk images on the source storage and a second disk image list which lists disk images on the target storage to generate a common disk image list which lists a set of common disk images on both the source and target storage. The technique further involves transferring, from the source storage to the target storage, a set of data portions representing differences between the particular disk image and a common disk image listed on the common disk image list. The set of data portions in combination with the common disk image form a deployed copy on the target storage.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: October 7, 2014
    Assignee: Citrix Systems, Inc.
    Inventors: Richard William Sharp, David Jonathan Scott, Jonathan James Ludlam
  • Patent number: 8856293
    Abstract: A network-attached storage (NAS) device comprises an operational state comprising first system settings; a network interface configured to couple to a network and a processor coupled to the network interface. The processor may be configured to identify a NAS configuration image stored on an externally accessible storage device, the NAS configuration image comprising second system settings created from an other NAS device on the network; determine that the NAS configuration image is compatible with the NAS device; receive a copy of the NAS configuration image; compare the second system settings with the first system settings to identify compatible system settings, and modify the first system settings based on the compatible system settings.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: October 7, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Nauzad Sadry
  • Patent number: 8856487
    Abstract: Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Emanuele Confalonieri, Corrado Villa
  • Patent number: 8850154
    Abstract: Memory resource partitioning code allocates a memory partition in response to a process requesting access to memory storage. Memory partition rules may define attributes of the memory partition. The attributes may include a minimum memory allocation and a maximum memory allocation for the memory partition.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: September 30, 2014
    Assignee: 2236008 Ontario Inc.
    Inventor: Michael Kisel
  • Patent number: 8849941
    Abstract: Techniques for configuring and operating a virtual desktop session are disclosed herein. In an exemplary embodiment, an inter-partition communication channel can be established between a virtualization platform and a virtual machine. The inter-partition communication channel can be used to configure a guest operating system to conduct virtual desktop sessions and manage running virtual desktop sessions. In addition to the foregoing, other techniques are described in the claims, the detailed description, and the figures.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: September 30, 2014
    Assignee: Microsoft Corporation
    Inventors: Mahadeva Alladi, Sriram Sampath, Ido Ben-Shachar, Dustin L. Green, Ashwin Palekar