Virtual Machine Memory Addressing Patents (Class 711/6)
  • Patent number: 9864626
    Abstract: In a computer system, joint operation of multiple hypervisors is coordinated. A persistent hypervisor and a non-persistent hypervisor are executed. The non-persistent hypervisor is executed in the supervisor mode according to an operating regime controlled by a scheduler engine, and the persistent hypervisor is executed in the hypervisor mode under the control of a handler engine. The handler engine monitors, and responds, to an attempted mode transition of the processor between the hypervisor and supervisor modes, and coordinates the suspension and resumption, as appropriate, of the persistent hypervisor.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 9, 2018
    Assignee: AO KASPERSKY LAB
    Inventors: Vyacheslav I. Levchenko, Igor Y. Kumagin
  • Patent number: 9858198
    Abstract: In an embodiment, a processor includes logic to provide a first virtual address of first data stored in a memory at a first physical address. The memory includes pages of a memory allocation unit page size. The processor also includes translation logic to access the first data via a first virtual to physical address translation that includes a first hierarchy of page translation tables to map to a first page having a first page size that is smaller than the memory allocation unit size. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventor: Larry Seiler
  • Patent number: 9858202
    Abstract: Methods and apparatus relating to low overhead paged memory runtime protection are described. In an embodiment, permission information for guest physical mapping are received prior to utilization of paged memory by an Operating System (OS) based on the guest physical mapping. The permission information is provided through an Extended Page Table (EPT). Other embodiments are also described.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Ravi L. Sahita, Xiaoning Li, Manohar R. Castelino
  • Patent number: 9851992
    Abstract: A hypervisor of a host detects a request by a guest or a hypervisor administrator to expose a device associated with the host to the guest. The hypervisor locates free space in a configuration space of the device. The hypervisor assigns a configuration space associated with the hypervisor to the located free space. The hypervisor notifies the guest of the configuration space associated with the hypervisor and a range of addresses associated with the free space. The hypervisor exposes the device to the guest. The configuration space associated with the hypervisor may be a message-signaled capability associated with the hypervisor.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: December 26, 2017
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Alex Williamson
  • Patent number: 9852054
    Abstract: A mechanism is provided for managing memory of a runtime environment executing on a virtual machine. The mechanism includes an elastic cache made of objects within heap memory of the runtime environment. When the runtime environment and virtual machine are not experiencing memory pressure from a hypervisor, the objects of the elastic cache may be used to temporarily store application-level cache data from applications running within the runtime environment. When memory pressure from the hypervisor is exerted, the objects of the elastic cache are re-purposed to inflate a memory balloon within heap memory of the runtime environment.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: December 26, 2017
    Assignee: VMware, Inc.
    Inventor: Benjamin J. Corrie
  • Patent number: 9854036
    Abstract: A method for migrating memory data of a virtual machine, and a related apparatus, and a cluster system are provided. The method includes: obtaining a data sending request for sending memory data of a first virtual machine, where the request includes an identity of the first virtual machine and a PFN of the memory data that is requested to be sent; querying a correspondence information base according to the identity of the first virtual machine to obtain a correspondence of the first virtual machine; querying the correspondence of the first virtual machine according to the PFN of the memory data that is requested to be sent, so as to obtain a physical memory page address of the memory data; and sending, to a destination physical host by using an RDMA network adapter, memory data stored at the physical memory page address of the memory data.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 26, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jie Yang, Xiaofeng Zhang
  • Patent number: 9854041
    Abstract: Technologies are described herein for reducing network traffic when replicating memory data across hosts. The memory data stored in a main memory of the host computer is replicated to a main memory of a second host computer. Memory data from the local data storage of the second host computer that is a duplicate of memory data from the main memory is identified. Instead of sending the memory data from the main memory that is duplicated, the duplicated memory is copied from the local storage to the main memory of the second host computer.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: December 26, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Brijesh Singh, Eden Grail Adogla, II
  • Patent number: 9842032
    Abstract: The subject matter of this specification can be implemented in, among other things, a method including receiving a request to create a live snapshot of a state of a virtual machine including a memory and an original disk file. The method further includes copying, by a hypervisor, data from the memory to a storage device to form a memory snapshot. The method further includes pausing the virtual machine and creating a new disk file at a reference point-in-time. The original disk file is a backing file of the new disk file. The method further includes resuming the virtual machine. The virtual machine is to perform disk operations using the new disk file after the reference point-in-time. The method further includes copying the original disk file to a disk snapshot file. The method further includes providing the live snapshot including the disk snapshot file and the memory snapshot.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: December 12, 2017
    Assignee: Red Hat, Inc.
    Inventor: Eric Blake
  • Patent number: 9836240
    Abstract: An example method of providing deduplication support for one or more memory pages includes setting, by a memory manager, an initial memory page to a write protection mode. The initial memory page is located in an address space allocated to a memory consumer. The method also includes detecting, by the memory manager, an attempted write to the initial memory page. The method further includes creating, by the memory manager, a copy of the initial memory page in response to detecting the attempted write. The method also includes discarding, based on a determination of whether to discard the initial memory page or the copy of the initial memory page, the initial memory page or the copy of the initial memory page to provide protection for memory deduplication.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: December 5, 2017
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Andrea Arcangeli
  • Patent number: 9824032
    Abstract: Systems and methods for guest page table validation by virtual machine (VM) functions. An example method comprises: storing a first VM function invocation instruction in a first memory page executable from a default memory view of a VM, wherein executing the first VM function invocation instruction switches a page table pointer to a trampoline memory view of the VM; configuring a write access permission, from the trampoline memory view, to a page table comprised by a VM page table hierarchy; storing a second VM function invocation instruction in a second memory page executable from the trampoline memory view, wherein executing the second VM function invocation instruction switches the page table pointer to an alternative memory view of the VM; storing, in the second memory page, validation instructions to validate the VM page table hierarchy; and storing protected instructions within a third memory page executable from the alternative memory view.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: November 21, 2017
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Paolo Bonzini
  • Patent number: 9817756
    Abstract: Techniques are described for enabling a virtual machine to be presented with an amount of available guest memory, where a hypervisor or other privileged component manages the mapping of the guest memory to either volatile memory (e.g., RAM) or to secondary storage (e.g., SSD). This enables volatile memory to be effectively oversubscribed to on host computing devices that have a limited amount of total available volatile memory but which are running multiple virtual machines. For example, each virtual machine on the device can be presented as having access to the total amount of available RAM that is available on the device. The hypervisor or other virtualization component then monitors the usage of the memory by each virtual machine and shapes which portions of the guest memory for that virtual machine are mapped to RAM and which portions are mapped to secondary storage, such as SSD.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: November 14, 2017
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventor: Atle Normann Jorgensen
  • Patent number: 9817592
    Abstract: A virtual disk conversion system determines location ranges for data on a storage device that are found in files representing a virtual disk in a source format. An intermediate virtual disk data structure containing the location ranges for the data is generated, and the intermediate virtual disk data structure is used to associate data at the location ranges with a new file on the storage device that represents a virtual disk in a destination format.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: November 14, 2017
    Assignee: NETAPP, INC.
    Inventors: Sunny Ratra, Sungwook Ryu, Steven Beam, Shweta Behere, Sreenivasa Potakamuri, Seema Kamat, Ben de Waal
  • Patent number: 9811365
    Abstract: A method of migrating applications from an enterprise-based network to a multi-tenant network of a compute service provider may include receiving a request to migrate an application running on a first virtual machine instance within the enterprise-based network. Dependencies of the application may be determined by identifying at least a second virtual machine instance within the enterprise-based network, where the at least second virtual machine instance associated with the application. Resource monitoring metrics associated with hardware resources used by the first virtual machine instance and the at least second virtual machine instance may be received. The first and at least second virtual machine instances may be migrated from the enterprise-based network to at least one virtual machine at a server within the multi-tenant network based on the monitoring metrics, thereby migrating the application from the enterprise-based network to the multi-tenant network.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: November 7, 2017
    Assignee: Amazon Technologies, Inc.
    Inventor: Apolak Borthakur
  • Patent number: 9811260
    Abstract: A system and method for ballooning with assigned devices includes inflating a memory balloon, determining whether a first memory page is locked based on information associated with the first memory page, when the first memory page is locked unlocking the first memory page and removing first memory addresses associated with the first memory page from management by an input/output memory management unit (IOMMU), and reallocating the first memory page. The first memory page is associated with a first assigned device.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: November 7, 2017
    Assignee: RED HAT ISRAEL, LTD
    Inventors: Paolo Bonzini, Michael Tsirkin
  • Patent number: 9804870
    Abstract: A processing core comprising instruction execution logic circuitry and register space. The register space to be loaded from a VMCS, commensurate with a VM entry, with information indicating whether a service provided by the processing core on behalf of the VMM is enabled. The instruction execution logic to, in response to guest software invoking an instruction: refer to the register space to confirm that the service has been enabled, and, refer to second register space or memory space to fetch input parameters for said service written by said guest software.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Barry E. Huntley, Ravi L. Sahita, Vedvyas Shanbhogue, Jason W. Brandt
  • Patent number: 9804871
    Abstract: A processing core comprising instruction execution logic circuitry and register space. The register space to be loaded from a VMCS, commensurate with a VM entry, with information indicating whether a service provided by the processing core on behalf of the VMM is enabled. The instruction execution logic to, in response to guest software invoking an instruction: refer to the register space to confirm that the service has been enabled, and, refer to second register space or memory space to fetch input parameters for said service written by said guest software.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Barry E. Huntley, Ravi L. Sahita, Vedvyas Shanbhogue, Jason W. Brandt
  • Patent number: 9798634
    Abstract: A failover manager may be configured to determine a plurality of tenants executable on a server of a plurality of servers, each tenant being a virtual machine executable on the server in communication with at least one corresponding user. The failover manager may include a replicated tenant placement selector configured to dispatch a first replicated tenant for a first tenant of the plurality of tenants to a first standby server of the plurality of servers, and configured to dispatch a second replicated tenant for a second tenant of the plurality of tenants to a second standby server of the plurality of servers. The failover manager also may include a replicated tenant loader configured to activate, based on a failure of the server, the first replicated tenant on the first standby server to replace the first tenant, and the second replicated tenant on the second standby server to replace the second tenant.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: October 24, 2017
    Assignee: SAP SE
    Inventors: Mengjiao Wang, Yu Cheng, Wen-Syan Li
  • Patent number: 9798867
    Abstract: Techniques are presented for obfuscating programs of virtual machines. On a virtual machine hosted by a physical device, a program is run that is configured to execute one or more operations. At a virtual machine manager hosted by the physical device and configured to manage the virtual machine, execution of the program is monitored to detect a trapping event that causes the virtual machine manager to take over operation of the program. Upon detecting the trapping event, a specific operation of the program is performed that differs from an operation implied by static analysis of the program.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: October 24, 2017
    Assignee: Cisco Technology, Inc.
    Inventor: Robert Krten
  • Patent number: 9794292
    Abstract: A selection of a document that includes a command and a parameter is received, and a user is caused to be associated with a policy that grants permission to execute the document. A request is received, from a requestor, to execute the document, the request including a parameter value, and the requestor is determined to be the user associated with the policy. The user is validated to have access to a resource indicated by the parameter value, and the command is caused to be executed against the resource.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 17, 2017
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Amjad Hussain, Manivannan Sundaram, Sivaprasad Venkata Padisetty, Nikolaos Pamboukas, Alan Hadley Goodman
  • Patent number: 9785374
    Abstract: Various techniques of managing storage devices in a computing system are described in this application. In one embodiment, a method includes receiving an input containing consumption data representing consumption of a storage device in one of the processing units and determining if the storage device in one of the processing units is consumed excessively. In response to determining that the storage device is consumed excessively, an indicator may be generated to indicate a potential program migration from the one of the processing units to another one of the processing units in the computing system.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: October 10, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mark Santaniello, Badriddine Khessib, Laura Caulfield, Bikash Sharma
  • Patent number: 9785366
    Abstract: A method of writing data to persistent storage includes (a) for each data block of a set of data blocks, storing data of that data block at an offset within a log segment of the persistent storage in conjunction with a logical block address (LBA) of that data block on the persistent storage, a size of the log segment being larger than a size of each data block, (b) identifying a particular log segment of the persistent storage that has become filled with data blocks, and (c) upon identifying the particular log segment as having become filled, inserting pointers to respective data blocks stored within the particular log segment into respective locations defined by the respective LBA of each respective data block within a map tree.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: October 10, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Steven Morley, Daniel Cummins, Peter Puhov, Walter O'Brien, Sudhir Srinivasan
  • Patent number: 9779240
    Abstract: Aspects of the present invention include hypervisor based security using a hypervisor to monitor a VM. In embodiments of the present invention, the information gathered by the hypervisor in the monitoring is compared against a reference image to determine if there are possible rootkits present on the VM. If there are potential rootkits, the VM can be quarantined.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 3, 2017
    Assignee: VMware, Inc.
    Inventors: Azeem Feroz, Rahul Mathias Madan, Arnold Poon, Aditi Vutukuri
  • Patent number: 9772869
    Abstract: Certain aspects direct to systems and methods for performing virtual machine (VM) management to provide efficient user login and minimize resource usage. The system includes a virtual machine server storing a hypervisor and multiple VMs, and a virtual desktop controller. The virtual desktop controller is configured to control the virtual machine server to execute the hypervisor, and to execute at least (M+S) instances of the VMs on the executed hypervisor. When the virtual desktop controller detects a current number X of the executed VMs on the executed hypervisor, the virtual desktop controller determines whether X is greater than M. If X is greater than M, the virtual desktop controller controls the virtual machine server to execute some instances unexecuted VMs as the spare VMs on the hypervisor, such that S instances of the spare VMs are available to provide efficient user login.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: September 26, 2017
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Brandon Burrell, Muthukkumaran Ramalingam
  • Patent number: 9760394
    Abstract: Generally described, aspects of the present disclosure relate to a live update process of the virtual machine monitor during the operation of the virtual machine instances. An update to a virtual machine monitor can be a difficult process to execute because of the operation of the virtual machine instances. Generally, in order to update the virtual machine monitor, the physical computing device needs to be rebooted, which interrupts operation of the virtual machine instances. The live update process provides for a method of updating the virtual machine monitor without rebooting the physical computing device.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 12, 2017
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Anthony Nicholas Liguori, Matthew Shawn Wilson, Ian Paul Nowland
  • Patent number: 9753754
    Abstract: A virtual machine monitor (VMM) is configured to enforce deterministic execution of virtual machines in a multiprocessor machine. The VMM is configured to ensure that any communication by physical processors via shared memory is deterministic. When such VMMs are implemented in a distributed environment of multiprocessor machines coupled via a logical communication link, non-deterministic server applications running on virtual machines using the VMM may be replicated.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: September 5, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jonathan R. Howell, Eric Traut, Jacob R. Lorch, John R. Douceur
  • Patent number: 9754561
    Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: September 5, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Jonathan Dunaisky, Henry Packard Moreton, Jeffrey A. Bolz, Yury Y. Uralsky, James Leroy Deming, Rui M. Bastos, Patrick R. Brown, Amanpreet Grewal, Christian Amsinck, Poornachandra Rao, Jerome F. Duluk, Jr., Andrew J. Tao
  • Patent number: 9742841
    Abstract: First and second machines execute a plurality of distributed processes. A storing unit stores therein progress information of a process executed by the first machine. A calculating unit transmits the progress information to the second machine upon receiving a reassignment instruction indicating reassignment of the process to the second machine. The calculating unit transmits data to be used in the process to the second machine together with the progress information upon receiving the data during the transmission of the progress information. Upon receiving the progress information and the data, the second machine executes the process reassigned from the first machine using the progress information and the data.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: August 22, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Nobutaka Imamura
  • Patent number: 9720791
    Abstract: In an approach for testing the operations of a host system during a host system migration, a terminal agent exchanges messages already exchanged between the current host system and a terminal with the new host system. A manual operation replay unit replays messages generated by manual operations among the messages sent to the current host system by the terminal. An automatic response unit automatically generates a response message for messages received from the new host system. The automatic response unit also generates screen data for a screen displayed on the terminal on the basis of messages received from the new host system. A comparison unit compares and evaluates screen data generated by the automatic response unit and screen data from a screen generated by the terminal on the basis of messages received from the current host system.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Masahiko Kosuda, Toshio Nakamura
  • Patent number: 9715400
    Abstract: Techniques are described for importing and using virtual machine images in configured manners, such as by a virtual machine image importation service on behalf of clients. An image may be retrieved based on a client-provided location, and various characteristics of the image may be identified via application of multiple heuristic or other assessment tests to various aspects of the retrieved image such as a master boot record, filesystem, or directory structure of the image to determine a testing vector that is compared to identification vectors associated with known operating systems, in order to automatically determine a specific operating system installed on the image to be imported. Modifications may be made to drivers, configuration and system files of the retrieved image based on the identified operating system and other image characteristics.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 25, 2017
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Ekanth Sethuramalingam, Amita Ekbote, Hari Subramanian, Nagaraju Shiramshetti, Sudharsan Balakrishnan Sripadham, Raviprasad Venkatesha Murthy Mummidi, Sophia Yeemei Tsang
  • Patent number: 9710246
    Abstract: Using stored information about the compilation environment during compilation of a code segment to improve performance of just-in-time compilers. A set of characteristic(s) of a compilation environment is measured during compilation of a code segment. Information that may be relevant to how the compilation is performed is derived from at least one of the measured characteristics and stored in a persistent storage device. Upon a subsequent request to compile that code segment, the information is retrieved and used to change compilation behavior. The set of characteristic(s) relate to at least either compilation backlog or peak memory usage. The changed compilation behavior involves at least adjusting the scheduling of the subsequent compilation request or adjusting the compiler optimization level.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventor: Marius Pirvu
  • Patent number: 9703723
    Abstract: In an environment in which a processor operates a hypervisor and multiple guest partitions operating under the hypervisor's control, it is desirable to allow a guest partition access to a physical memory device without decreasing system performance. Accordingly, a conversion instruction for converting a logical address to a real address, i.e., an LTOR instruction, executable from a guest partition, is added to the processor. Upon the guest partition's execution of the conversion instruction with the logical address specified, the processor converts the logical address to an encrypted real address, and returns it to the guest partition. The guest partition is then able to pass the encrypted real address to an accelerator that converts the encrypted real address to a real address in order to access the memory device using the real address.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Masanori Mitsugi, Hiroyuki Tanaka
  • Patent number: 9703948
    Abstract: A processor includes a decode unit to decode a return target restrictive return from procedure (RTR return) instruction. A return target restriction unit is responsive to the RTR return instruction to determine whether to restrict an attempt by the RTR return instruction to make a control flow transfer to an instruction at a return address corresponding to the RTR return instruction. The determination is based on compatibility of a type of the instruction at the return address with the RTR return instruction and based on compatibility of first return target restrictive information (RTR information) of the RTR return instruction with second RTR information of the instruction at the return address. A control flow transfer unit is responsive to the RTR return instruction to transfer control flow to the instruction at the return address when the return target restriction unit determines not to restrict the attempt.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventor: Paul Caprioli
  • Patent number: 9703905
    Abstract: The present invention provides a method and a system for simulating multiple processors in parallel, and a scheduler. In this embodiment, the scheduler maps debug interface information of a to-be-simulated processor requiring debugging onto the scheduler during parallel simulation of multiple processors, so that the scheduler is capable of debugging, by using a master thread, the to-be-simulated processor requiring debugging via a debug interface of the to-be-simulated processor requiring debugging pointed by the debug interface information, thereby implementing debugging during parallel simulation of multiple processors.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 11, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Handong Ye, Jiong Cao, Xiaochun Ye, Da Wang
  • Patent number: 9697142
    Abstract: Execution-Aware Memory protection technologies are described. A processor includes a processor core and a memory protection unit (MPU). The MPU includes a memory protection table and memory protection logic. The memory protection table defines a first protection region in main memory, the first protection region including a first instruction region and a first data region. The memory protection logic determines a protection violation by a first instruction when 1) an instruction address, resulting from an instruction fetch operation corresponding to the first instruction, is not within the first instruction region or 2) a data address, resulting from an execute operation corresponding to the first instruction, is not within the first data region.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Patrick Koeberl, Steffen Schulz
  • Patent number: 9678823
    Abstract: An apparatus includes a memory configured to hold a condition for determining whether or not to migrate a virtual machine that runs on a certain information processing apparatus included in a plurality of information processing apparatuses, to other information processing apparatus included in the plurality of information processing apparatuses, and a processor coupled to the memory and configured to when the condition is satisfied in a first information processing apparatus included in the plurality of information processing apparatuses, migrate a first virtual machine that runs on the first information processing apparatus to another information processing apparatus included in the plurality of information processing apparatuses, after migrating the first virtual machine, detect a status of an error occurring in the first information processing apparatus, and change the condition, based on the detected status of the error.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: June 13, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Tomoyuki Kumeta, Yasuhiro Kawasaki, Keita Murakami
  • Patent number: 9678910
    Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage assembly is provided. The data storage assembly includes a plurality of storage drives each comprising a PCIe host interface and solid state storage media, with each of the storage drives configured to store and retrieve data responsive to storage operations received over an associated PCIe host interface. The data storage assembly includes a PCIe switch circuit coupled to the PCIe host interfaces of the storage drives and configured to receive the storage operations issued by one or more host systems over a shared PCIe interface and transfer the storage operations for delivery to the storage drives over selected ones of the PCIe host interfaces. The data storage assembly includes holdup circuitry configured to provide power to at least the storage drives after input power is lost to the data storage assembly.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: June 13, 2017
    Assignee: Liqid Inc.
    Inventors: Jason Breakstone, Christopher Long
  • Patent number: 9678769
    Abstract: A host computing device can include a host domain that includes an agent for configuring the operation and/or functionality of virtual machine instances and/or operating systems associated with the instances, which may be heterogeneous (i.e., running different operating systems than each other). One or more data volumes associated with the host machine can include an image of an operating system. In an embodiment the agent can access the image of the operating system and configure operating system settings, add data, and/or remove data.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: June 13, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Jonathan N. Scott, Vikram V. Sahijwani, George Oliver Jenkins
  • Patent number: 9672056
    Abstract: Systems and methods for reducing redundant network transmissions in virtual machine live migration.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: June 6, 2017
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 9665398
    Abstract: A method and an apparatus for activity based execution scheduling are described. Activities may be tracked among a plurality of threads belonging to a plurality of processes running in one or more processors. Each thread may be associated with one of the activities. Each activity may be associated with one or more of the threads in one or more of the processes for a data processing task. The activities may be ordered by a priority order. A group of the threads may be identified to be associated with a particular one of the activities with highest priority based on the priority order. A thread may be selected from the identified threads for next scheduled execution in the processors.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 30, 2017
    Assignee: Apple Inc.
    Inventors: James Michael Magee, Russell A. Blaine, Daniel Allen Chimene, Vishal Patel, Shantonu Sen
  • Patent number: 9658867
    Abstract: Provided is a method of preserving object code translations of a library for future reuse by an emulator. A munmap(2) system call is intercepted from an application for unmapping a mapped library memory address. A determination is made if an entry related to the mapped library memory address is present in a first predefined data structure. If said entry is present, a determination is made if the mapped library memory address corresponds to a library text or library data. If the mapped memory address corresponds to the library text, said entry is flagged as inactive in the first predefined data structure, and an object code translation of the library text is preserved in the mapped library memory address. If the mapped library memory address corresponds to the library data, contents of the mapped address are reset to zero.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: May 23, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Deepak Sreedhar, Rajesh Kumar Chaurasia
  • Patent number: 9654411
    Abstract: A virtual machine deployment and management engine deploys virtual machines to physical host computers based on a deployment time matrix. The deployment time matrix specifies approximate amounts of time used to clone or deploy a virtual machine from every host computer to every other host computer. The virtual machine deployment and management engine selects a deployment path based on the deployment times and executes the clone or deploy operations.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: May 16, 2017
    Assignee: VMware, Inc.
    Inventors: Gururaja Hegdal, Kiran Kasala, Marichetty M.S.
  • Patent number: 9641303
    Abstract: Embodiments are provided herein for increasing low density signature space for multiplexed transmissions for a plurality of users. The embodiments include generating a virtual signature using a combination operation on a plurality of basic signatures. The generated virtual signatures are provisioned as basic resource units (BRUs) for transmissions for corresponding users. The combination operation is a row-wise or column-wise permutation for combining, in each of the virtual signatures, rows or columns of corresponding basic signatures. The rows or columns represent sequences of frequency bands at one time interval or sequences of allocated time intervals at one frequency band. Alternatively, the combination operation is intra-basic resource unit (BRU) hopping. The embodiments also include generating a plurality of BRU sets comprised of virtual signatures. Each of the BRU sets is provisioned for a corresponding user.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: May 2, 2017
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Alireza Bayesteh, Jianglei Ma, Hosein Nikopour, Zhihang Yi
  • Patent number: 9633406
    Abstract: During a process of migrating a source system into a standardized virtual environment, virtual machine instances of the source system executing in a hypervisor are snapshotted as virtual machine images in an operational repository of the hypervisor. The virtual machine images in the operational repository are short-term snapshots. From time to time during the migration process, long-term snapshots of the source system are created by checking given ones of the virtual machine images from the hypervisor operational repository into an image library as image objects.
    Type: Grant
    Filed: July 26, 2015
    Date of Patent: April 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vasanth Bala, Kamal Bhattacharya, Thomas Diethelm, Praveen Jayachandran, Lakshminarayanan Renganarayana, Marcel Schlatter, Akshat Verma, Xiaolan Zhang
  • Patent number: 9626212
    Abstract: Embodiments described herein rapidly migrate child virtual machines (VM) by leveraging shared memory resources between parent and child VMs. In a first, proactive phase, parent VMs are migrated to a plurality of potential target hosts. In a second, reactive phase, after a request is received to migrate a child VM to a selected target host, memory blocks that are unique to the child VM are migrated to the selected target host. In some examples, memory blocks are compressed and decompressed as needed. In other examples, the operation environment is modified. Aspects of the disclosure offer a high performance, resource efficient solution that outperforms traditional approaches in areas of software compatibility, stability, quality of service control, resource utilization, and more.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: April 18, 2017
    Assignee: VMware, Inc.
    Inventors: Daniel James Beveridge, Gabriel Tarasuk-Levin
  • Patent number: 9619263
    Abstract: In one embodiment, a virtual machine manager may use dynamic memory balancing and greedy ballooning to improve guest memory performance. A memory 130 may have a system memory page set with a system memory page set size associated with the virtual machine to support a guest memory page set of the virtual machine with a guest memory page set size. A processor 120 may instruct the virtual machine to execute a reduction of the guest memory page set size. The processor 120 may maintain the system memory page set size during the reduction.
    Type: Grant
    Filed: June 11, 2011
    Date of Patent: April 11, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Kevin Broas
  • Patent number: 9612976
    Abstract: In a method for managing memory pages, responsive to determining that a server is experiencing memory pressure, one or more processors identifying a first memory page in a listing of memory pages in the server. The method further includes determining whether the first memory page corresponds to a logical partition (LPAR) of the server that is scheduled to undergo an operation to migrate data stored on memory pages of the LPAR to another server. The method further includes, responsive to determining that the first memory page does correspond to a LPAR of the server that is scheduled to undergo an operation to migrate data, determining whether to evict the first memory page based on a memory page state associated with the first memory page. The method further includes, responsive to determining to evict the first memory page, evicting data stored in the first memory page to a paging space.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Keerthi B. Kumar, Swetha N. Rao
  • Patent number: 9612966
    Abstract: A virtual machine cache provides for maintaining a working set of the cache during a transfer between virtual machine hosts. In response to the transfer, a previous host retains cache data of the virtual machine, which is provided to the new host of the virtual machine. The cache data may be transferred via a network transfer.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: April 4, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Vikram Joshi, Yang Luan, Michael Brown, Bhavesh Mehta
  • Patent number: 9612975
    Abstract: Embodiments of the inventive concept can include a multi-stage mapping technique for a page cache controller. For example, a gigantic virtual page address space can be mapped to a physical page address efficiently, both in terms of time and space. An internal mapping module can implement a mapping technique for kernel virtual page address caching. In some embodiments, the mapping module can include integrated balanced skip lists and page tables for mapping sparsely populated kernel virtual page address space or spaces to physical block (i.e., page) address space or spaces. The mapping module can automatically and dynamically convert one or more sections from a skip list to a page table, or from a page table to a skip list. Thus, the kernel page cache can be extended to have larger secondary memory using volatile or non-volatile page cache storage media.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: April 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: ZiHui (Jason) Li
  • Patent number: 9606818
    Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 28, 2017
    Assignee: Qualcomm Incorporated
    Inventors: Erich James Plondke, Lucian Codrescu, Christopher Edward Koob, Piyush Patel, Thomas Andrew Sartorius
  • Patent number: 9606825
    Abstract: According to one example, a method includes with a hypervisor, detecting that a guest has executed a memory monitor command for a virtual processor, making a copy of a memory address associated with the memory monitor command, the copy being placed in hypervisor memory, and with the hypervisor, in response to detecting that the guest system has executed a wait command, executing a loop until the copy is different than the data stored in the memory address.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: March 28, 2017
    Assignee: Red Hat Israel, Ltd
    Inventors: Michael Tsirkin, Paolo Bonzini