Abstract: A method of providing virtualization services includes identifying computer programs executable as a plurality of tasks, including identifying tasks from the plurality of tasks. The method includes executing the computer programs by virtual central processing units (CPUs) in a virtual machine executed on a host hardware platform and defined to provide a virtualization platform for virtualization of a target hardware platform. This includes executing the plurality of tasks other than the identified tasks by the virtual CPUs in the virtual machine executed on CPUs of the host hardware platform, and at least partially in parallel with these tasks, executing the identified tasks on additional CPUs of the host hardware platform. The target hardware platform includes one or more CPUs for execution the plurality of tasks no greater in number than the CPUs of the host hardware platform on which the plurality of tasks other than the identified tasks are executed.

Abstract: The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, a first instruction unit, a second instruction unit, an instruction distributing unit, a data transferring controller, a buffer module and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.

Abstract: A system and method provide for mapping a virtual core of a computing system to an external computing resource and intercepting an instruction directed from an application resident on the computing system to the virtual core. The intercepted instruction may be sent to the external computing resource for processing.

Abstract: Various techniques are disclosed for offloading the processing of data packets that contain financial market data. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize financial market data in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

Abstract: Systems and methods for scalable SDN devices having ports/network interfaces mapped to cardinal flow processing (CFP) units are provided. According to one embodiment, an incoming packet is received, at a software-defined networking (SDN) switch. An ingress port on which the incoming packet was received is determined. A cardinal direction to which the ingress port is mapped is determined. Based on the determined cardinal direction, the SDN switch identifies a cardinal flow processing (CFP) unit within the SDN switch with which the determined cardinal direction is associated. The SDN switch then causes the incoming packet to be processed by the identified CFP unit.

Abstract: A parallel computer system including a plurality of processors configured to perform LU factorization in parallel, the system is configured to cause each of the plurality of processors to execute processing including: generating a first panel by integrating a plurality of row panels among panels of a matrix to be subjected to the LU-factorization, the plurality of row panels being processed by the processor, generating a second panel by integrating a plurality of column panels among the panels of the matrix, the plurality of column panels being processed by the processor, and computing a matrix product of the first panel and the second panel. In parallel with the computation of the matrix product, each processor is configured to receive or transmit a column panel to be used for computation of a subsequent matrix product from or to another processor among the plurality of processors.

Abstract: Embodiments for a processor that selectively enables and disables branch prediction are disclosed. The processor may include counters to track a number of fetched instructions, a number of branches, and a number of mispredicted branches. A misprediction threshold may be calculated dependent upon the tracked number of branches and a predefined misprediction ratio. Branch prediction may then be disabled when the number of mispredictions exceed the determined threshold value and dependent upon the branch rate.

Abstract: Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

Abstract: There are provided a system, a method and a computer program product for selecting an active data stream (a lane) while running SPMD (Single Program Multiple Data) code on SIMD (Single Instruction Multiple Data) machine. The machine runs an instruction stream over input data streams. The machine increments lane depth counters of all active lanes upon the thread-PC reaching a branch operation. The machine updates the lane-PC of each active lane according to targets of the branch operation. The machine selects an active lane and activates only lanes whose lane-PCs match the thread-PC. The machine decrements the lane depth counters of the selected active lanes and updates the lane-PC of each active lane upon the instruction stream reaching a first instruction. The machine assigns the lane-PC of a lane with a largest lane depth counter value to the thread-PC and activates all lanes whose lane-PCs match the thread-PC.

Abstract: The present disclosure describes methods and systems that monitor the utilization of computational resources. In one implementation, a system periodically measures the utilization of computational resources, determines an amount of computational-resource wastage, identifies the source of the wastage, and generates recommendations that reduce or eliminate the wastage. In some implementations, recommendations are generated based on a cost of the computational-resource wastage. The cost of computational-resource wastage can be determined from factors that include the cost of providing a computational resource, an amount of available computational resources, and the amount of actual computational-resource usage. Methods of presenting and modeling computational-resource usage and methods that associate an economic cost with resource wastage are presented.

Abstract: A network interface for a first network on chip resource capable of interfacing a data processing unit in the first resource with the network, the network interface including an output communication controller including a mechanism detecting an indicator marking an end of communication between the first resource and at least one second resource with which a communication link is set up, and a mechanism outputting a signal indicating closure of the link to be sent to the second resource, after detection of an end of communication indicator.

Abstract: High volume data processing systems and methods are provided to enable ultra-low latency processing and distribution of data. The systems and methods can be implemented to service primary trading houses where microsecond delays can significantly impact performance and value. According to one aspect, the systems and methods are configured to process data from a variety of market data sources in a variety of formats, while maintaining target latencies of less than 1 microsecond. A matrix of FPGA nodes is configured to provide ultra-low latencies while enabling deterministic and distributed processing. In some embodiments, the matrix can be configured to provide consistent latencies even during microburst conditions. Further book building operations (determination of current holdings and assets) can occur under ultra-low latency timing, providing for near instantaneous risk management, management, and execution processes, even under micro-burst conditions.

Abstract: A computer program product for performing a method comprising receiving, by a processor executing on a computing device, data to be processed from a scheduler configured to assign job data. The processor also storing the received data to be processed into a single queue, wherein the single queue is shared by the multiple virtual machines running on the physical machine, and in response to an idle virtual machine being among the multiple virtual machines, assigning, by the processor, data in the queue to the idle virtual machine to be processed by the idle virtual machine, wherein storing the received data to be processed into a single queue comprises parsing the received data to be processed and storing data to be processed, which is determined as specific to a predetermined application after the parsing, into the single queue.

Abstract: Methods, apparatuses, and computer program products for collective operation management in a parallel computer are provided. Embodiments include a parallel computer having a plurality of compute nodes coupled for data communications over a data communications network. Embodiments include a first compute node entering a collective operation. Each compute node of the plurality of compute nodes is associated with the collective operation. In response to entering the collective operation, the first compute node decreases power consumption of the first compute node.

Abstract: Methods, apparatuses, and computer program products for collective operation management in a parallel computer are provided. Embodiments include a parallel computer having a plurality of compute nodes coupled for data communications over a data communications network. Embodiments include a first compute node entering a collective operation. Each compute node of the plurality of compute nodes is associated with the collective operation. In response to entering the collective operation, the first compute node decreases power consumption of the first compute node.

Abstract: A system includes a removable or replaceable I/O interface (e.g., a panel and associated electronics card). In one embodiment, a security device includes an FPGA I/O array that can be programmed for different interfaces. The interchangeable I/O panel and card is designed with a selected interface's matching physical electronics and connectors. This permits the main physical chassis of a security device to remain unchanged and avoid re-design, so that a user can readily use different interface options that can be changed by the user.

Abstract: A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfaces and an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations is known before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate times write-enable inputs of configuration registers are disabled.

Abstract: The present invention relates to a computation cell and a self-healing, fault-tolerant FPGA architecture and, more particularly, to a computation cell and an FPGA including the same, which can detect a transient internal error or permanent internal error by inputting an original function and a spare function and comparing a prestored error detection code with a generated error detection code signal. The computation cell and the self-healing, fault-tolerant FPGA architecture of the present invention can reconfigure stem cells and look-up tables included in the computation cell and can output a normal output signal even if a transient error or a permanent error is generated in an computation cell such that the corresponding computation cell and an computation tile can be normally operated.

Abstract: A regulated hybrid gaming system comprised of a terminal including an entertainment software controller coupled to a gaming environment multiplexer, wherein the entertainment software controller receives credit and provides an entertainment game; a real world controller provides a gambling game; and the gaming environment multiplexer which receives from a game world controller a request to couple the game world controller to the entertainment software engine providing the entertainment game; determines that the game world controller is approved for a regulatory regime; and couples the game world controller to the entertainment software controller, when the multiplexer determines that the game world controller is approved for the regulatory regime.

Abstract: Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.

Abstract: Described is an apparatus which comprises: a transmitter; an input-output (I/O) interface coupled to the transmitter; and logic to split data for transmission into a plurality of packets, wherein each packet is stored in a buffer and then transmitted via the I/O interface to a receiver, wherein the logic can vary a number of packets sent prior to the transmitter receiving an Acknowledgement (ACK) signal, and wherein the logic can vary a packet length of the number of packets.

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Abstract: Provided are systems and methods for a first process for writing messages to a shared memory (each of the messages being written to a respective buffer of the shared memory, and the messages configured to be read in a specified sequence by a second process), determining that writing of one of the messages to the shared memory has been completed and, sending, to the second process and in response to determining that writing of one of the messages to the shared memory has been completed, an offset value corresponding to a location in the shared memory, wherein the second process is configured to read one or more messages that are stored in the portion of the shared memory before the offset value. Also the second process reads one or more messages stored in buffers that reside in the portion of the shared memory before the offset value, and commits the reads.

Abstract: Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels.

Abstract: Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels.

Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed.

Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed.

Abstract: Embodiments relate to a page table including a data fetch width indicator. An aspect includes allocating a memory page in a main memory to an application. Another aspect includes creating a page table entry corresponding to the memory page in the page table. Another aspect includes determining, by a data fetch width indicator determination logic, the data fetch width indicator for the memory page. Another aspect includes sending a notification of the data fetch width indicator from the data fetch width indicator determination logic to supervisory software. Another aspect includes setting the data fetch width indicator in the page table entry by the supervisory software based on the notification. Another aspect includes, based on a cache miss in the cache memory corresponding to an address that is located in the memory page, fetching an amount of data from the memory page based on the data fetch width indicator.

Abstract: A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

Abstract: Embodiments relate to a page table including a data fetch width indicator. An aspect includes allocating a memory page in a main memory to an application. Another aspect includes creating a page table entry corresponding to the memory page in the page table. Another aspect includes determining, by a data fetch width indicator determination logic, the data fetch width indicator for the memory page. Another aspect includes sending a notification of the data fetch width indicator from the data fetch width indicator determination logic to supervisory software. Another aspect includes setting the data fetch width indicator in the page table entry by the supervisory software based on the notification. Another aspect includes, based on a cache miss in the cache memory corresponding to an address that is located in the memory page, fetching an amount of data from the memory page based on the data fetch width indicator.

Abstract: A message flow controller limits a process from passing a new message in a reliable message passing layer from a source node to at least one destination node while a total number of in-flight messages for the process meets a first level limit. The message flow controller limits the new message from passing from the source node to a particular destination node from among a plurality of destination nodes while a total number of in-flight messages to the particular destination node meets a second level limit. Responsive to the total number of in-flight messages to the particular destination node not meeting the second level limit, the message flow controller only sends a new packet from among at least one packet for the new message to the particular destination node while a total number of in-flight packets for the new message is less than a third level limit.

Abstract: A method for operating a programmable IC is disclosed. A set of circuits specified by a set of configuration data is operated in a set of programmable resources. In response to one of a set of status signals indicating an error, a value indicative of an error is stored in a respective one of a plurality of error status registers. The values stored in the plurality of error status registers are provided to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources. At least one error handling process is performed by the error handling circuit as a function of values stored in the plurality of error status registers.

Abstract: In particular embodiments, a method includes determining a data flow rate of the active connections at a proxy, comparing the data flow rate to a first pre-determined threshold value, and, when the data flow rate exceeds the first pre-determined threshold value, creating one or more new processing threads associated with the proxy.

Abstract: Exemplary method, system, and computer program product embodiments for full exploitation of parallel processors for data processing are provided. In one embodiment, by way of example only, a set of parallel processors is partitioned into disjoint subsets according to indices of the set of the parallel processors. The size of each of the disjoint subsets corresponds to a number of processors assigned to the processing of the data chunks at one of the layers. Each of the processors are assigned to different layers in different data chunks such that each of processors are busy and the data chunks are fully processed within a number of the time steps equal to the number of the layers. A transition function is devised from the indices of the set of the parallel processors at one time steps to the indices of the set of the parallel processors at a following time step.

Abstract: In some embodiments, a method includes storing a set of data point values. Each data point value from the set of data point values is associated with a compute device from a set of compute devices that are included in a data center. The method also includes receiving a selection indicative of a region of the data center. A portion of the set of compute devices is disposed within the region of the data center. The method further includes sending a signal to display a topological map that includes a set of indicators. Each indicator from the set of indicators is associated with a compute device from the portion of the set of compute devices. A characteristic of an indicator from the set of indicators is based on a data point value of a respective compute device.

Abstract: A technique for chargeback with simultaneous multithreading (SMT) by a computer is provided. One or more of an operating system and a second-level hypervisor of the computer manage a logical core configuration for simultaneous multithreading, the operating system and/or the second-level hypervisor has control over a logical core and control over logical threads on the logical core. The operating system and/or the second-level hypervisor is configures a host hypervisor to assign an entirety of the logical core to a single physical core, such that one logical core executes per physical core. The logical core is run on the single physical core on an exclusive basis for a period of time, such that the logical threads of the logical core execute on physical threads of the single physical core. A capacity use time is determined for each of the logical threads executing on the physical threads of the single physical core.

Abstract: A semiconductor integrated circuit includes: a floating point arithmetic unit that includes circuit resources over which power saving control is performed, and executes a floating point arithmetic operation; a power-control instruction control unit that receives a pre-access instruction corresponding to a floating point arithmetic operation instruction, and invalidates stepwise the power saving control over the circuit resources included in the floating point arithmetic unit to operate a part of the circuit resources in the floating point arithmetic unit; and a control unit that causes the floating point arithmetic unit to execute the floating point arithmetic operation, wherein before execution of the floating point arithmetic operation in the floating point arithmetic unit, power consumption is previously increased by the pre-access instruction.

Abstract: A heterogeneous processor architecture is described.

Abstract: Different processor cores in a computing device can support different features. In one or more embodiments, the features supported by each of multiple physical processor cores of a computing device are identified. A set of one or more features of the multiple physical processor cores to make available to virtual processor cores of the virtual machine are determined based at least in part on both the one or more features supported by each of the multiple physical processor cores and a number of virtual processor cores of the virtual machine. In additional embodiments, a multi-level scheduling model is used. An operating system level scheduler of an operating system schedules multiple applications for execution on multiple processor cores, and a user level scheduler of an application schedules application threads of that application for execution on one or more of the multiple processor cores.

Abstract: In particular embodiments, a method includes determining a data flow rate of the active connections at a proxy, comparing the data flow rate to a first pre-determined threshold value, and, when the data flow rate exceeds the first pre-determined threshold value, creating one or more new processing threads associated with the proxy.

Abstract: A method of performing collective communication in a collective communication system includes processing nodes, including: determining whether a command message, regarding one function among a broadcast function, a scatter function, and a gather function, is generated by a processor; determining a transmission order between the processing nodes by giving transmission priorities to processing nodes that do not communicate, based on a status of each of the processing nodes if it is determined that the command message regarding the one function among the broadcast function, the scatter function, and the gather function, is generated by the processor; and performing communication with respect to the command message based on the determined transmission order.

Abstract: A phase-locked loop (PLL) circuit system includes first, second, and third PLL circuits, first, second, and third multiplexer circuits coupled to the first, second, and third PLL circuits, and a majority voter circuit coupled to the first, second, and third PLL circuits, wherein the PLL circuit system provides a glitch-free output clock signal by selecting a locked PLL circuit. Each PLL circuit includes a first input for receiving a reference clock signal; a second input for receiving a feedback clock signal; a first output for providing an output clock signal; a second output for providing a lock signal; and a return path coupled between the first output and the second input. The return path can be a direct connection or a logic circuit. Each multiplexer circuit includes three lock inputs, a first clock input, a second clock input, a defeat input, and a clock output.

Abstract: A computer system and method are provided to assess a proper degree of parallelism in executing programs to obtain efficiency objectives, including but not limited to increases in processing speed or reduction in computational resource usage. This assessment of proper degree of parallelism may be used to actively moderate the requests for threads by application processes to control parallelism when those efficiency objectives would be furthered by this control.

Abstract: An inspection and modification window can be displayed within a user interface of a business application being executed in a business application inspection and modification environment. Application code relating to a current navigation point within the business application can be listed within the inspection and modification window. Modifications to the Application code can be received via one or more user inputs, and the business application can be executed from the current navigation point to test how the received modifications to the application code affect operation of the business application.

Abstract: A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.

Abstract: In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit.

Abstract: A first computing device includes a data transmission processing unit transmitting data to be transferred to another computing device to a first storage area among the plurality of storage areas, and an interrupt generating unit generating an interrupt corresponding to transmission of data by the data transmission processing unit with respect to a transmission destination of the data together with identification information specifying the storage area, and a second computing device includes an interrupt processing unit specifying from which computing device the interrupt is requested based on the identification information received together with the interrupt when receiving the interrupt, and a data receiving unit reading out data from the first storage area corresponding to the computing device specified by the interrupt processing unit among the plurality of storage areas to efficiently communicate among computing devices in an information processing apparatus including a plurality of computing devices.

Abstract: A message flow controller limits a process from passing a new message in a reliable message passing layer from a source node to at least one destination node while a total number of in-flight messages for the process meets a first level limit. The message flow controller limits the new message from passing from the source node to a particular destination node from among a plurality of destination nodes while a total number of in-flight messages to the particular destination node meets a second level limit. Responsive to the total number of in-flight messages to the particular destination node not meeting the second level limit, the message flow controller only sends a new packet from among at least one packet for the new message to the particular destination node while a total number of in-flight packets for the new message is less than a third level limit.