Abstract: An exemplary SIMD computing system comprises a SIMD processing element (SPE) configured to perform a selected operation on a portion of a processor input data word, with the operation selected by control signals read from a control memory location addressed by a decoded instruction. The SPE may comprise one or more adder, multiplier, or multiplexer coupled to the control signals. The control signals may comprise one or more bit read from the control memory. The control memory may be an M×N (M rows by N columns) memory having M possible SIMD operations and N control signals. Each instruction decoded may select an SPE operation from among N rows. A plurality of SPEs may receive the same control signals. The control memory may be rewritable, advantageously permitting customizable SIMD operations that are reconfigurable by storing in the control memory locations control signals designed to cause the SPE to perform selected operations.

Abstract: A complier produces a configuration file to configure a fracturable data path of a configurable unit in a coarse-grained reconfigurable processor to concurrently generate different address sequences generated using different address associated with different operations. The fracturable data path includes multiple computation stages respectively including a pipeline register. The compiler analyzes a first address calculation and a second address calculation and assigns a first set of stages to the first operation to generate the first address sequence and a second set of stages to the second operation to generate the second address sequence using the second set of stages, based on the analysis. A configuration file for the configurable unit is generated by the compiler that assigns the first set of stages to the first operation and the second set of stages to the second operation and includes two or more immediate values for each computation stage.

Abstract: An instruction scheduling method and an instruction scheduling system for a reconfigurable array processor. The method includes: determining whether a fan-out of a vertex in a data flow graph (DFG) is less than an actual interconnection number of a processing unit in a reconfigurable array; establishing a corresponding relationship between the vertex and a correlation operator of the processing unit; introducing a register to a directed edge, acquiring a retiming value of each vertex; arranging instructions in such a manner that retiming values of the instruction vertexes are in ascending order, and acquiring transmission time and scheduling order of the instructions; folding the DFG, placing an instruction to an instruction vertex; inserting a register and acquiring a current DFG; and acquiring a common maximum subset of the current DFG and the reconfigurable array by a maximum clique algorithm, and distributing the instructions.

Abstract: Implementations of the present disclosure are directed to systems and methods for processing headers that support multiple protocols. A header of a packet includes a bridge type (BTYPE) field that indicates the protocol of the packet. A command field of the packet is interpreted differently based on the value of the BTYPE field. Among the benefits of implementations of the present disclosure is that a single network may be used to carry packets of different protocols without the overhead of encapsulation.

Abstract: Systems, methods, and computer-readable media are provided for patient case and care complexity characterization, and detecting matches of an individual patient's record with collections of other patients' records, based on serial, longitudinal patterns, for facilitating efficient health services utilization, implementing programs to reduce complexity, preventive medicine, and risk management in health care.

Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.

Abstract: An image processing apparatus includes a processor that performs image processing and that is constructed by using a reconfigurable-circuit device whose circuit is reconfigurable. The processor is configured to acquire image data that corresponds to each of one or more small regions into which an image is divided, determine a feature of the image data that is acquired and that corresponds to each of the one or more small regions, select a circuit configuration and perform processing in accordance with the obtained feature of the image data that corresponds to each of the one or more small regions, and cause a repository to retain rendering information, which is the image data that corresponds to each of the one or more small regions and that has undergone the processing.

Abstract: A circuit for use in a processor includes a first processing channel having a first logic unit, a second processing channel having a second logic unit, and multiplexing circuitry. The multiplexing circuitry includes an input multiplexer arranged to switch between a first state in which an input of the first logic unit is coupled to an input line of the first processing channel, and a respective second state in which the input of the first logic unit is instead coupled to an input line of the second processing channel; and an output multiplexer arranged to switch between a first state in which an output line of the second processing channel is coupled to an output of the second logic unit, and a second state in which the output line of the second processing channel is instead coupled to an output of the first logic unit.

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Abstract: Embodiments include performing decompression of a file. Aspects include receiving a compressed input stream for the file and processing the compressed input stream, by two or more pipelines in parallel, to create an output vector, wherein each pipeline includes a first decoder and a second decoder. Aspects also include writing, by each of the two or more pipelines, entries onto a scratchpad in an order defined by the output vector and writing one or more entries from the scratchpad to a main history buffer based on a determination that a validity field of the one or more entries has a value of true.

Abstract: The present invention relates to methods and systems for storing and querying database entries with neuromorphic computers. The system is comprised of a plurality of encoding subsystems that convert database entries and search keys into vector representations, a plurality of associative memory subsystems that match vector representations of search keys to vector representations of database entries using spike-based comparison operations, a plurality of binding subsystems that update retrieved vector representations during the execution of hierarchical queries, a plurality of unbinding subsystems that extract information from retrieved vector representations, a plurality of cleanup subsystems that remove noise from these retrieved representations, and one or more input search key representations that propagates spiking activity through the associative memory, binding, unbinding, cleanup, and readout subsystems to retrieve database entries matching the search key.

Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.

Abstract: A data processing system comprising a plurality of processors, wherein each of the processors is configured to perform data transfer operations to transfer outgoing data to one or more others of the processors during a first of the exchange stages; receive incoming data from the one or more others of the processors during the first of the exchange stages; determine further outgoing data in dependence upon at least part of the incoming data; count an amount of at least part the incoming data received during the first of the exchange stages from the one or more others of the processors; and in response to determining that the amount of the at least part of the incoming data received has reached a predefined amount, perform data transfer operations to transfer the further outgoing data to the one or more others of the processors during a second of the exchange stages.

Abstract: Some embodiments provide a method for updating a core allocation among processes of a gateway datapath executing on a gateway computing device having multiple cores. The gateway datapath processes include a first set of data message processing processes to which a first set of the cores are allocated and a second set of processes to which a second set of the cores are allocated in a first core allocation. Based on data regarding usage of the cores, the method determines a second core allocation that allocates a third set of the cores to the first set of processes and a fourth set of the cores to the second set of processes. The method updates a load balancing operation to load balance received data messages over the third set of cores rather than the first set of cores. The method reallocates the cores from the first allocation to the second allocation.

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

Abstract: Embodiments of the present disclosure include techniques for processing neural networks. Various forms of parallelism may be implemented using topology that combines sequences of processors. In one embodiment, the present disclosure includes a computer system comprising a plurality of processor groups, the processor groups each comprising a plurality of processors. A plurality of network switches are coupled to subsets of the plurality of processor groups. A subset of the processors in the processor groups may be configurable to form sequences, and the network switches are configurable to form at least one sequence across one or more of the plurality of processor groups to perform neural network computations. Various alternative configurations for creating Hamiltonian cycles are disclosed to support data parallelism, pipeline parallelism, layer parallelism, or combinations thereof.

Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.

Abstract: The disclosed invention includes methods for linking individual software-defined radios (SDR) into a cohesive network of SDRs capable of recording a sample of radiofrequency (RF) signals emitted in an RF environment. Individual SDRs communicate with an IP network, and host a linking application that executes the recording. A user identifies a lead SDR from among the SDRs, and uses the lead SDR to task participating SDRs with reference to a clock source. Also disclosed is a system of SDRs configured to be linked into a cohesive network of SDRs capable of recording a sample of RF signals emitted in an RF environment. Embodiments of the disclosed invention include co-located and dispersed SDRs. Some embodiments use SDRs organized into a mesh network. Embodiments of the disclosed invention are configured to perform total band monitoring, total band capture, RF environment simulation, interference identification, interference simulation, and distributed quality of service evaluation of wireless networks.

Abstract: Techniques related to implementing fully convolutional networks for semantic image segmentation are discussed. Such techniques may include combining feature maps from multiple stages of a multi-stage fully convolutional network to generate a hyper-feature corresponding to an input image, up-sampling the hyper-feature and summing it with a feature map of a previous stage to provide a final set of features, and classifying the final set of features to provide semantic image segmentation of the input image.

Abstract: An Execution Array Memory Array (XarMa©) processor is described for signal processing and internet of things (IoT) applications, (pronounced sharma, that means happiness in Sanskrit). The XarMa© processor uses a 1 to K+1 adjacency network in an array of execution units. The 1 to K+1 adjacency refers to connections separately made in rows and in columns of execution unit and local file nodes, where the number of Rows?K>1 and of Columns?K>1 and K is an odd integer. Instead of a large central multi-ported register file, a distributed set of storage files local to each execution unit is used. The instruction set architecture uses instructions that specify forwarding of execution results to execution units associated with destination instructions. This execution array is scalable to support cost effective and low power high-performance application specific processing focused on target product requirements.

Abstract: Systems, apparatuses and methods may provide for technology that dynamically tunes platform features based on virtual machine runtime requirements. In one example, a first virtual machine and a second virtual machine of a cloud server platform may each be associated with one or more logical cores. The first virtual machine may have a first configuration to efficiently support a first feature setting arrangement on the associated logical cores. The second virtual machine may have a different second configuration to efficiently support a different second feature setting arrangement on the different associated logical cores. Feature settings that are specific to an application associated with a virtual machine may be determined based on application runtime requirements. Such determined feature settings may be stored as a bit mask in control fields of a virtual machine control and enforced on the logical cores associated with a given virtual machine.

Abstract: A system and method of processing instructions may comprise an application processing domain (APD) and a metadata processing domain (MTD). The APD may comprise an application processor executing instructions and providing related information to the MTD. The MTD may comprise a tag processing unit (TPU) having a cache of policy-based rules enforced by the MTD. The TPU may determine, based on policies being enforced and metadata tags and operands associated with the instructions, that the instructions are allowed to execute (i.e., are valid). The TPU may write, if the instructions are valid, the metadata tags to a queue. The queue may (i) receive operation output information from the application processing domain, (ii) receive, from the TPU, the metadata tags, (iii) output, responsive to receiving the metadata tags, resulting information indicative of the operation output information and the metadata tags; and (iv) permit the resulting information to be written to memory.

Abstract: A clock fractional divider module which is formed as, comprises or has integrated therein a dual-core lock step unit. The dual-core lock step unit is configured in order to realize a clock fractional division arrangement, mechanism or process accompanied by an error detection, recognition and/or correction arrangement, mechanism or process.

Abstract: A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.

Abstract: A method for simulating a set of instructions to be executed on a processor including performing a performance simulation of the processor over a number of simulation cycles. Modeling, in a frontend component, branch prediction and instruction cache is performed providing instructions to the instruction window, and modeling of an instruction window for the cycle is performed. From the simulation, a performance parameter of the processor is obtained without modeling a reorder buffer, issue queue(s), register renaming, load-store queue(s) and other buffers of the processor.

Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.

Abstract: A data processing method (100) for synthesizing in real time customized traffic information for a user who wants to reach a destination position from a departure position, the data processing method (100) comprising the steps of: —obtaining (103) data which define a topological graph, said topological graph being an oriented graph containing information on the connection between segments of a road network, said topological graph comprising nodes which represent points of connection between two adjacent segments and arcs which connect nodes and which correspond to road or carriageway segments; —generating (104) data which define a routes graph (Gp), the routes graph (Gp) being a subset of the topological graph, having a departure node (10) associated with the departure position, a destination node (20) associated with the destination position, intermediate nodes between the departure node (10) and the destination node (20), arcs (1-5) which connect the nodes of the routes graph to one another, the generating s

Abstract: A reconfigurable logical circuit includes a data processing unit; a memory in which plural combinations of configuration control bits are stored; and a selector unit that selectively switches the plural combinations of configuration control bits stored in the memory and supplies a selected one of the plural combinations of configuration control bits to the data processing unit to reconfigure processing contents of the data processing unit.

Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.

Abstract: Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.

Abstract: Apparatuses and methods of data processing are disclosed. An apparatus comprises two data processing clusters each having multiple data processing lanes to perform single instruction multiple data (SIMD) processing. Decoded instructions are issued to at least one of the two data processing clusters. A decoded SIMD instruction specifying a vector length which is more than the width of the data processing lanes of the first data processing cluster has a first part issued to the first data processing cluster for execution. An issuance target for a second remaining part of the decoded SIMD instruction is selected in dependence on a dynamic performance condition. When the dynamic performance condition has a first state the issuance target is the first data processing cluster and when the dynamic performance condition has a second state the issuance target is the second data processing cluster.

Abstract: Disclosed are a self-adaptive chip (100) and configuration method. The self-adaptive chip includes: a plurality of dynamically reconfigurable cells arranged in an array, each of the plurality of dynamically reconfigurable cells being capable of being dynamically reconfigured as needed to execute different operating functions and/or input-output control functions, wherein, each of the plurality of dynamically reconfigurable cells is connected to multiple neighboring dynamically reconfigurable cells, to acquire data from one or more of the multiple neighboring dynamically reconfigurable cells, and output an operation result based on the data to at least one neighboring dynamically reconfigurable cell.

Abstract: A computer-implemented method for generating program code based on one or more blocks of a block diagram in a technical computing environment including a model editor and a code generator. The method comprises opening the block diagram in the model editor, the block diagram comprising a delay block that delays a signal received by an input port for a number of periods before being emitted at an output port, determining that a composite signal is connected to the input port, and generating definitions for variables, the variables including a state buffer, a pointer and an index. The method further comprises generating loop code, the loop code comprising instructions for setting the pointer to a position in the state buffer with an offset of index, instructions for outputting elements from the state buffer, instructions for inputting the composite signal to the state buffer, and instructions for adjusting the index.

Abstract: Embodiments of the present invention provide a task scheduling method and apparatus on a heterogeneous multi-core reconfigurable computing platform. The method includes: when determining that a to-be-executed hardware task is in a ready state, adding the to-be-executed hardware task into a target hardware task queue corresponding to a function of the to-be-executed hardware task; reconfiguring, according to a priority of the to-be-executed hardware task and a usage status of multiple reconfigurable resource packages, at least one reconfigurable resource package in the multiple reconfigurable resource packages into a target intellectual property IP core that can execute the to-be-executed hardware task.

Abstract: A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.

Abstract: Methods and apparatuses relating to pipelined runtime services in spatial arrays are described.

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. At least one of the plurality of processing elements includes a plurality of control inputs.

Abstract: An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.

Abstract: An information processing method is disclosed, including: determining a module for which a design for testability (DFT) processing is needed, in a chip; establishing, in an including manner, a DFT signal transmission channel in the module for which the DFT processing is needed, and generating a channel file by using a corresponding port signal; and interpenetrating the DFT signal transmission channel layer by layer until the top layer of the chip, according to an instantiated reference relationship. An information processing device and a computer storage medium are also disclosed.

Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.

Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.

Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.

Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.

Abstract: Techniques for determining a location of an entity are described. A determination module using member profile data may determine the location of the entity. Member profile data can include information about a member's employer and the employer's location. The determination module accesses member profiles from a social network. Additionally, the determination module may create a subgroup of entity-related member profiles from the accessed member profiles. The entity-related member profiles can be associated with a specific entity. Furthermore, the determination module may determine a suggested location for the specific entity based on location information derived from the related member profiles. Moreover, the determination module may calculate a connection density for the specific entity based on connections associated with the entity-related member profiles.

Abstract: A device comprising a battery, a memory, a data acquisition circuit and a processor. The sensors may sample a current state of a dynamic process. The data acquisition circuit may have a first clock rate based on a sampling rate of the dynamic process. The data acquisition circuit may read sensor information from the sensors. The processor may have a second clock rate. The processor may process the sensor information and generate a monitoring signal based on at least one of the sensor information, a model of the dynamic process and a desired state of the dynamic process. The processor may schedule procedures for the device and determine computation times for the procedures based on context information. The second clock rate is faster than the first clock rate. The procedures are scheduled based on the sampling rate, the computation times for the procedures and opportunities to enter a standby mode to conserve power.

Abstract: In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.

Abstract: Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged.

Abstract: Systems and methods provide a processing task load and type adaptive manycore processor architecture, enabling flexible and efficient information processing. The architecture enables executing time variable sets of information processing tasks of differing types on their assigned processing cores of matching types. This involves: for successive core allocation periods (CAPs), selecting specific processing tasks for execution on the cores of the manycore processor for a next CAP based at least in part on core capacity demand expressions associated with the processing tasks hosted on the processor, assigning the selected tasks for execution at cores of the processor for the next CAP so as to maximize the number of processor cores whose assigned tasks for the present and next CAP are associated with same core type, and reconfiguring the cores so that a type of each core in said array matches a type of its assigned task on the next CAP.

Abstract: A method of operation of a computing system includes: reconfigurable hardware devices having first application fragment and second application fragment; configuring virtual bus module having virtual bus for electrically coupling the reconfigurable hardware devices; allocating a physical port in the virtual bus, based on availability, for coupling the first application fragment and the second application fragment through the virtual bus; implementing an application through the virtual bus including transferring application data between the first application fragment and the second application fragment; activating a signal buffer interface by the virtual bus module: activating a pin buffer dispatch module for storing the application data from application input buffer, and activating memory request port by roll-back table module, storing the application data, in response to the pin buffer dispatch module; and alerting a roll-back detector including dismissing the application data exceeds a roll-back threshold or

Abstract: A method of wafer-level testing of a register programmable integrated circuit may be provided. The method may comprise transforming a microcode instruction and related data from an initializing processor format into tester format data, and applying the tester format data to the integrated circuit on a wafer.