Abstract: The semiconductor device includes a controller and a plurality of dynamically reconfigurable circuits connected to one another in series below the controller to perform operations in the manner of a pipeline. The controller inputs data and reconfiguration information to the first one of the dynamically reconfigurable circuits. Each of the dynamically reconfigurable circuits includes a processing unit that performs a data computation, an updating unit that updates the reconfiguration information, and a repetition controlling unit that determines whether to repeat the computation and controls the data and the reconfiguration information.

Abstract: The execution engine is a new organization for a digital data processing apparatus, suitable for highly parallel execution of structured fine-grain parallel computations. Possible applications include many types of digital signal processing computations, such as filtering, convolution, and deconvolution, as well as many types of linear algebra operators, such as iterative and direct solvers, singular value decomposition, and constraint optimization. The invention improves energy efficiency of these structured parallel operators as compared to a regular data flow or von Neumann computer.

Abstract: Processing within a computing environment is facilitated by filtering requests of the computing environment. A processing unit that receives a request determines whether it is to perform the request. This determination is made by, for instance, comparing an identifier of the request with an identifier of the processing unit making the determination. If there is a mismatch, then the request is blocked. Other processing within the computing environment is also facilitated by selectively using buffer entries. The selection criteria is based, for instance, on identifier information.

Abstract: An electronic device including an array of addressable registers storing data. An input register connected to the array stores an input command parameter (e.g an opcode of a command) and its associated operands in one or more input registers connected to the addressable register array. A single instance of a command accesses the at least one register of the array. Based on the input command parameter, the command for all of the address operands: reads a datum of the data previously stored in at least one register, updates the datum thereby producing an updated datum, and writes the updated datum into at least one register. The command has multiple address operands referencing the one or more registers and supports two or more of the address operands being identical. The device includes logic circuitry which provides a logical output signal to the processing circuitry indicating which, if any, of the address operands are identical.

Abstract: A data processing method and apparatus, wherein control-plane data of a communication system is processed in a multicore processing element and user-plane data of the communication system is processed in the same multicore processing element.

Abstract: A microprocessor architecture comprising a microprocessor operably coupled to a plurality of registers and arranged to execute at least one instruction. The microprocessor is arranged to determine a class of data operand. The at least one instruction comprises one or more codes in a register specifier that indicates whether relative addressing or absolute addressing is used in accessing a register. In this manner, absolute and relative register addressing is supported within a single instruction word.

Abstract: Disclosed is an SIMD-type microprocessor comprising a processor element group, plural processor elements with an operation part and a register file being arranged therein and a processor element control signal generator configured to output a processor element control signal controlling an operation of the processor element, wherein a feed part configured to feed a processor element control signal output from the processor element control signal generator to the processor element is provided at a center of the processor element group.

Abstract: Provided is a parallel program execution method in which in order to reflect structural characteristics of a multithreaded processor-based parallel system, performance of the parallel loop is predicted while compiling or executing using a performance prediction model and then the parallel program is executed using an adaptive execution method.

Abstract: One embodiment of a microprocessor core capable of executing a plurality of threads substantially simultaneously includes a plurality of register resources available for use by the threads, where the register resources are fewer in number than the number threads multiplied by a number of architectural register resources required per thread, and a supervisor for allocating the register resources among the plurality of threads.

Abstract: In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled between one of the dispatch ports and one of the writeback ports. Other embodiments are described and claimed.

Abstract: A system and method for Input/Output scheduling are described herein. In one embodiment, the method includes installing a plurality of Input/Output (I/O) schedulers to schedule I/O requests for a plurality of I/O devices, wherein each of the I/O schedulers schedules I/O requests according to a different scheduling method. The method also includes scheduling one of the I/O requests with at least one of the plurality of I/O schedulers. The method also includes determining that a second I/O scheduler replaces an I/O scheduler of the plurality of I/O schedulers, installing the second I/O scheduler, and scheduling one of the I/O requests with the second scheduler.

Abstract: A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is read with a first bit length from a first bit field in the first memory unit starting at a first start point. The bit segment that has been read is stored in the first bit field in the second memory unit starting at a second start point. The first or the second start points is updated by a predetermined value and the updated start point is stored for subsequent method steps.

Abstract: A device that supports a plurality n of message objects, including a plurality of registers associated with each message object, including at least one object match ID register that contains a multi-bit object match ID field, and at least one object mask register that contains a multi-bit object mask field; and, a CAN/CAL module that processes incoming messages. The CAN/CAL module assembles a multi-bit screener ID from selected bits of each incoming message to be acceptance filtered, compares the bits comprising the screener ID with corresponding bits of the object match ID field associated with each of at least designated ones of the message objects, disregarding any bits of each object match ID field that are masked by corresponding bits of the associated object mask field, and then determines whether any of the comparisons results in a match.

Abstract: A reconfigurable processor including a plurality of reconfigurable slots, a memory, an instruction queue, a configuration selection unit, and a configuration loader. The plurality of reconfigurable slots are capable of forming reconfigurable execution units. The memory stores a plurality of steering vector processing hardware configurations for configuring the reconfigurable execution units. The instruction queue stores a plurality of instructions to be executed by at least one of the reconfigurable execution units. The configuration selection unit analyzes the dependency of instructions stored in the instruction queue to determine an error metric value for each of the steering vector processing hardware configurations indicative of an ability of a reconfigurable slot configured with the steering vector processing hardware configuration to execute the instructions in the instruction queue, and chooses one of the steering vector processing hardware configurations based upon the error metric values.

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: A hierarchical microprocessor. An embodiment of a hierarchical microprocessor includes a plurality of first-level instruction pipeline elements; a plurality of execution clusters, where each execution cluster is operatively coupled with each of the first-level instruction pipeline elements. Each execution cluster includes a plurality of second-level instruction pipeline elements, where each of the second-level instruction pipeline elements corresponds with a respective first-level instruction pipeline element, and one or more instruction execution units operatively coupled with each of the second-level instruction pipeline elements, where the microprocessor is configured to execute multiple execution threads using the plurality of first-level instruction pipeline elements and the plurality of execution clusters.

Abstract: A microprocessor which is adapted to start a second task at a predetermined time when a first task is running if a current time becomes to be equal to the predetermined time is disclosed. The microprocessor executing an instruction read out from a program address updated every time when each execution of instruction is completed, includes update ceasing means for ceasing the program address from being updated when an stopping time comes in order to abort a first task defined by a first computer program and overwriting means for overwriting the program address with an initial address of a second computer program when a predetermined time comes in order to start to execute a second task defined by the second computer program at the predetermined time.

Abstract: The present invention is a re-configurable circuit capable of reducing latency by selecting a route for skipping the FF of an operation unit and outputting data to a connection destination operation unit if an accumulated process time is below an operation cycle allocated to the operation unit. The operation unit comprises at least a selector, a flip-flop and an operator. In a program for generating configuration information for switching the configuration of the operation unit of the re-configurable circuit, the selector selects the use/non-use of the flip-flop, based on the configuration information and selector switching condition is reflected in the configuration information for determining whether to take a route for transferring data inputted to the selector to the operator or a route for transferring the data to the operator skipping the flip-flop.

Abstract: A traffic management processor includes a departure time calculator for generating a departure time for each packet, a departure time table having a plurality of rows, each having a first portion for storing the departure time for a corresponding packet and having a second portion for storing a rollover bit, and a reset circuit configured to reset the rollover bits in a predetermined time.

Abstract: The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped against a corresponding desired set of heuristics. Heuristics relating to job requests submitted by processes in the computer system are monitored and analysed. These heuristics may include the number of read and write requests, the ratio of read requests to write requests, input/output throughput, disk utilization and the average time taken for processes to submit subsequent jobs once an initial job completes. The analysed heuristics are compared to the desired sets of heuristics for the plurality of input/output schedulers to select one of the plurality of input/output schedulers.

Abstract: A data processing apparatus that reduces a fanout load of a control signal for controlling a pipeline includes a first pipeline processing portion for executing a processing in five divided stages, a second pipeline processing portion for executing a processing one stage behind the first pipeline processing portion, and a plurality of flip-flops for latching the control signals inputted to the respective stages. The second pipeline processing portion performs the processing in each stage based on delayed control signals generated by once latching the control signals inputted to the respective stages by the flip-flop, thereby reducing the fanout load and signal delay of the control signals. Moreover, a wiring length of a control line for transmitting the control signals can be set to be longer than a conventional wiring length.

Abstract: An instruction-programmable processor, such as a digital signal processor, having a level one program cache memory and instruction buffer subsystem, is disclosed. The subsystem includes a loop cache subsystem that includes a branch cache register file for storing instruction opcodes corresponding to a sequence of fetch addresses beginning with a base address. If the fetch address issued by the instruction fetch unit is a hit relative to the loop cache subsystem loop cache control logic disables reads from program data RAM in favor of accesses to the branch cache register file. The branch cache register file can be loaded with opcodes beginning with each backward branch that is a miss relative to the branch cache register file and can be loaded with opcodes beginning with backward branches that are a miss relative to the branch cache register file and that have been executed twice in succession.

Abstract: A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the instruction address, an instruction decoder decoding an instruction from said cache memory corresponding to an instruction address from said instruction address generator, an operand address generator generating an operand address in response to an output signal of said instruction decoder, and an operand cache memory having entries each storing an operand address and operand data corresponding to the operand address in its entry. The data processor executes an instruction that makes entries in both of said instruction cache memory and said operand cache memory ineffective.

Abstract: A CAN microcontroller that supports a plurality of message objects, including a processor core that runs CAN applications, and a CAN/CAL module that processes incoming messages, and a data memory. The data memory includes a first memory segment that provides a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects. The memory-mapped registers for each message object contain respective command/control fields for configuration and setup of that message object.

Abstract: A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fused instruction. The fused instruction has an opcode that represents the operation performed by the first instruction and the operation performed by the second instruction. The fused instruction has three source operands and one destination operand. Two of the three source operands are the two source operands of the first instruction, and the third source operand is the source operand of the second instruction that is not the destination operand of the first instruction. The destination operand of the fused instruction is the destination operand of the second instruction. An execution unit that can execute a fused instruction in one clock cycle is also disclosed.

Abstract: A system and method for checking and correcting soft errors in a next instruction pointer is described. In one embodiment, a parity bit is generated for a next instruction pointer that is produced in a front end of a processor. The next instruction pointer and the parity bit are staged from the front end of the processor to a back end of the processor. Another next instruction pointer is generated in the back end of the processor when an instruction corresponding to the next instruction pointer generated in the front end executes. The next instruction pointer generated in the back end is also parity protected. The next instruction pointer generated in the front end is checked for a parity error. The next instruction pointer generated in the back end is also checked for the parity error. Finally, both next instruction pointers are compared to determine if both are equal.

Abstract: A data storage system having a plurality of disk drives. Each one has a pair of bi-directional ports. A pair of directors controls the flow of data to and from the disk drives. A first fiber channel port by-pass selector section is provided. The first fiber channel by-pass selector section includes: an input/output port coupled to a first one of the directors; and, a plurality of output/input ports connected between a first one of the ports of the plurality of disk drives through a first plurality of fiber channel links. The first fiber channel port by-pass selector section is adapted to couple the first one of the directors serially to one, or ones, of the first ports of the plurality of disk drives through a first fiber channel selectively in accordance with a control signal fed to the first fiber channel by-pass selector section. The first fiber channel includes one, or more, of the first plurality of fiber channel links.

Abstract: A programmable arithmetic and logic unit (ALU) comprising a plurality of data selectors, the data selectors having corresponding data input lines; a plurality of ALU function input lines wherein the number of ALU function input lines is equal to the number of data input lines on each of the data selectors, and each ALU function input line corresponds to one data input line on each of the data selectors; wherein each of the data input lines of each of the data selectors is connected to the corresponding data input lines of each of the other data selectors and to the corresponding ALU function input line.

Abstract: A system and method of executing instructions within a counterflow pipeline processor. The counterflow pipeline processor includes an instruction pipeline, a data pipeline, a reorder buffer and a plurality of execution units. An instruction and one or more operands issue into the instruction pipeline and a determination is made at one of the execution units whether the instruction is ready for execution. If so, the operands are loaded into the execution unit and the instruction executes. The execution unit is monitored for a result and, when the result arrives, it is stored into the result pipeline. If the instruction reaches the end of the pipeline without executing it wraps around and is sent down the instruction pipeline again.

Abstract: The present invention provides techniques for coupling radio-frequency (RF) power to a metal plate in a ceramic pedestal. Perforations in the metal plate allow ceramic-to-ceramic bonding through the metal plate. The power from an RF power feed is distributed to the perforated metal plate via several electrodes that are spaced away from the centerline of the RF power feed, thus splitting power distribution. A ceramic bonding disk between the metal plate and the RF power feed provides mechanical support for the metal plate and a ceramic body to bond to through the perforations, thus reducing cracking of the metal plate and the surrounding ceramic material.

Abstract: A data processing system is provided having a main processor 4 and a coprocessor 26. When in a debug mode, the main processor 4 and the coprocessor 26 are supplied with different instructions. The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.

Abstract: A pipeline operation method and a pipeline operation device in which an operation result of an operation unit can be effectively written to a register. In the pipeline operation method and the pipeline operation device, a pipeline operation unit that can perform a pipeline operation, a non-pipeline operation unit that cannot perform a pipeline operation, and a register that is shared by the pipeline operation unit and the non-pipeline operation unit are arranged. To perform an operation while an operation result of each of the pipeline units is being written into the register, translating an instruction to the pipeline operation unit is interlocked when the writing of the operation result of the pipeline operation unit overlaps with the writing of the operation result of the non-pipeline operation unit.

Abstract: A system for transferring data in a single clock cycle between a digital signal processor (DSP) and an external memory unit and method of same. The system includes a data transfer element coupled between the external memory unit and the DSP, where the data transfer element is adapted to transfer the data between the external memory unit and the DSP in a single clock cycle. In one embodiment, the data transfer element is a coprocessor including a plurality of latch devices coupled to buses between the DSP and the memory unit. A first set of data are transferred from a first memory unit (e.g., from either the DSP internal memory unit or the external memory unit, depending on the direction of the data transfer) into the coprocessor during a first clock cycle and out of the coprocessor to a second memory unit in a second clock cycle occurring immediately after the first clock cycle.

Abstract: A digital signal processor particularly adapted for decoding digital audio. The barrel shifter of the processor includes logical circuitry, so that operations involving a combination of a logical operation and a shift, can be performed in a single pass through the combined barrel shifter/logical unit, rather than requiring separate passes through the barrel shifter and ALU, which would require more instruction cycles. The address generator of the processor, includes circuitry which concatenates the most significant bits of a base address of a table to the least significant bits of an index, to thereby rapidly generate addresses of indexed locations in a table.

Abstract: A system and method of executing instructions within a counterflow pipeline processor. The counterflow pipeline processor includes an instruction pipeline, a data pipeline, a reorder buffer and a plurality of execution units. An instruction and one or more operands issue into the instruction pipeline and a determination is made at one of the execution units whether the instruction is ready for execution. If so, the operands are loaded into the execution unit and the instruction executes. The execution unit is monitored for a result and, when the result arrives, it is stored into the result pipeline. If the instruction reaches the end of the pipeline without executing it wraps around and is sent down the instruction pipeline again.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: The present invention provides an information sharing apparatus that realizes global information sharing based on partial information which is locally released by communication. The information sharing apparatus includes information management devices each of which has a pipe management system and communicates with each other to transmit information. The pipe management system includes a pipe management part that manages a set of pipes. Each pipe has detailed items and their weights to represent a relationship between two information management devices. The pipe management system further includes a pipe retrieving part that retrieves a pipe matching a request of the user from the set of pipes managed by the pipe management part and a pipe composing part that generates a new pipe by composing retrieved pipes. The pipe management system transmits user's request to the other systems. Thereby pipes matching the request are composed to expand a pipe held by the system that originally transmitted the request.

Abstract: There is disclosed a data processing apparatus which can reduce fanout load of a control signal for controlling a pipeline. The data processing apparatus of the present invention includes a first pipeline processing portion for executing a processing in five divided stages, a second pipeline processing portion for executing a processing one stage behind the first pipeline processing portion, and a plurality of flip-flops for latching the control signals inputted to the respective stages. The second pipeline processing portion performs the processing in each stage based on delayed control signals Control-A to E generated by once latching the control signals Control-A to E inputted to the respective stages by the flip-flop. Because of this, the fanout load of the control signals Control-A to E is reduced, and signal delay of the control signals Control-A to E can be reduced.

Abstract: The processor according to the present invention includes a flag register that stores a first flag group and a second flag group. The second flag group includes the same operation flags (a carry flag and an overflow flag) as the first flag group. The processor executes first-type instructions and second-type instructions. The first-type instruction instructs to perform an operation and to update the first flag group according to the result of the operation. The second-type instruction instructs to perform an operation different from the operation in the first-type instruction and updates the second flag group according to the result of the operation.

Abstract: A hardware semaphore is one bit wide. A first hardware circuit detects one of the processes is writing a new value to the semaphore and forces the hardware semaphore to the new value written. A plurality of second hardware circuits are provided. Each second hardware circuit is associated with a separate one of the plurality of processes. Each of the particular second hardware circuit includes a detecting circuit that detects the processor with which the particular second hardware circuit is associated is attempting to write the new value to the semaphore. A circuit responsive to the detecting circuit provides the current value of the semaphore, before the write, to an output of the second particular hardware circuit.

Abstract: A digital signal processor particularly adapted for decoding digital audio. The barrel shifter of the processor includes logical circuitry, so that operations involving a combination of a logical operation and a shift, can be performed in a single pass through the combined barrel shifter/logical unit, rather than requiring separate passes through the barrel shifter and ALU, which would require more instruction cycles. The address generator of the processor, includes circuitry which concatenates the most significant bits of a base address of a table to the least significant bits of an index, to thereby rapidly generate addresses of indexed locations in a table.

Abstract: A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: Methods and systems for bit manipulation instructions are disclosed. The instruction srlmsk shifts a value stored in a first register based on a shift value stored in a second register and loads N bits from the shift register to a third register using a single instruction. The instruction concat loads the lower N bits from a first register into the high order bits of a second register and loads a subset of least significant bits of a third register to the low order bits of the second register using a single instruction. These instructions may be used to improve variable length encoding and decoding processes.

Abstract: A compression scheme is disclosed for program executables that run on Reduced Instruction Set Computer (RISC) processors, such as the PowerPC architecture. The RISC instruction set is expanded by adding opcodes to produce code that facilitates the removal of redundant fields. To compress a program, a compressor engine rewrites the executable using the new expanded instruction set. Next, a filter is applied to remove the redundant fields from the expanded instructions. A conventional compression technique such as Huffman encoding is then applied on the resulting code.

Abstract: A programmable address arithmetic unit and method for use on microprocessors, microcontrollers, and digital signal processors is described. The addressing arithmetic unit incorporates a programmable logic array or other programmable device coupled to address registers and the instruction stream, the address unit being responsive to commands in the processor's instruction set. A first set of instructions control the initialization and configuration of the address arithmetic unit logic. A second set of instructions reference operands using one or more addressing modes that calculate the operand's effective address using the logic programmed by said first set of instructions.

Abstract: A system and method of executing instructions within a counterflow pipeline processor. The counterflow pipeline processor includes an instruction pipeline, a data pipeline, a reorder buffer and a plurality of execution units. An instruction and one or more operands issue into the instruction pipeline and a determination is made at one of the execution units whether the instruction is ready for execution. If so, the operands are loaded into the execution unit and the instruction executes. The execution unit is monitored for a result and, when the result arrives, it is stored into the result pipeline. If the instruction reaches the end of the pipeline without executing it wraps around and is sent down the instruction pipeline again.

Abstract: A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit.

Abstract: A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

Abstract: A method for performing 16 Bit BIOS interrupt calls under a 32 Bit protected mode application. This has been impossible to-date and has forced BIOS development teams to add support into the BIOS for 32 bit function calls from 32 bit applications.