Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

Abstract: A method for operating a Reduced Instruction Set Computer (RISC) processor that executes mormal RISC instructions and special RISC instructions. The method comprises the step of controlling the RISC processor to perform a single operation, using a single functional unit for each RISC processor, in response to each normal RISC instruction. The method also comprises the step of controlling the RISC processor to perform multiple operations, using multiple functional units of the RISC processor in parallel, in response to each special RISC instruction.

Abstract: An information processing apparatus including a Global Positioning System (GPS) receiver for receiving a radio wave from a GPS satellite and a Reduced Instruction Set Computer (RISC) type microprocessor for processing signals corresponding to the radio wave received by the GPS receiver. The GPS receiver and RISC type microprocessor are incorporated into a single integrated circuit chip, and the RISC type microprocessor is provided with a bypass circuit which facilitates the execution of conditional branch instructions.

Abstract: The processing speed of a digital signal processor or system processor is controlled in accordance with the functions required in a task to be performed by the device, with these functions being compared to a table of maximum processing speeds at which various functions can be performed reliably by the device. This method is applied to a number of digital signal processors on a communications adapter, with a core kernel of each of these digital signal processors being driven at a processing speed controlled in this way, while peripheral functions of all these digital signal processors are performed according to a clock signal synchronized with data being received from a network transmission line.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

Abstract: A system and method is provided for use in register-based CPUs for simultaneously processing data in a series of CPU register banks while concurrently loading and unloading data into additional register banks. The register banks then sequentially shared between arithmetic processors connected to the CPU datapath. Each register bank, after being loaded with data, is connected to a plurality of data processors in sequence and the data in each register bank is processed. The data is not moved between register banks within the datapath, except when it is loaded and unloaded from the datapath. The invention takes advantage of the shorter time required to move control signals, as compared with moving data.

Abstract: An integrated RISC and relay ladder logic processor uses shared registers, program counter, bus lines, and processing circuitry to eliminate delays associated with transfer of control in co-processor type architecture. The RISC instructions do not significantly interfere with the specialized hardware needed for rapid relay logic execution, the latter which may be further improved through the use of a pipeline well suited for relay ladder logic which creates few pipeline hazards. Two levels of condition codes are used for the arithmetic and logic instructions to permit nested arithmetic operations without interference with those instructions visible to the user. Hybrid instructions are provided to synchronize the relay ladder instructions with the arithmetic instructions, thus truly integrating the two instruction sets.

Abstract: A data processor comprises a processing unit which processes an instruction in pipeline stages, the number of which is switchable between n and m, m being a larger number than n. The data processor also comprises a switching unit for switching the number of the pipeline stages of the processing unit between n and m. The switching unit comprises an indicating unit for indicating whether the data processor is in a first operating condition or in a second operating condition, depending either on the frequency of the operation clock provided for the data processor or on the power source voltage supplied to the data processor, and a pipeline control unit for ordering a processing unit to operate in n stages under the first operation condition, and for ordering the processing unit to operate in m stages under the second operating condition.

Abstract: An apparatus is provided that operates in conjunction with a processor having registers and associated caches and a memory. A load management module monitors loads that return data to the registers, including bus requests generated in response to loads that miss in one or more of the caches. A cache miss register includes entries, each of which is associated with one of the registers. A mapping module maps a bus request to a register and sets a bit in a cache miss register entry associated with the register when the bus request is directed to a higher level structure in the memory system.

Abstract: A time-shared multitask execution circuit for sharing registered digital hardware among a plurality of users is provided to achieve zero overhead switching while processing as few as 1 sample (in one clock cycle) for each user. The circuit comprises a three register bank, two switches, and a dual port RAM. On any given cycle of the clock, one register is processing data of a current user, one register is writing processed data of a prior user to the RAM, and one register is reading data of a subsequent user for processing from RAM. In this manner, processing, reading and writing are decoupled and proceed in parallel.

Abstract: An adder unit for a microprocessor, being capable, in response to a first control signal, of adding two full word data values, stored in a first storage location and in a second storage location, respectively, and being capable, in response to a second control signal, of adding in parallel four half word data values, a first half word data value and a second half word data value being stored in the first storage location at the low half and the high half thereof, respectively, and a third half word data value and a fourth half word data value being stored in the second storage location at the low half and the high half thereof, respectively. The adder unit includes a first half word adder, arranged so as to add the first half word and the third half word to provide a first sum output of the adder unit, and a first carry out signal. The adder unit also includes a second half word adder arranged so as to add the second half word and the fourth half word, with a carry-in of 0 to provide a second sum output.

Abstract: An address pipeline includes a sequence of registers for storing the memory addresses of instructions currently being processed within the different stages of an execution pipeline. In parallel with the execution pipeline, the address pipeline advances the corresponding memory addresses as the instructions are advanced through the execution pipeline. Address pipelining allows the programmer of a pipelined processor to understand the otherwise hidden operation of a pipelined processor by giving the programmer means to track instructions through the pipeline. In addition, the address pipeline includes an instruction status register for indicating whether an instruction at any given stage of the pipeline has been executed and a program counter address breakpoint register for storing the address of the instruction that actually triggers a breakpoint.

Abstract: A superscalar microprocessor defines a hierarchical structure of registers. The top level of the hierarchy includes performance critical registers and pointers to other levels of the hierarchy. A second level of the hierarchy may include special registers. Special registers may include arrays or groups of data. Special registers may be located in a special register file or remotely located throughout the microprocessor. Remote special registers are accessed via a special register bus. Resources throughout the microprocessor are defined as special registers. In this manner, resources throughout the microprocessor are accessed using special register move instructions that are handled in a manner similar to other register moves in instructions. Accordingly, adding and modifying resources within the microprocessor is transparent to the majority of the circuitry of the microprocessor. Thus, the present invention provides a uniform and flexible mechanism of communicating to resources of a microprocessor.

Abstract: A data processing apparatus having a pipeline computer architecture with an input pipeline latch is disclosed. The data processing apparatus includes an ALU that executes a plurality of processing instructions. At least some of the instructions have an immediate data format including a field for intermediate data and a field for specifying a destination for an output. The ALU uses two operands for performing at least some of the instructions having the immediate data format. The ALU conditionally accepts either the contents of the input pipeline latch or the ALU output of the previous instruction as a second operand to an immediate instruction depending on the destination specified in the destination field of the previous instruction.

Abstract: A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

Abstract: A method and apparatus for performing a system call in a system having a user privilege level and a kernel privilege level, wherein the kernel privilege level is higher than the user privilege level is disclosed. A sequence of instructions is executed at the user privilege level including a first instruction that requires a resource provided at the kernel privilege level. Control is transferred to a first procedure executing at the user privilege level by performing a near call and saving only a pointer to the first instruction. The first procedure includes a calling instruction that does not save an architectural state prior to transferring control. Control is transferred from the first procedure to a second procedure executing at the kernel privilege level. The second procedure determines the resource required by the first instruction. Control is transferred from the second procedure to a third procedure that is determined by the second procedure.

Abstract: In a microprocessor capable of carrying out instructions having different data lengths including an instruction decoder, a register, an operational circuit and a control circuit for controlling the register and the operational unit, the register is divided into a plurality of register units, and the operational circuit is divided into a plurality of operational circuits units, each of which is connected to one of the register units. The control circuit selectively operates the register units and the operation circuit units in accordance with outputs of the instruction decoder.